TWI622176B - Structure of mim capacitor and the method for fabricating the same - Google Patents

Abstract

A metal-insulator-metal (MIM) capacitor includes a first electrode layer, a second electrode layer, and an inverted T-type dielectric layer stack structure. The inverted T-type dielectric layer stack structure is formed between the first electrode layer and the second electrode layer. The above inverted T-type dielectric layer stack structure includes a vertical portion and a horizontal portion connected to the vertical portion, wherein another dielectric layer pattern is formed between the vertical portion and the horizontal portion to form the inverted T-type dielectric layer stack structure. .

Description

Structure of MIM capacitor and manufacturing method thereof

The invention relates to a capacitor, in particular to a semiconductor element having a metal-insulator-metal (MIM) capacitor.

In recent years, with the development of process technology for semiconductor integrated circuits, the minimum line width of components manufactured on semiconductor substrates has gradually been refined, and the integrated circuit density per unit area has also increased accordingly. However, due to the increase in the circuit density of the memory cell integrated circuit, the space that can be occupied by the cell capacitor for charge storage will become smaller. Therefore, it is necessary to develop a cell capacitor with an increased average capacitance per unit area.

As the density of semiconductor devices becomes higher, the cell size and operating voltage decrease. As a result, component update times tend to decrease and soft errors often occur. To overcome these limitations, it is necessary to develop a capacitor that has a higher capacitance value per single cell and can reduce leakage current.

Generally speaking, under high density, using Si ₃ N ₄ as the nitride and oxide (NO) structure of the dielectric material, the capacitance formed is not conducive to capacitive. The lack of sufficient area to obtain the required capacitance. For another example, using a metal-insulator-metal (MIM) type capacitor structure can obtain sufficient capacitance, which is one of the advantages of a MIM capacitor.

Secondly, in semiconductor integrated circuits, many mixed-signal circuits and high-frequency circuits often require the use of high-efficiency and high-speed components, such as capacitors or inductors. These components must have low series resistance, low loss, high Q, and low capacitance / resistance time constants. Generally, capacitors used in semiconductor integrated circuits include metal-insulator-silicon (MIS) capacitors or metal-insulator-silicon (MIM) capacitors. Among the MIS capacitors, since silicon is used as the lower electrode, the parasitic resistance value generated is high, which is only suitable for low-frequency circuits. In the MIM capacitor, the upper and lower electrodes are made of metal as the electrode, which can reduce the parasitic resistance value and increase the resonance frequency of the component. It is a component often used in high-frequency circuits. In addition, when manufacturing a high-frequency component structure, it must be compatible with the CMOS process to simplify the process integration.

Traditionally, MIM capacitors are formed under the first layer of metal interconnects square. Unfortunately, due to the mismatch in process conditions between the front-end and back-end processes, it is difficult to integrate the processes. Recently, it has been proposed to place MIM capacitors in multilayer metal interconnect structures. When the line width size is reduced to a certain extent, the component speed is no longer dependent only on the delay of the gate signal, but is dominated by the signal delay of the interconnect system. In order to reduce the signal delay time of the interconnect system, copper has been widely used to replace aluminum in the wire, and on the other hand, an insulating material (k <3.0) with a low dielectric value (Low-K) has been used. ) As a dielectric insulation layer (IMD) between metal wires to replace the traditional silicon dioxide to reduce the delay in capacitance. That is, during the subsequent copper process, the MIM capacitor is fabricated in an inter-metal dielectric (IMD) between metal wires.

The first figure shows a cross-sectional view of a back-end of line structure of a conventional semiconductor device. The post-process line structure includes a metal-insulating layer-metal (MIM) capacitor structure composed of a first metal layer 100, an insulating layer 101, and a second metal layer 102. The insulating layer 101 is formed between the first metal layer 100 and the second metal layer 102, and the line width of the insulating layer 101 and the second metal layer 102 is approximately the same. The insulating layer 101 is formed of a single layer of dielectric material. The patterned insulating layer 101 and the second metal layer 102 are completed through an etching process. Due to the etching process, the portion of the side 101a near the bottom of the insulating layer 101 is liable to form an undercut, which results in insulation. A portion of the side 101a of the layer 101 is prone to a junction spiking phenomenon and a leakage current is formed. As a result, the performance of the device is affected. The inter-metal wire dielectric layer 104 covers and closes the entire MIM capacitor structure. Then, vias 103a and 103b are formed in the inter-metal wire dielectric layer 104, and the vias 103a and 103b are electrically connected to the first metal layer 100 and the second metal layer 102, respectively. The metal wire 105 is formed on the inter-metal wire dielectric layer 104 and is electrically connected to the via holes 103a and 103b.

In view of the above, in the conventional MIM capacitor structure, a leakage current is generated in some cases, even when the transistor is turned off. When a leakage current is generated, for example, in a case where the voltage value of an output signal is maintained within a specific range in a logic circuit, the value of the output signal varies and therefore a misjudgment may occur. Therefore, based on the leakage current caused by the poor structure of the conventional MIM capacitor, the present invention provides a new MIM capacitor structure to improve this problem.

The invention provides a semiconductor element. The semiconductor device includes a MIM capacitor. The MIM capacitor includes a first electrode layer, a second electrode layer, and an inverted T-shaped dielectric layer stack structure. The inverted T-type dielectric layer stack structure is formed between the first electrode layer and the second electrode layer.

One object of the present invention is to reduce the leakage current of a semiconductor device, and the other object is to reduce the leakage current of a semiconductor device. The leakage current of the conductor element is reduced so that the failure of the logic circuit can be suppressed. The semiconductor element includes a logic element.

According to an aspect of the present invention, the inverted T-type dielectric layer stack structure includes a vertical portion and a horizontal portion connected to the vertical portion, and another dielectric layer pattern (etch stop layer) is formed between the vertical portion and the horizontal portion, To form the inverted T-type dielectric layer stack structure.

According to another aspect of the present invention, the line width of the horizontal portion and the etching stop layer is approximately equal to each other, and is larger than the line width of the vertical portion. The line width of the vertical portion is approximately equal to the line width of the first electrode layer.

According to an aspect of the present invention, a method for forming a MIM capacitor includes: first, forming a MIM thin film layer on a bottom layer, wherein the MIM thin film layer includes a bottom metal layer, a dielectric layer stack layer, and an upper metal layer; The dielectric layer stack is formed between the bottom metal layer and the upper metal layer. The dielectric layer stack includes at least three dielectric layers, including a first dielectric layer, a second dielectric layer, and a third dielectric layer. Electrical layer; then, patterning the third dielectric layer and the upper metal layer to form a vertical portion and an upper electrode pattern; and then patterning the first dielectric layer, the second dielectric layer, and the bottom metal layer to form A horizontal stacked layer pattern and a lower electrode pattern; wherein the vertical portion and the horizontal stacked layer pattern form an inverted T-shaped dielectric layer stacked structure.

According to another aspect of the present invention, the semiconductor device further includes a dielectric layer between metal wires to cover the MIM capacitor.

According to one aspect of the present invention, the semiconductor device further includes a plurality of through holes formed in the dielectric layer between the metal wires, wherein the plurality of through holes include two types: the first type of through holes are dielectrics between the metal wires. The upper surface of the layer to the upper surface of the first electrode layer. The second type of through-holes are from the upper surface of the dielectric layer between the metal wires through the horizontal portion to the upper surface of the second electrode layer.

According to still another aspect of the present invention, the through holes are filled with a conductive material to form a first via hole and a second via hole in the first type of via hole and the second type of via hole, respectively. The via and the second via are electrically coupled to the first electrode layer and the second electrode layer, respectively.

According to another aspect of the present invention, the thickness of the second via is approximately equal to the thickness of the first via plus the thickness of the first electrode layer and the inverted T-type dielectric layer stack structure.

According to another aspect of the present invention, the plurality of vias includes two types: the first type of vias are from the upper surface of the dielectric layer between the metal wires to the upper surface of the first electrode layer, and the second type of vias are from The upper surface of the dielectric layer between the metal wires penetrates to the lower surface. First guide holes and second guide holes are formed and connected respectively On the dielectric layer between the first electrode layer and the metal wire. The thickness of the second via is approximately equal to the thickness of the first via plus the thickness of the first electrode layer, the inverted T-shaped dielectric layer stack structure, and the second electrode layer.

According to another aspect of the present invention, the semiconductor device further includes a metal wire formed on the dielectric layer between the metal wires, the first via hole and the second via hole, wherein the metal wire is electrically coupled to the first via hole and the second via hole. .

These advantages and other advantages will make the reader understand the present invention clearly from the description of the following preferred embodiments and the scope of patent application.

100‧‧‧ first metal layer

101‧‧‧ Insulation

101a‧‧‧side

102‧‧‧Second metal layer

103a, 103b, 209a, 209b‧‧‧ guide holes

104, 200, 200a‧‧‧Dielectric layer between metal wires

105‧‧‧metal wire

201‧‧‧ bottom metal layer

201a‧‧‧ Lower electrode pattern

202‧‧‧First dielectric layer

202a‧‧‧Horizontal

203‧‧‧Second dielectric layer

203a‧‧‧Dielectric layer pattern

204‧‧‧Third dielectric layer

204a‧‧‧Vertical

205‧‧‧upper metal layer

205a‧‧‧upper electrode pattern

208‧‧‧Horizontal stacked layer pattern

210‧‧‧ metal wire

218‧‧‧ inverted T-shaped dielectric layer stack structure

234‧‧‧ Dielectric layer stack

The detailed description of the present invention and the schematic diagrams of the embodiments described below should make the present invention more fully understood; however, it should be understood that this is only used as a reference for understanding the application of the present invention, rather than limiting the invention to a specific implementation Example.

The first diagram shows a cross-sectional view of a back-end process line structure of a semiconductor device according to one of conventional techniques; the second diagram shows a cross-sectional view of a MIM thin film layer of a back-end circuit structure of a semiconductor device according to an embodiment of the present invention; the third picture A patterned cross-sectional view showing a third dielectric layer and an upper metal layer of a MIM thin film layer of a semiconductor device according to an embodiment of the present invention; the fourth figure shows an inverted T-shape of a semiconductor device according to an embodiment of the present invention A cross-sectional view of a dielectric layer stack structure and an inverted T-type MIM capacitor structure; a fifth diagram shows a cross-sectional view of a dielectric element between metal wires covering and encapsulating the inverted T-type MIM capacitor structure according to an embodiment of the present invention; FIG. 6 is a cross-sectional view showing a rear-end process circuit structure of a semiconductor device having an inverted T-type MIM capacitor structure according to an embodiment of the present invention; FIG. 7 is a diagram showing an inverted T-type according to another embodiment of the present invention A cross-sectional view of a back-end process line structure of a semiconductor element of a MIM capacitor structure.

The present invention will be described in detail herein with regard to specific embodiments of the invention and their perspectives. Such descriptions are intended to explain the structure or flow of steps of the present invention, and are intended to be illustrative and not to limit the scope of patent application of the present invention. Therefore, in addition to the specific embodiments and preferred embodiments in the description, the present invention can be widely implemented in other different embodiments. In the following detailed description, the component symbols will be marked as part of the accompanying diagrams, and will be represented in a special way that can implement this embodiment, description. Such an embodiment would illustrate enough details to enable a person of ordinary skill in the art to implement it. The reader must understand that other embodiments can also be used in the present invention, or structural, logical, and electrical changes can be made without departing from the described embodiments. Therefore, the following detailed description is not intended to be considered as a limitation; on the contrary, the embodiments included therein will be defined by the scope of the accompanying patent application. Furthermore, certain terms are used throughout the specification and accompanying patent applications to refer to specific constituent elements. Those skilled in the art will understand that semiconductor component manufacturers may refer to the same component under different names, such as an insulating layer and a dielectric layer.

The invention provides a capacitor of a semiconductor element and a manufacturing method thereof. The capacitor structure is a MIM capacitor structure, which is formed in the circuit structure of the later stage of the semiconductor element. The MIM capacitor structure is an inverted T-shaped MIM capacitor structure. The inverted T-shaped MIM capacitor structure includes an inverted T-shaped dielectric layer stack structure. The inverted T-shaped dielectric layer stack structure is formed by sequentially depositing and patterning multiple dielectric layers, thereby improving the leakage current caused by the poor structure of the conventional MIM capacitor structure. The inverted T-type dielectric layer stack structure includes a horizontal portion and a vertical portion, and the vertical portion is located above the horizontal portion. The vertical portion is located below the upper electrode pattern, and the horizontal portion is located above the lower electrode pattern. A very thin dielectric layer pattern is formed between the vertical portion and the horizontal portion, wherein the very thin dielectric layer pattern is used as an etch stop layer in one of the vertical portions.

The second figure shows a cross-sectional view of a MIM thin film layer of a rear-stage circuit structure of a semiconductor device according to an embodiment of the present invention. In one embodiment, the semiconductor element includes a logic element or a logic circuit. The overall structure of a general semiconductor device includes a front-end line structure and a rear-end line structure. The rear-end line structure is formed on the front-end line structure after the front-end line structure is completed. It can be produced by a standard semiconductor process. Regarding the formation of the subsequent circuit structure of the semiconductor device, first, a MIM thin film layer is formed on a bottom layer 200. The MIM thin film layer includes a bottom metal layer 201, a dielectric layer stack layer 234, and an upper metal layer 205. The dielectric layer stack layer 234 is formed between the bottom metal layer 201 and the upper metal layer 205, as shown in the second figure. As shown. A dielectric layer stack layer 234 is formed on the bottom metal layer 201, and an upper metal layer 205 is formed on the dielectric layer stack 234. For an embodiment, the dielectric layer stack layer 234 includes at least three dielectric layers, namely a first dielectric layer 202, a second dielectric layer (etch stop layer) 203, and a third dielectric layer 204. A second dielectric layer 203 is formed between the first dielectric layer 202 and the third dielectric layer 204. A second dielectric layer 203 is formed on the first dielectric layer 202, and a third dielectric layer 204 is formed on the second dielectric layer 203. The second dielectric layer 203 is an etch stop layer of the upper metal layer 205 and the third dielectric layer 204.

Therefore, the MIM thin film layer is formed by sequentially depositing a bottom metal layer 201, a first dielectric layer 202, a second dielectric layer 203, a third dielectric layer 204, and an upper metal layer 205 on the bottom layer 200 in this order. The second dielectric layer 203 is an etch stop layer, and its thickness is preferably 30 to 150 nm. In some embodiments, the material and thickness of the bottom metal layer 201, the first dielectric layer 202, the third dielectric layer 204, and the upper metal layer 205 may be required according to the actual application (different semiconductor elements or their characteristics). And choose or adjust. The thickness of the second dielectric layer 203 is much smaller than the thickness of the first dielectric layer 202 and the third dielectric layer 204.

In one embodiment, the bottom layer 200 is a metal interlayer dielectric (IMD). For example, a low dielectric constant material (k <3.0) is used in the dielectric layer (IMD) of the metal wire to replace the traditional silicon dioxide (k ≒ 3.9) to reduce the capacitance. delay. For example, the dielectric material of fluorinated glass (FSG) has a k value between 3.7 and .2.8. Because the physical properties and chemical properties of fluorinated glass and silicon dioxide are similar, they are highly compatible with the original process conditions. In another embodiment, the inter-metal dielectric layer (IMD) 200 includes silicon dioxide (SiO ₂ ) or borophospho glass (BPSG).

In an embodiment, the material of the upper metal layer 205 and the lower metal layer 201 is selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten silicide, tungsten nitride, copper, or aluminum, or other metals with similar properties. Or alloy. In one embodiment, the material of the first dielectric layer 202 and the third dielectric layer 204 is selected from silicon dioxide (SiO ₂ ) or nitrogen silicide (Si ₃ N ₄ ). In one embodiment, the first dielectric layer 202 and the third dielectric layer 204 may be formed by chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). The method is to form, for example, supply SiH ₄ gas, N ₂ gas and NH ₃ gas to form a nitrogen silicide (Si ₃ N ₄ ) thin film layer. In a preferred embodiment, based on the compatibility with the process of the first dielectric layer 202 and the third dielectric layer 204, the material of the second dielectric layer 203 may include silicon oxynitride (SiO _x N _y ). The formation of the above oxynitride film can be formed by methods such as chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). For example, below a temperature range, A mixed gas of SiH ₄ gas, NH ₃ gas, and N ₂ O gas is supplied to form a silicon oxynitride (SiO _x N _y ) thin film layer. In another example, in the step of forming the oxynitride film, an in-situ step is performed under a temperature range in a NH ₃ or NO gas environment, and the silicon dioxide layer is formed by a plasma. Nitriding or nitriding on the surface.

In another embodiment, the material of the second dielectric layer 203 is a high dielectric constant (Hi-K) material, such as Si ₃ N ₄ , Al ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , CeO ₂ , Dy ₂ O ₃ , Ta ₂ O ₅ , Pr ₂ O ₃ , TiO ₂ , HfO ₂ , ZrO ₂ , Ba _x Sr _1-x TiO ₃ (BST), SrBiTa ₂ O ₉ (SBT) or PbZr _x Ti _1-x O ₃ .

Please refer to the third figure. After the MIM thin film layer is formed, patterning is performed on the third dielectric layer 204 and the upper metal layer 205 by using a lithography and etching process; that is, a lithography and etching process is performed. A portion of the third dielectric layer 204 and the upper metal layer 205 on the etching stop layer are removed to form a patterned structure. For example, a standard photolithography process is used to form a first photoresist layer pattern (not shown). Then, an etching process is performed using the first photoresist layer pattern as an etching mask until the etching is performed until the etching stop layer (the second dielectric layer 203) is exposed. As a result, the vertical portion 204a of the MIM capacitor and the MIM capacitor are formed. Electrode pattern 205a. Since the etch stop layer is not etched, the thickness of the vertical portion 204a after the etching can be accurately controlled. After the etching is completed, the remaining photoresist layer is removed. The line width of the vertical portion 204a of the MIM capacitor and the electrode pattern 205a on the MIM capacitor are approximately equal. For example, the vertical portion 204a of the MIM capacitor and the electrode pattern 205a on the MIM capacitor form a first line pattern structure. In other words, in this step, only the third dielectric layer 204 of the dielectric layer stack layer 234 is patterned, and the first dielectric layer 202 and the dielectric layer 203 maintain the original thin film layers without being patterned.

Then, referring to the fourth figure, after the vertical portion 204a of the MIM capacitor and the electrode pattern 205a on the MIM capacitor are formed, the first dielectric layer 202 and the first dielectric layer 202 of the dielectric layer stack 234 are formed by a lithography and etching process. Patterning is performed on the second dielectric layer 203 and the underlying metal layer 201; that is, a lithography and etching process is performed to remove a portion of the first dielectric layer 202 and the second dielectric layer 203 and the underlying metal layer on the underlying layer 200. 201, and another patterned structure is formed. For example, a standard photolithography process is used to form a second photoresist layer pattern (not shown). Then, an etching process is performed by using the second photoresist layer pattern as an etching mask until the etching is performed until the upper surface of the bottom layer 200 is exposed. As a result, a horizontal stacked layer pattern 208 of the MIM capacitor and an electrode pattern 201a under the MIM capacitor are formed. The horizontal stacked layer pattern 208 includes a horizontal portion 202a and a dielectric layer pattern 203a. After the etching is completed, the remaining photoresist layer is removed. The line widths of the horizontal portion 202a, the dielectric layer pattern 203a, and the lower electrode pattern 201a of the MIM capacitor are approximately equal. For example, the horizontal stacked layer pattern 208 of the MIM capacitor and the electrode pattern 201a below the MIM capacitor form a second line pattern structure. The line width of the second line pattern structure is larger than the line width of the first line pattern structure.

In this step, an inverted T-type dielectric layer stack structure 218 and an inverted T-type MIM capacitor structure are formed. The inverted T-type dielectric layer stack structure 218 serves as a dielectric layer of the inverted T-type MIM capacitor structure. The inverted T-type dielectric layer stack structure 218 includes a horizontal portion 202a, a dielectric layer pattern 203a, and a vertical portion 204a, wherein the dielectric layer pattern 203a is located between the horizontal portion 202a and the vertical portion 204a. In other words, the vertical portion 204 a is a layer pattern 208 stacked vertically to form the inverted T-shaped dielectric layer stack structure 218. The line width of the horizontal portion 202a is larger than the line width of the vertical portion 204a. Therefore, the thickness of the dielectric layer 218 of the inverted T-type MIM capacitor structure includes the sum of the thicknesses of the horizontal portion 202a, the dielectric layer pattern 203a, and the vertical portion 204a. Therefore, the capacitance value of the inverted T-type MIM capacitor can be controlled by the total thickness of the inverted T-type dielectric layer stack structure 218.

The inverted T-type MIM capacitor structure includes an upper electrode pattern 205a, an inverted T-type dielectric layer stack structure 218, and a lower electrode pattern 201a. The breakdown voltage can also be controlled by the total thickness of the inverted T-type dielectric layer stack structure 218.

A dielectric layer pattern 203a separates the vertical portion 204a below the electrode pattern 205a above the MIM capacitor and the horizontal portion 202a above the electrode pattern 201a below the MIM capacitor to separate each other. Therefore, even if the vertical portion 204a is generated after etching, In the case of an undercut on the side, the undercut on the side still does not contact the lower electrode pattern 201a, so the leakage current caused by the bottom of the dielectric layer of the conventional MIM capacitor structure directly contacting the lower electrode pattern can be greatly improved. situation.

After that, please refer to the fifth figure. After the inverted T-type MIM capacitor structure is formed, a metal-to-wire dielectric layer 200a is formed on the basis of the metal-to-wire dielectric layer 200 to cover and seal the entire inverted-T MIM capacitor structure. The inter-metal wire dielectric layer 200a can be formed by a chemical vapor deposition method.

Next, referring to the sixth figure, after forming the inter-metal wire dielectric layer 200a, a lithography and etching process is used to pattern the inter-metal wire dielectric layer 200a; that is, a lithography is performed. And an etching process to remove a part of the horizontal stacked layer pattern 208 on the lower electrode pattern 201a, to remove a part of the metal interlayer dielectric layer 200a on the horizontal stacked layer pattern 208, and to remove a part of the upper electrode pattern 205a between the metal conductive lines. The dielectric layer 200a forms a plurality of through-holes in the dielectric layer 200a between the metal wires. The through-holes penetrate the horizontal stacked layer pattern 208, so that the through-holes can expose the upper surface and the upper electrode pattern 201a. The upper surface of the electrode pattern 205a. For example, a standard photolithography process is used to form a third photoresist layer pattern (not shown). Then, an etching process is performed by using the third photoresist layer pattern as an etching mask until the etching is performed until the upper surface of the lower electrode pattern 201a and the upper surface of the upper electrode pattern 205a are exposed. As a result, a plurality of through holes are formed in the metal wires. Inter-dielectric layer 200a. These vias are divided into two types: the first type of vias are from the upper surface of the inter-metal wire dielectric layer 200a to the upper surface of the upper electrode pattern 205a, and the second type of vias are from the inter-metal wire interposer. The upper surface of the electrical layer 200a penetrates the horizontal stacked layer pattern 208 (the horizontal portion 202a and the dielectric layer pattern 203a) to the upper surface of the lower electrode pattern 201a. After the etching is completed, the remaining photoresist layer is removed.

Then, a conductive material is filled in the through holes, for example, the through holes are filled with tungsten or copper to form a plurality of through holes in the first type through holes and the second type through holes, respectively. (via) 209a and 209b are in the metal interlayer dielectric layer 200a, and the via holes 209a and 209b are electrically coupled (connected) to the upper electrode pattern 205a and the lower electrode pattern 201a, respectively. In this step, the horizontal stacked layer pattern 208 of the inverted T-type dielectric layer stacked structure 218 is penetrated by the via hole 209b, as shown in the sixth figure. The depth (thickness) of the via hole 209b is approximately equal to the depth (thickness) of the via hole 209a plus the depth (thickness) of the upper electrode pattern 205a and the inverted T-type dielectric layer stack structure 218.

In another embodiment, after the inter-metal wire dielectric layer 200a is formed, patterning is performed on the inter-metal wire dielectric layer 200a by a lithography and etching process; that is, a lithography and etching process is performed. The process is to directly remove a part of the inter-metal-wire dielectric layer 200a on the inter-metal-wire dielectric layer 200 to form a plurality of through-holes in the inter-metal-wire dielectric layer 200a; the through-holes pass through the inter-metal wire dielectric The upper and lower surfaces of the electrical layer 200a. Similarly, the vias are divided into two types: the first type of vias are from the upper surface of the inter-metal wire dielectric layer 200a to the upper surface of the upper electrode pattern 205a, and the second type of vias are from the inter-metal wire interposer. The upper surface of the electrical layer 200a penetrates to the lower surface thereof. After the etching is completed, the remaining photoresist layer is removed.

Similarly, conductive materials are filled in the through holes, for example, the through holes are filled with tungsten or copper to form a plurality of conductive holes in the first type through holes and the second type through holes, respectively. The holes 209a and 209b are in the inter-metal wire dielectric layer 200a, and the via holes 209a and 209b are respectively formed and connected to the upper electrode pattern 205a and the inter-metal wire dielectric layer 200. In this step, the horizontal stacked layer pattern 208 of the inverted T-type dielectric layer stacked structure 218 is not penetrated by the via hole 209b, as shown in the seventh figure. The depth (thickness) of the via hole 209b is approximately equal to the depth (thickness) of the via hole 209a plus the depth (thickness) of the upper electrode pattern 205a, the inverted T-shaped dielectric layer stack structure 218, and the lower electrode pattern 201a.

Finally, a lithography and etching process is used to form the metal wire 210 on the inter-metal wire dielectric layer 200a and the vias 209a and 209b; the metal wire 210 is electrically coupled (connected) with the vias 209a and 209b, and the semiconductor is completed as a result Fabrication of component post-process circuit structure.

In addition to the descriptions here, different improvements that can be achieved by the examples and implementations described in the present invention should be covered in the scope of the present invention. An embodiment is an implementation or example of the present invention. An embodiment, an embodiment, some embodiments, or other embodiments described in the description refer to What is described is that a particular feature, structure, or characteristic described in connection with this embodiment is included in at least some embodiments, but not necessarily all embodiments. The embodiments of the various aspects are not necessarily the same embodiment. It should be understood that in the description of the embodiments of the present invention, various features are sometimes combined in the drawings and text descriptions of an embodiment. The purpose is to simplify the technical features of the present invention and help to understand the implementation of various aspects of the present invention. the way. In addition to the descriptions here, different improvements that can be achieved by the examples and implementations described in the present invention should be covered in the scope of the present invention. Therefore, the drawings and examples disclosed herein are intended to illustrate rather than limit the present invention, and the scope of protection of the present invention should only be based on the scope of patent applications listed below.

Claims (24)

A MIM capacitor includes: a first electrode layer; a second electrode layer; and an inverted T-type dielectric layer stack structure formed between the first electrode layer and the second electrode layer; wherein the inverted T-type dielectric layer The stacked structure includes a horizontal portion and a vertical portion, the vertical portion is located above the horizontal portion, and the horizontal portion is located above the second electrode layer; wherein the inverted T-shaped stacked structure from bottom to top is: An electrical layer; a second dielectric layer; and a third dielectric layer; wherein the second dielectric layer is an etch stop layer. The MIM capacitor according to claim 1, wherein the material of the horizontal portion and the vertical portion is selected from silicon dioxide or nitrogen silicide. The MIM capacitor according to claim 1, wherein a dielectric layer is disposed between the horizontal portion and the vertical portion. The MIM capacitor according to claim 3, wherein a line width of the dielectric layer and the horizontal portion is approximately equal to and larger than a line width of the vertical portion. The MIM capacitor according to claim 3, wherein a material of the dielectric layer is a high dielectric constant material. The MIM capacitor according to claim 5, wherein the high dielectric constant material includes SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , CeO ₂ , Dy ₂ O ₃ , Ta ₂ O ₅ , Pr ₂ O ₃ , TiO ₂ , HfO ₂ , ZrO ₂ , Ba _x Sr _1-x TiO ₃ (BST), SrBiTa ₂ O ₉ (SBT), or PbZr _x Ti _1-x O ₃ . The MIM capacitor according to claim 1 or 3, further comprising a dielectric layer between metal wires to cover the MIM capacitor. The MIM capacitor according to claim 7, further comprising a plurality of vias formed in the dielectric layer between the metal wires, wherein the plurality of vias includes a first type of vias from the dielectric layer between the metal wires. The upper surface is to the upper surface of the first electrode layer, and the second type of through hole extends from the upper surface of the dielectric layer between the metal wires through the horizontal portion to the upper surface of the second electrode layer. The MIM capacitor according to claim 8, wherein a conductive material is filled in the first type of via and the second type of via to form a first via and a second via, wherein the first via is The first electrode layer and the second electrode layer are electrically coupled to the second via hole, respectively. The MIM capacitor according to claim 9, wherein the thickness of the second via is approximately equal to the thickness of the first via plus the thickness of the first electrode layer and the stacked structure of the inverted T-type dielectric layer. The MIM capacitor according to claim 7, further comprising a plurality of vias formed in the dielectric layer between the metal wires, wherein the plurality of vias includes a first type of vias from the dielectric layer between the metal wires. The upper surface is to the upper surface of the first electrode layer, and the second type of through hole penetrates from the upper surface of the dielectric layer between the metal wires to the lower surface thereof. The MIM capacitor according to claim 11, wherein a conductive material is filled in the first type of via and the second type of via to form a first via and a second via, wherein the first via is And the second via hole are respectively formed and connected on the dielectric layer between the first electrode layer and the metal wire. The MIM capacitor according to claim 12, wherein the thickness of the second via is approximately equal to the thickness of the first via plus the first electrode layer, the inverted T-shaped dielectric layer stack structure, and the second electrode layer Of thickness. The MIM capacitor according to claim 7, further comprising a metal wire formed on the dielectric layer between the metal wires, the first via hole and the second via hole, wherein the metal wire is electrically coupled to the first via hole. With the second guide hole. The MIM capacitor according to claim 1, wherein the material of the first electrode layer and the second electrode layer is selected from tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten silicide, tungsten nitride, copper, Aluminum or alloy. A method for forming a MIM capacitor comprises: forming a bottom metal layer on a bottom dielectric layer; forming a dielectric layer stack layer on the bottom metal layer, the dielectric layer stack layer including at least a first dielectric Layers, a second dielectric layer, and a third dielectric layer; forming an upper metal layer on the dielectric layer stack layer; patterning the third dielectric layer and the upper metal layer to form a vertical portion and a An upper electrode pattern; patterning the first dielectric layer, the second dielectric layer, and the underlying metal layer to form a horizontal stacked layer pattern and a lower electrode pattern; and wherein the vertical portion and the horizontal stacked layer pattern constitute an inverted T-type dielectric layer stack structure. The method for forming a MIM capacitor according to claim 16, further comprising forming a dielectric layer between the metal wires to cover the MIM capacitor. The method for forming a MIM capacitor as described in claim 17, further comprising forming a plurality of through holes in the dielectric layer between the metal wires, wherein the plurality of through holes include a first type of through hole, The upper surface of the electrical layer to the upper surface of the upper electrode pattern, and the second type of through hole extends from the upper surface of the dielectric layer between the metal wires through the horizontal stacked layer pattern to the upper surface of the lower electrode pattern. The method for forming a MIM capacitor as described in claim 18, further comprising filling a conductive material in the first type of via and the second type of via to form a first via and a second via, wherein the The first via hole and the second via hole are electrically coupled to the upper electrode pattern and the lower electrode pattern, respectively. The method for forming a MIM capacitor as described in claim 19, wherein the thickness of the second via hole is approximately equal to the thickness of the first via hole plus the thickness of the upper electrode pattern and the inverted T-shaped dielectric layer stack structure. The method for forming a MIM capacitor as described in claim 17, further comprising forming a plurality of through holes in the dielectric layer between the metal wires, wherein the plurality of through holes include a first type of through hole, The upper surface of the electrical layer to the upper surface of the upper electrode pattern; The upper surface of the electrical layer penetrates to its lower surface. The method for forming a MIM capacitor as described in claim 21, further comprising filling a conductive material into the first type of via and the second type of via to form a first via and a second via, wherein the The first via hole and the second via hole are respectively formed and connected on the dielectric layer between the first electrode layer and the metal wire. The method of forming a MIM capacitor as described in claim 22, wherein the thickness of the second via is approximately equal to the thickness of the first via plus the upper electrode pattern, the inverted T-shaped dielectric layer stack structure, and the second The thickness of the electrode layer. The method for forming a MIM capacitor according to claim 19 or 22, further comprising forming a metal wire on the dielectric layer between the metal wires, the first via hole and the second via hole, wherein the metal wire is electrically coupled. The first guide hole and the second guide hole.