A7 B7 3769twf.doc/008 五、發明説明（（）A7 B7 3769twf.doc / 008 V. Description of the invention (()
本發明是有關於一種改善半導體元件之平坦度的製造 方法，且特別是有關於一種選擇性沈積（selectively deposited)絕緣層應用至動態隨機存取記憶體（dynamic random access memory ;以下簡稱 DRAM)或嵌入式 DRAM 的製造方法。 DRAM是一廣泛使用的積體電路元件，尤其在今日資 訊電子產業中更佔有不可或缺的地位。通常，高度積集化 的DRAM，例如大於4MB的儲存容量者，需要利用三度空 間的電容結構來實現’例如所謂的堆疊狀(stack type)或溝 槽型（trench type)電容兀件。 習知邏輯電路元件和記憶體元件是分別位於不同的 晶片上，然在目前速度要求愈來愈快的時代，已經漸漸趨 向於將兩種不同的元件同時製造於同一晶片上，以增加資 料處理的速度，此種將邏輯電路元件和記憶體元件佈局於 一晶片上的半導體元件是爲嵌入式動態隨機存取記憶體 (embedded DRAM)。 此種嵌入式DRAM可以高速存取大量的資料，對積體 電路的應用有很大的助益，其可應用於處理大量資料的邏 輯電路上’例如爲圖形處理器。一個完成的嵌入式DRAM 係包含邏輯電路、轉移場效電晶體（transfer field effect transistor ; Transfer FET)以及與轉移場效電晶體耦合的電 容器。其中，轉栘場效電晶體係作爲電容器之下電極與位 元線選擇性耦接的開關，因此可自電容器讀取資料或將資 料存入於電容器。 3 C錆先閲讀背面之注^^項存填寫本買) 裝· 訂 本紙张尺度適川中國國家標率（CNS ) Λ4規格（2丨0x297公髮） 3769twf.doc/00S ^ -—________ 五、發明説明（>) (誚先閱讀背面之注意事項再填寫本頁) 隨著半導體元件的積集度增加，電容器設計逐漸朝多 層與三度空間發展，使得電容器與其他元件區之高度差提 间’在DRAM或嵌入式DRAM之陣列區（array area)與堆 疊狀電容元件’造成過度的高拔隆起狀部份（excessive topography)。因此在後續之絕緣層沈積時，傳統之沈積法 無法達成全面性平坦化（global planarization)，甚至藉由化 學機械硏磨法（chemical mechanical polishing;以下簡稱 CMP)亦不能完全改善平坦化之程度。 有鑑於此’本發明的主要目的就是在提供一種改善半 導體元件之平坦度的製造方法，藉由沈積絕緣層於 DRAM、嵌入式Dram或堆疊狀電容元件時，能改善平坦 化之程度，更進〜步達成全面性平坦化。 依照本發明之一較佳實施例，提出一種改善半導體元 件2PS度0勺製造方法，適用在於動態隨機存取記憶體包括 下列步·驟’提供具有週邊電路區與記憶體區之基底，基底 上已形成有第—介電層，且第一介電層上形成一電容器與 基底電性親接。然後，形成一第二介電層與一第三介電層 分別覆蓋於記憶體區與周邊電路區之上，以及進行選擇性 沈積絕緣層之製程，以形成絕緣層覆蓋於第二介電層與第 三介電層’且絕緣層表面具有良好之平坦性。其中在進行 選擇性沈積絕緣層之製程時，絕緣層於第三介電層的沈積 速率’可爲絕緣層於第二介電層的沈積速率之5〜10倍。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂’下文特舉一較佳實施例，並配合所附圖式，作詳細說 ___ 4 A7 ^769twf.doc/00S 57 Λ'發明説明（3 ) 明如下： 圖式之簡單說明： ^ 第1A〜1C圖係繪示依照本發明之較佳實施例，一種 改善半導體元件之平坦度的製造流程剖面圖·，以荩 第2A〜2B圖係繪示依照本發明之較佳實施例，一種 改善半導體元件之平坦度的製造流程剖面圖。 圖式標記說明： 100、500 :半導體基底 102 :邏輯電路區 104 :記憶體區 120 :闊極The invention relates to a manufacturing method for improving the flatness of a semiconductor device, and in particular, to a selective deposited insulating layer applied to a dynamic random access memory (DRAM) or Manufacturing method of embedded DRAM. DRAM is a widely used integrated circuit component, and it has an indispensable position in today's information electronics industry. In general, highly integrated DRAMs, such as those with a storage capacity of more than 4MB, need to use a three-dimensional space capacitor structure to achieve the 'such as a so-called stack type or trench type capacitor element. It is known that logic circuit elements and memory elements are located on different chips. However, in the current era of faster and faster requirements, it has gradually become more and more common to manufacture two different components on the same chip to increase data processing. Speed, this type of semiconductor device that arranges logic circuit elements and memory elements on a chip is an embedded dynamic random access memory (embedded DRAM). Such an embedded DRAM can access a large amount of data at a high speed, which is very helpful for the application of integrated circuits. It can be applied to a logic circuit that processes a large amount of data, such as a graphics processor. A completed embedded DRAM system includes a logic circuit, a transfer field effect transistor (Transfer FET), and a capacitor coupled to the transfer field effect transistor. Among them, the transition field effect transistor system serves as a switch that selectively couples the electrodes below the capacitor to the bit line, so data can be read from the capacitor or stored in the capacitor. 3 C 锖 Please read the note on the back ^^ to save and fill in this purchase) Binding · The size of the paper is suitable for Sichuan China National Standards (CNS) Λ4 specification (2 丨 0x297) 3769twf.doc / 00S ^ -—________ 5 、 Explanation of the invention (>) (诮 Please read the notes on the back before filling this page) With the increase of the accumulation of semiconductor elements, the capacitor design gradually develops into multiple layers and three degrees of space, making the height difference between the capacitor and other component areas The improvement of the array area and the stacked capacitor element in the DRAM or the embedded DRAM caused excessive high topography. Therefore, in the subsequent deposition of the insulating layer, the conventional deposition method cannot achieve global planarization, and even the degree of planarization cannot be completely improved by chemical mechanical polishing (hereinafter referred to as CMP). In view of this, the main purpose of the present invention is to provide a manufacturing method for improving the flatness of a semiconductor device. By depositing an insulating layer on a DRAM, an embedded ram, or a stacked capacitor, the flatness can be improved, ~ Step to achieve comprehensive flattening. According to a preferred embodiment of the present invention, a method for improving the semiconductor device 2PS degree and 0 spoon is provided. The method is applicable to a dynamic random access memory including the following steps. 'Providing a substrate with a peripheral circuit area and a memory area. A first dielectric layer has been formed, and a capacitor is formed on the first dielectric layer to be electrically connected to the substrate. Then, a second dielectric layer and a third dielectric layer are formed to cover the memory region and the peripheral circuit region, respectively, and a process of selectively depositing an insulating layer is performed to form an insulating layer to cover the second dielectric layer. And the third dielectric layer 'and the surface of the insulating layer has good flatness. In the process of selectively depositing the insulating layer, the deposition rate of the insulating layer on the third dielectric layer may be 5 to 10 times the deposition rate of the insulating layer on the second dielectric layer. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and it is described in detail with the accompanying drawings ___ 4 A7 ^ 769twf.doc / 00S 57 Λ ' The description of the invention (3) is as follows: A brief description of the drawings: ^ Figures 1A to 1C are cross-sectional views of a manufacturing process for improving the flatness of a semiconductor device in accordance with a preferred embodiment of the present invention. Figure 2B is a cross-sectional view of a manufacturing process for improving the flatness of a semiconductor device according to a preferred embodiment of the present invention. Description of graphical symbols: 100, 500: semiconductor substrate 102: logic circuit area 104: memory area 120: wide pole
130a、160a:源極區 130b、160b :汲極區 140 :字元線 180 ： DRAM 200、320、350、360、506、508、509 :介電層 240 :位元線 3 00 :下電極 340 :上電極 380 :電容器 400、400a、510 :絕緣層 420 :平坦之表面 420a :全面平坦之表面 502、504 :區域 本紙张尺度適用中國囤家標冷（（，NS ) Λ4規格（210X 297公釐） (誚先閲讀背面之注意事項再填寫本頁) '裝· 订 A7 3769twf.doc/008 B7 五、發明説明（6 ) 實施例 第1A〜1C圖係繪示依照本發明之較佳實施例，一種 改善半導體元件之平坦度的製造流程剖面圖。 請參照第1A圖，於一半導體矽基底1〇〇上已形成元 件區部份，邏輯電路區102之閘極120結構、其源極區130a 與汲極區130b，介電層200以及記憶體區104之 DRAM180、其字元線140、源極區160a、汲極區160b、 位元線240與其電容器380。其中，介電層200的材質， 例如爲氧化物，用以隔離字元線140、位元線24〇與電容 器380等。且電容器380的結構包括：下電極300、介電 層320與上電極340。在邏輯電路區102上形成一介電層 3 50，例如爲多砂氧化砂（silicon rich oxide ;以下簡稱 SRO)，其例如在一充滿氧氣的環境下以化學氣相法形成， 並在記憶體區丨〇4上覆蓋有介電層360，介電層300的材 質比如爲氮化矽，具有防止電容器380上之電極，受後續 介電層中摻質的汙染，減少漏電流的產生，而降低更新週 期（refresh cycle)的次數。 請參照第1B圖，形成一絕緣層400覆蓋整個基底結 構與元件區，絕緣層400的材質比如爲氧化矽。係以臭氧 (以下簡稱 Ο;)與砂酸四乙酯（tetra-ethy 1-ortho-silicate ; 以下簡稱TEOS)爲氣源，使用次常壓,化學氣相沈積法時 (sub-atmospheric chemical vapor deposition ；以下簡稱 SACVD)。其沈積條件可調整至使絕緣層400(例如氧化 矽物質）於介電層350(例如SRO)的沈積速率，約爲絕緣層 6 ί紙张尺/1適用中國國家標苹((则八4規格（210>< 297公嫠) — ----^------裝-- - * (請先閱讀背面之注意事項再填寫本頁) 訂 A7 B7 3769twf.doc/008 五、發明説明（t ) 400於介電層360(例如氮化矽）的沈積速率之數倍， 5〜10倍。 在以〇3與TEOS爲氣源，使用SACVD，在特 件下，對於表面進行沈積反應，具有強烈之選擇& % (達番 ，照 K. Fujiino 等，於 1991 FM/C Co«/.)。因爲，跑 句鲁 Λ ^ ^ , 訂 層400之氧化矽與介電層350之SRO的性質差敫 切鲦 電層360之氮化矽爲接近，在進行SACVD時，會％ X外 者沈積速率具有選擇性。由於在對邏輯電路區102 > ^ % 層200，絕緣層4〇0之沈積速率較大，因此在相间的 時間內，邏輯電路區102之絕緣層400厚度較厚，而 了邏輯電路區102與記憶體區104之間的高低落差，使得 邏輯電路區102與記憶體區1〇4可經由絕緣層400，而提 供一平坦之表面420。 i( 請參照第1C圖，由於上述CVSACVD- TEOS沈積之 絕緣層400，已具有極良好之平坦性，再加以CMP硏磨絕 緣層400，成爲絕緣層400a後’得到全面平坦之表面 420a 〇 因爲半導體元件的積集度增加，DRAM之記憶體與其 他周圍部份（periphery)，與嵌入式DRAM之DRAM與_ 輯電路區部份，在其電容器設計朝多層與三度空間發展’ 使得電容器與其他元件區之高度差提高、，造成後續沈積之 平坦化的困難。本發明利用〇3-sacvd-teos沈積氧化砂 時，對於SRO與氮化矽之選擇性，甚至產生沈積速率爲 1〇倍的差異，並配合CMP ’達成全面平坦化的目標。 本紙張尺廋璉用中國國家標率.（rNs ) Λ4規格（210Χ 297公釐） A7 B7 3769twf.doc/008 · 五、發明説明（6) 本.發明將選擇性絕緣層的沉積應用在DRAM與嵌入 式DRAM ’以提供晶片具有一平坦的表面，而利於後續製 程之進行。 另外’亦可將本發明應用在晶片上具有大的高低落 差，而亦需具有平坦化的表面時。如第2A圖所示，在區 域502與區域504的基底500上形成有一介電層506，而 介電層5〇6在區域502與504分別具有頗大的高低落差 h ’介電層例如爲氧化物。之後，分別在表面較高的區域 502與表面較低的區域5〇4上形成介電層508、509，介電 層208爲氮化矽，而介電層509爲多矽氧化矽，再利用選 擇性沉積絕緣層的方式，而可在基底5〇〇上形成具有一平 坦表面之絕緣層510，如第2B圖所示。 綜上所述，本發明的特徵在於： 1·本發明藉由o3-sacvd-teos的方式，選擇性沈積 絕緣層於DRAM、嵌入式DRAM或堆疊狀電容元件以及具 有高低落差的晶片上’而能改善平坦化之程度，以更進〜 步達成全面性平坦化。 2. 本發明之Ο,-SACVD-TEOS的沈積法，其沈積條件 可調整至使氧伦矽物質於氧化矽的沈積速率，約爲氧化砂 物質於氣化砂的沈積速率Z數倍，甚至爲5〜1 〇倍。而本 發明選擇性沈積絕緣層的方法並不限於沉積在多矽氧化 矽與氮化矽層上，其材質只要是以〇3_SACVD-TEOS沉積 其上而具有選擇性的材質即可。 3. 本發明亦提出以氮化矽材質做爲介電層，覆蓋整個 , 8 本紙认尺度诚用中國國家標埤（（、NS)A4規格（210X297公梦 ("先閱讀背面之注意事項再填寫本頁)130a, 160a: source region 130b, 160b: drain region 140: word line 180: DRAM 200, 320, 350, 360, 506, 508, 509: dielectric layer 240: bit line 3 00: lower electrode 340 : Upper electrode 380: Capacitors 400, 400a, 510: Insulating layer 420: Flat surface 420a: Fully flat surface 502, 504: Area This paper size applies to Chinese standard cold ((, NS) Λ4 specification (210X 297 male) (%) (诮 Please read the precautions on the back before filling in this page) 'Binding · Order A7 3769twf.doc / 008 B7 V. Description of the invention (6) Example 1A ~ 1C are drawings showing the best implementation according to the present invention For example, a sectional view of a manufacturing process for improving the flatness of a semiconductor device. Referring to FIG. 1A, a device region portion, a gate 120 structure of a logic circuit region 102, and a source electrode thereof have been formed on a semiconductor silicon substrate 100. Region 130a and drain region 130b, dielectric layer 200 and DRAM 180 of memory region 104, its word line 140, source region 160a, drain region 160b, bit line 240 and its capacitor 380. Among them, dielectric layer 200 Material, such as oxide, is used to isolate word line 140, bit line 24 and electrical The capacitor 380 includes a lower electrode 300, a dielectric layer 320, and an upper electrode 340. A dielectric layer 3 50 is formed on the logic circuit area 102, for example, silicon rich oxide; SRO for short, which is formed, for example, by a chemical vapor phase method in an oxygen-filled environment, and is covered with a dielectric layer 360 on the memory region 04. The material of the dielectric layer 300 is, for example, silicon nitride, and has a prevention The electrode on the capacitor 380 is contaminated by dopants in the subsequent dielectric layer, which reduces leakage current and reduces the number of refresh cycles. Please refer to FIG. 1B to form an insulating layer 400 covering the entire base structure and In the element area, the material of the insulating layer 400 is, for example, silicon oxide. Ozone (hereinafter referred to as Ο;) and tetra-ethy 1-ortho-silicate (hereinafter referred to as TEOS) are used as gas sources, and sub-normal pressure is used. In the case of chemical vapor deposition (sub-atmospheric chemical vapor deposition; hereinafter referred to as SACVD), the deposition conditions can be adjusted so that the deposition rate of the insulating layer 400 (such as a silicon oxide substance) on the dielectric layer 350 (such as SRO) is about For insulation 6 ί Paper Rule / 1 Applicable to Chinese National Standard Ping ((The eight 8 size (210 > < 297 gong)) — ---- ^ ------ install --- * (Please read the Please fill in this page again.) Order A7 B7 3769twf.doc / 008 V. Description of the invention (t) The deposition rate of dielectric layer 360 (such as silicon nitride) is several times, 5 ~ 10 times. With 〇3 and TEOS as the gas source, using SACVD, under special features, there is a strong choice for the deposition reaction on the surface &% (Dafan, according to K. Fujiino et al., 1991 FM / C Co «/. ). Because, running properties Λ ^ ^, the properties of the silicon oxide of the ordering layer 400 and the SRO of the dielectric layer 350 are different. The silicon nitride of the cutting layer 360 is close. When performing SACVD, the deposition rate will be% X. Be selective. Since the deposition rate of the logic circuit area 102 > ^% layer 200 and the insulation layer 400 is relatively large, the thickness of the insulation layer 400 of the logic circuit area 102 is thicker in the interphase time, and the logic circuit area 102 is thicker. The level difference between the memory area 104 and the memory area 104 allows the logic circuit area 102 and the memory area 104 to pass through the insulating layer 400 to provide a flat surface 420. i (Please refer to FIG. 1C, because the insulating layer 400 deposited by the above CVSACVD-TEOS already has very good flatness, and then the CMP honing the insulating layer 400 to become the insulating layer 400a, 'a fully flat surface 420a is obtained. The accumulation of semiconductor components has increased, and the memory and other peripheral parts of DRAM, and the DRAM and _ series circuit areas of embedded DRAM have evolved in their capacitor design toward multiple layers and three degrees of space. The height difference of other element regions is increased, which makes it difficult to planarize subsequent depositions. When the present invention uses 〇3-sacvd-teos to deposit oxide sand, the selectivity for SRO and silicon nitride even produces a deposition rate of 10 times The difference between the two, and cooperate with CMP 'to achieve the goal of comprehensive flattening. The paper size is based on the Chinese national standard. (RNs) Λ4 size (210 × 297 mm) A7 B7 3769twf.doc / 008 · V. Description of the invention (6 ) This invention applies the deposition of a selective insulation layer to DRAM and embedded DRAM 'to provide a wafer with a flat surface, which is conducive to subsequent processes. In addition,' this invention can also be applied When there is a large height difference on the wafer, and a flat surface is also required. As shown in FIG. 2A, a dielectric layer 506 is formed on the substrate 500 in the region 502 and the region 504, and the dielectric layer 506 The regions 502 and 504 each have a relatively large height difference h ′, for example, the dielectric layer is an oxide. Thereafter, dielectric layers 508 and 509 are formed on the region 502 having a higher surface and the region 504 having a lower surface, respectively. The dielectric layer 208 is silicon nitride, and the dielectric layer 509 is polysilicon oxide. The insulating layer 510 having a flat surface can be formed on the substrate 500 by using the method of selectively depositing an insulating layer. As shown in Figure 2B. In summary, the present invention is characterized by: 1. The present invention selectively deposits an insulating layer on a DRAM, an embedded DRAM, or a stacked capacitor element by using a method of o3-sacvd-teos and has a high and low dropout. On the wafer, the degree of planarization can be improved, and comprehensive planarization can be further achieved. 2. In the deposition method of the 0, -SACVD-TEOS of the present invention, the deposition conditions can be adjusted so that the oxygen-silicon material is The deposition rate of silicon oxide is about The deposition rate of sand is several times, or even 5 to 10 times. The method for selectively depositing an insulating layer of the present invention is not limited to depositing on polysilicon oxide and silicon nitride layers, and the material is only required to be 〇3_SACVD- TEOS can be deposited on it with a selective material. 3. The present invention also proposes to use silicon nitride as a dielectric layer to cover the entire surface. 8 papers are certified in accordance with China's national standard ((, NS) A4 specifications). (210X297 Public Dream (" Read the notes on the back before filling this page)
、1T A7 3769twf.doc/00S B7 五、發明説明（/)) 電容器，以防止DRAM受外來汙染，並降低電容器更新 週期的次數。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 9 (誚先閲讀背面之注意事項再填寫本頁)1T A7 3769twf.doc / 00S B7 V. Description of the Invention (/)) Capacitors to prevent DRAM from external pollution and reduce the number of capacitor refresh cycles. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 9 (诮 Please read the notes on the back before filling in this page)
本紙张尺度適川中國國家標( CNS ) Λ4規格（2I〇X297公釐〉This paper is suitable for Sichuan National Standard (CNS) Λ4 specification (2I0X297mm)