3253twf/0O5 A7 B7 五、發明説明（I ) 本發明是有關於一種積體電路的製造方法，且特別是有 關於一種內連線（Interconnects)的製造方法。 隨著積體電路元件積集度的增加、金屬氧化物半導體 (Metal Oxide Semiconductor，MOS)電晶體逐漸縮小，使 得晶片的表面無法提供足夠的面積，以製作所需的內連線 時，採用兩層以上之金屬層設計的多重內連線（Multilevel Interconnect)，已成爲許多積體電路製程所採用的方式， 以用以解決晶片面積不足的問題。‘ 典型多重內連線的製作，係在MOS電晶體的主體完成 之後，在基底上建立兩層以上的金屬層，以傳導電子。而金 屬層之間則藉由金屬層間介電層（Inter-Metal Dielectic， IMD)來絕緣隔離，或是藉由金屬層間介電層中所形成的插 塞（Plug)，以連接兩金屬層，形成一個完整的迴路（Circuit)。 第1A圖至第1D圖是習知一種金屬內連線的製造流程 剖面圖。請參照第1A圖，在已形成有場效電晶體102的基 底1〇〇上，先形成一層內層介電層1〇6,然後再將其圖案化， 以形成接觸窗開口 110，裸露出場效電晶體1〇2的源極/汲極 區 104。 接著，請參照第1B圖，在接觸窗開口 110中塡入導體 材料，以形成接觸窗插塞112,與源極/汲極區104電性耦接。 其後，在基底100上形成金屬層114,使其與接觸窗插塞112 電性耦接。接著，於基底100上形成與元件表面共形的介電 層】丨6。然後，再於基底1〇〇上形成一層旋塗式物質層I〗8， 使其覆蓋介電層116表面，並且塡入金屬層1H之間的溝渠 3 本紙張尺度逋用中國國家橾準（CNS ) A4規格（2丨0父297公^^7 (請先閲讀背面之注項再填寫本莧) 訂 fty 域· 經濟部中央標準局貝工消费合作社印製 3253twf/〇〇5 3253twf/〇〇5 經濟部中央標率局貝工消費合作社印製 A7 B7 五、發明説明（> ) 中’其後再於基底100上形成一層介電層124。其中，介電 層116之材質包括富含矽氧化物（8出<;〇11以吐（^如，511〇)， 其形成的方法例如爲化學氣相沈積法；旋塗式物質層118包 括流動性氧化物（Flowing Oxide)，例如爲旋塗式玻璃（Spin on Glass ’ SOG )或氫化矽倍半氧化物（Hydrogen SilSeSqui〇xane’HSQ)等；介電層124之材質則包括氧化矽， 形成的方法例如爲化學氣相沈積法。 接著’請參照第1C圖，以化學機械硏磨法，硏磨去除 元件表面的介電層124,以使元件的表面全面性地平坦化， 完成由介電層116、旋塗式物質層118與介電層124a所共 同形成的三明治結構金屬層間介電層。然後，將介電層116、 旋塗式物質層118與介電層124a圖案化，以形成介層窗開 口（ Via Opening) 126，裸露出第一層金屬層114。 然後，請參照第1D圖，在基底100上形成一層阻障層/ 黏著層13〇,使其覆蓋介層窗開口 126所暴露的介電層116、 旋塗式物質層Π8、介電層124a與金屬層114之表面。然 後’再於基底100上形成金屬層132，使其塡滿介層窗開口 126 ’與第一層金屬層ι14電性耦接。其後，以回蝕刻或化 學機械硏磨的方式，去除介電層124a上所覆蓋的阻障層/黏 著層U0與金屬層132，使留於介層窗開口 126中的阻障層/ 黏著層130與金屬層132形成介層窗插塞134。 在上述的方法中，由於晶片表面的金屬層114的圓案密 度以及圖案彼此之間的距離並不相同，因而以化學機械硏磨 法硏磨不同位置的介電層124時，其硏磨的速度會有不同的 4 本紙張尺度逋用中國囷家橾準（CNS) A4規格（210><297公釐） (請先閲讀背面之注$項再填寫本頁) 訂_ -·<- 3253twf/00$ A7 B7 五、發明説明（今） 影響，使得硏磨的過程中，其製程的控制不易掌握’而時常 過度硏磨介電層124,使元件的表面產生凹陷的現象’以致 無法達到平坦化之目的。 此外，以上述的方法在形成介層窗開口 126之後’將造 成介層層窗開口 126所裸露的旋塗式物質層Π8產生親水性 鍵結（Hydrophilic Bond) Si-OH，而吸收水氣。而吸收水氣 之後的旋塗式物質層Π8，在後續將阻障層/黏著層BO或金 屬層132形成於介層窗開口 126的過程中，極易造成所形成 之介層窗插塞產生出氣（Outgassing)的現象，進而衍生介 層窗毒化（Poison)的問題。 另一方面，隨著積體電路的高度積集化，爲有效增加元 件的密度，目前介層窗的製作已由未接著介層窗 (Unlanded-Via)取代傳統的接著介層窗（Landed-Via)。 然而，未接著介層窗開口的形成，不但使旋塗式物質層Π8 所裸露的面積增加，吸收水氣所衍生的問題更爲嚴重，亦可 能在形成未接著介層窗開口 126的過程中，因爲蝕刻的控制 不當，過度蝕刻介電層116以及介電層116下方之內層介電 層106，而造成後續所形成之介層窗插塞134與基底100中 的其他導體層產生短路的現象。 因此本發明的目的就是在提供一種內連線的製造方法， 可以輕易地控制介電層的平坦化製程，避免由於晶片表面金 屬層的圖案密度以及圖案彼此間距離的不同，而使元件的表 面在平坦化的過程中產生凹陷現象。 本發明的另一目的是在提供一種內連線的製造方法，可 5 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公β ---------CC-------ir------.€- -- (請先閲讀背面之注$項再填寫本頁) 經濟部中夬揉率局貞工消費合作社印裝 鯉濟部中央揉準局負工消费合作社印装 3253twf/005 A7 _B7 五、發明説明（f) 以在定義介層窗開口後，防止介層窗開口所裸露之旋塗式物 質層產生親水的鍵結吸收水氣，以避免在後續製程中，造成 介層窗的出氣，而使介層窗毒化。 本發明的再一目的是在提供一種內連線的製造方法，可 以防止在定義未接著介層窗開口的製程中，由於過度触刻介 電層，而造成後續所形成之介層窗插塞與基底中的其他導體 層產生短路的現象。 根據本發明之上述目的’提出一種金屬內連線的製造方 法，此方法係在基底上形成內層介電層之後，並不直接進行 接觸窗插塞的製作，而是在內層介電層上先形成一層触刻終 止層，接著，再於內層介電層與蝕刻終止層中形成接觸窗插 塞，並進行金屬層的形成以及三明治結構的金屬層間介電層 之製作。在內層介電層與金屬層間介電層所增加的蝕刻終止 層，可以避免在後續形成介層窗開口的過程中，造成過度蝕 刻的現象。而在金屬層間介電層中，其旋塗式物質層以及氧 化層之間所增加的保護層，可以作爲硏磨氧化層的硏磨終止 層，有效控制金屬層間介電層其化學機械平坦化之製程。而 將金屬層間介電層圖案化，形成介層窗開口之後，進行離子 佈植或電漿處理，則可以破壞介層窗開口所裸露之旋塗式物 質層表面的吸水鍵結，避免在後續製程中，造成介層窗的出 氣，而使介層窗毒化。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 6 本纸張尺度逍用中國國家標準（CNS ) A4规格（210x297公釐） ---------c_.— ·(請先Mr讀背面之注^^項再填寫本頁) 訂_ 3253twf/005 A7 B7五、發明説明（7) 圖式之簡單說明： 第1A圖至第1D圖繪示習知一種內連線的製造流程剖 面圖：以及 第2A圓至第2E圓繪示依照本發明實施例，一種內連 經濟部中央橾率局貝工消费合作社印製 線的製造流程剖面圖。 圖式之標記說明： 100， 200 :基底 102， 202:場效電晶體 104， 204 :源極/汲極區 106， 206 :內層介電層 110， 210 :接觸窗開口 112, 212 :接觸窗插塞 114， 214 :金屬層 116， 124，216，224 :介電層 118， 218 :旋塗式物質層 126， 226 :介層窗開口 130， 230 :黏著/阻障層 132， 232 :金屬層 134， 234 :接觸窗插塞 208 ： 蝕刻終止層 220 ： 離子佈植 222 ： 保護層 228 ： 表面處理步驟 實施例 N.1.J/ . ---------rr------IT-------<· (諳先閲讀背面之注$項再填寫本頁) 本紙張尺度遥用中國國家標準（CNS ) A4規格（2!0X297公釐） 3253twf/〇〇5 Α7 Β7 五、發明説明（（） {請先Sijf背面之注$項再填寫本頁) 第2A圖至第2E圖繪示依照本發明一種內連線的製造 流程剖面圖。首先，請參照第2A圖，在已形成有場效電晶 體202的基底200上，先形成一層內層介電層206，然後再 於內層介電層2〇6上形成一層蝕刻終止層208。其後，將蝕 刻終止層208與內層介電層206圖案化，以形成接觸窗開口 21〇，裸露出場效電晶體202的源極/汲極區204。其中，內 層介電層206之材質包括氧化矽，形成的方法例如爲化學氣 相沈積法；蝕刻終止層2085之材質包括氮化矽（SiNx)、 氮氧化矽（SiOyNz)、氧化鋁（Al2〇3)或五氧化二鉬（Ta205 )。 接著，請參照第2B圖，在接觸窗開口 210中塡入導體 材料，以形成接觸窗插塞212,與源極/汲極區204電性耦接。 其後，在基底200上形成金屬層214，使其與接觸窗插塞212 電性耦接。接著，於基底200上形成一層與元件表面共形的 介電層216。然後，再於基底200上形成一層旋塗式物質層 經濟部中央橾準局胄Η消费合作杜印裝 ，使其覆蓋介電層216表面，並且塡入金屬層214之間 的溝渠中。其後，進行固化與離子佈植220，以破壞旋塗式 物質層218表面的吸水鍵結。其中，金屬層214之材質包括 金屬鋁、或金屬銅；介電層216之材質與蝕刻終止層208具 有不同之蝕刻率，其材質包括可以吸附游離的離子（Mobile Ion)之介電材料，例如爲富含矽氧化物（SiHcon Rich 〇xide， SR〇) ’形成的方法例如以矽烷（SiH4)爲氣體源，利用化 學氣相沈積的方法進行沈積；旋塗式物質層218則包括具有 低介電常數之介電材質，例如爲流動性氧化物（Flowing 0xide)，例如爲旋塗式玻璃（Spin on Glass，S0G)或氫化 _ 8 ( CNS } ( 210x297^# ) 3253twf/〇〇5 A7 B7 ___ 五、發明説明（7 ) 砂倍半氧化物（Hydrogen Silsesquioxane，HSQ)等；而離 ----------— (請先6^背面之注^^項再填寫本頁) 子佈植220所採用的雜質例如爲砷或磷，其能量約爲 50KeV〜500KeV 左右。 接著’請參照第2C圖，於基底200上形成保護層222 與介電層2M。其中’保護層222之材質與介鼋層224具有 不同之硏磨速率’其材質包括氮化矽（SiNx)、氮氧化矽 (SiOyNz)、氧化鋁（Al2〇3)或五氧化二鉅（Ta205 );介 電層224之材質包括氧化矽、磷矽玻璃（PSG)或硼磷矽玻 璃（BPSG) ’形成的方法例如以四乙氧基矽烷（TEOS)爲 反應氣體’利用化學氣相沈積的方式，以形成氧化矽材質之 介電層224。 接著’請參照第2D圖，去除部份的介電層224，以使 元件全面性地平坦化，例如透過化學機械硏磨技術，以保護 層222爲硏磨終止層，硏磨去除元件表面的介電層224，以 使元件的表面Μ加地平坦化。由於，保護層222可以作爲硏 磨的終止層，因此可以保護保護層222下方的旋塗式物質層 218 ’避免因爲金屬層214圖案密度的不同，造成旋塗式物 質層218的毀損，而使元件無法全面性平坦化之問題。 經濟部中央樣率局貝工消费合作杜印裝 其後，仍請參照第2D圖，以蝕刻終止層2〇8爲蝕刻終 點，將介電層224a、保護層222、旋塗式物質層218與介電 層216圖案化，以形成介層窗開口 226,裸露出金屬層214。 然後，再執行表面處理步驟22S，以破壞介層窗開口 226所 裸露之旋塗式物質層218表面的吸水鍵結，防止後續將導體 材質塡入於介層窗開口 226時，由於旋塗式物質層218的出 9 本紙張尺度逋用中國國家榡準（CNS ) A4規Hl〇X297公釐1 " " 3253twf/005 A7 B7 __ 五、發明説明（又） 氣現象所造成之介層窗毒化問題。其中，處理步驟228可以 以離子佈植或以電漿處理的方式執行。離子佈植所採用的雜 質包括砷或磷，其能量約爲50KeV〜500KeV左右；而電漿 處理的氣體源則例如爲氧氣或氫氣。由於，蝕刻終止層208， 可以在形成介層窗開口 226的製程中作爲蝕刻的終點，防止 過度蝕刻介電層2丨6以及介電層206，而造成後續所形成之 介層窗插塞與基底200中的其他導體層產生短路的現象。因 此，本發明可用以製作未接著介層窗開口，以增加暴露於介 層窗開口 226的面積，使後續所形成之介層窗插塞與金屬層 的接觸面積增加，以提昇元件的導電性。另一方面，由於本 發明在形成介層窗開口 226之後所施行之表面處理步驟 22S，可以破壞介層窗開口 226所裸露之旋塗式物質層218 表面的吸水鍵結，因此，製作未接著介層窗開口，雖然會裸 露出較多的旋塗式物質層218,亦不會在後續的製程中造成 出氣與毒化的問題。 之後，請參照第2E圖，在介層窗開口 226中形成介層 窗插塞234。典型的方法，係在碁底200上先形成一層阻障 層/黏著層23〇，其材質例如爲鈦/氮化鈦，使其覆蓋介層窗 開口 226所暴露的介電層216、旋塗式物質層218、介電層 224與金屬層214之表面。然後，再於基底200上形成金屬 層232，其材質例如爲金屬鋁、金屬鎢、或金屬銅，使其塡 滿介層窗開口 226，與第一層金屬層214電性耦接。其後， 以回蝕刻或化學機械硏磨的方式，去除介電層224上所覆蓋 的阻障層/黏著層230與金屬層232，使留於介層窗開口 226 本紙張尺度逍用中國因家標準（CNS > A4規格（210X297公釐} ---------II (倩先Mtl背面之注意事項再填寫本頁) 訂 鋰濟部中央樣準局工消費合作社印«. 3253twf/005 A7 B7 五、發明説明（？） 中的阻障層/黏著層230與金屬層232形成介層窗插塞234。 由於本發明在形成介層窗開口 226之後所施行之處理步驟 228，可以破壞介層窗開口 226所裸露之旋塗式物質層218 表面的吸水鍵結，因此在形成介層窗插塞234的過程中，並 不會造成介層窗出氣的現象，而衍生毒化的問題。 由上述本發明較佳實施例可知，本發明具有下列特徵： 1. 可以使化學機械硏磨製程的均勻度控制更容易。 2. 在旋塗式物質層上覆蓋一層保護層，可以使化學機械 硏磨的製程終止於保護層，確保旋塗式物質層不會因爲金屬 層圖案密度的不同，而在硏磨的過程中造成其毀損，而使元 件無法全面性平坦化之問題。 3. 在形成介層窗開口之後，經由離子佈植或電漿處理裸 露於介層窗開口的旋塗式物質層，可以去除旋塗式物質層的 吸水鍵，因此可以防止在後續製程中，由於介層窗出氣現象 所衍生的毒化問題。 4·在內層介電層與金屬層間介電層之間所增加的蝕刻終 止層，可以避免在形成介層窗開口的過程中，造成過度蝕刻 昀現象，因此，本發明可以適用於採用未接著接觸窗的高度 積集化元件中。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圔內，當可作各種之更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者爲準。 本紙張AA適用中圏國家樣準（CNS )八4邪_ ( 21()χ 297公兼） --------Q—- {請先《讀背面之注$項再填寫本頁) -訂 -OI. 經濟部中央橾準局貝工消费合作社印裝3253twf / 0O5 A7 B7 V. Description of the Invention (I) The present invention relates to a method for manufacturing an integrated circuit, and more particularly to a method for manufacturing interconnects. With the increase of the integration degree of integrated circuit components, metal oxide semiconductor (MOS) transistors have gradually shrunk, so that the surface of the wafer cannot provide sufficient area for the required interconnections. Multilevel interconnects with multi-layer metal layer designs have become the method used in many integrated circuit manufacturing processes to solve the problem of insufficient chip area. ‘The production of a typical multiple interconnect is to create two or more metal layers on the substrate after conducting the body of the MOS transistor to conduct electrons. The metal layers are insulated by an inter-metal dielectric layer (Inter-Metal Dielectic, IMD), or by a plug formed in the inter-metal dielectric layer to connect the two metal layers. Form a complete circuit. 1A to 1D are cross-sectional views of a conventional manufacturing process of a metal interconnect. Referring to FIG. 1A, an inner dielectric layer 106 is formed on the substrate 100 on which the field effect transistor 102 has been formed, and then patterned to form a contact window opening 110 to expose the field. The source / drain region 104 of the effect transistor 102. Next, referring to FIG. 1B, a conductive material is inserted into the contact window opening 110 to form a contact window plug 112, which is electrically coupled to the source / drain region 104. Thereafter, a metal layer 114 is formed on the substrate 100 so as to be electrically coupled with the contact window plug 112. Next, a dielectric layer conforming to the surface of the element is formed on the substrate 100]. Then, a spin-on material layer I is formed on the substrate 100 so as to cover the surface of the dielectric layer 116 and penetrate into the trench between the metal layers 1H. CNS) A4 specification (2 丨 0 father 297 public ^^ 7 (please read the note on the back before filling in this card) Order the fty domain · Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 3253twf / 〇〇5 3253twf / 〇 〇 Printed by A7 B7, Shellfish Consumer Cooperative, Central Standards Bureau, Ministry of Economic Affairs 5. In the description of the invention (>), a dielectric layer 124 is then formed on the substrate 100. Among them, the material of the dielectric layer 116 includes rich Silicon-containing oxides (8 out of < 〇11 to spit (^, 511)), the formation method is, for example, a chemical vapor deposition method; the spin-on material layer 118 includes a flowing oxide (Flowing Oxide), For example, Spin on Glass' SOG or Hydrogen SilSeSquixane'HSQ, etc .; the material of the dielectric layer 124 includes silicon oxide, and the formation method is, for example, chemical vapor deposition Next, please refer to Figure 1C, and use the chemical mechanical honing method to honing away The dielectric layer 124 on the surface of the element is used to flatten the surface of the element comprehensively, and a sandwich structure metal interlayer dielectric layer formed by the dielectric layer 116, the spin-on material layer 118, and the dielectric layer 124a is completed. Then, , Patterning the dielectric layer 116, the spin-on material layer 118, and the dielectric layer 124a to form a via opening 126 and exposing the first metal layer 114. Then, referring to FIG. 1D, A barrier layer / adhesive layer 13 is formed on the substrate 100 so as to cover the surfaces of the dielectric layer 116, the spin-on material layer Π8, the dielectric layer 124a, and the metal layer 114 exposed by the dielectric window opening 126. Then, 'A metal layer 132 is formed on the substrate 100 so that it fills the dielectric window opening 126' and is electrically coupled to the first metal layer ι14. Thereafter, the dielectric is removed by means of etch-back or chemical mechanical honing. The barrier layer / adhesive layer U0 and the metal layer 132 covered on the layer 124a make the barrier layer / adhesive layer 130 and the metal layer 132 remaining in the via window opening 126 to form a via window plug 134. In the method, due to the circular pattern density and pattern of the metal layer 114 on the wafer surface, The distance between them is not the same. Therefore, when the dielectric layer 124 at different positions is honed by a chemical mechanical honing method, the honing speed will be different. 4 paper sizes, using China National Standard (CNS) A4 specifications (210 > < 297 mm) (Please read the note on the back before filling this page) Order _-· <-3253twf / 00 $ A7 B7 V. The description of the invention (today) affects and makes the burnish In the process, the control of its process is not easy to grasp, and the dielectric layer 124 is often excessively honed to cause the surface of the element to have a depression phenomenon, so that the purpose of flattening cannot be achieved. In addition, after the formation of the interstitial window opening 126 in the above-mentioned method, the exposed spin-on material layer Π8 of the interstitial window opening 126 will generate a hydrophilic bond Si-OH and absorb moisture. The spin-coated material layer Π8 after absorbing water vapor is very likely to cause the formation of the formed interlayer window plug in the subsequent process of forming the barrier layer / adhesive layer BO or the metal layer 132 in the interlayer window opening 126. The phenomenon of outgassing leads to the problem of poisoning of the interlayer window (Poison). On the other hand, with the integration of integrated circuits, in order to effectively increase the density of components, the production of vias has been replaced by unlanded-vias (Landed-Via). Via). However, the formation of the non-adhered interstitial window openings not only increases the exposed area of the spin-on material layer Π8, but also worsens the problems caused by the absorption of water vapor. It may also be in the process of forming the non-adhered interstitial window openings 126. Because of the improper control of the etching, the dielectric layer 116 and the inner dielectric layer 106 under the dielectric layer 116 are over-etched, causing a short circuit between the subsequently formed dielectric window plug 134 and other conductor layers in the substrate 100. phenomenon. Therefore, the object of the present invention is to provide a method for manufacturing interconnects, which can easily control the planarization process of the dielectric layer, and avoid the difference in the pattern density of the metal layer on the surface of the wafer and the distance between the patterns from each other, which will cause the surface of the device to be different. Depression occurs during the planarization process. Another object of the present invention is to provide a method for manufacturing an internal connection, which can be applied to 5 paper sizes that are applicable to the Chinese National Standard (CNS) A4 (210X297 male β --------- CC ---- --- ir ------. €--(Please read the note $ on the back before filling out this page) Printed by the Central Ministry of Economic Affairs of the Ministry of Economic Affairs Industrial and consumer cooperative printing 3253twf / 005 A7 _B7 V. Description of the invention (f) To prevent the spin-coated material layer exposed from the opening of the interlayer window from generating hydrophilic bonds to absorb moisture after defining the opening of the interlayer window, to avoid moisture In the subsequent process, the interstitial window is outgassed and the interstitial window is poisoned. Another object of the present invention is to provide a manufacturing method of interconnects, which can prevent the process that defines the opening of the interstitial window, Due to the over-etching of the dielectric layer, a short-circuit phenomenon occurs between the subsequently formed dielectric window plug and other conductor layers in the substrate. According to the above object of the present invention, a method for manufacturing a metal interconnect is proposed. After the inner dielectric layer is formed on the substrate, the contact window is not directly performed. In the production of the plug, a contact stop layer is first formed on the inner dielectric layer, and then a contact plug is formed in the inner dielectric layer and the etch stop layer, and a metal layer is formed and a sandwich structure is formed. The production of a metal interlayer dielectric layer. The etching stop layer added to the inner dielectric layer and the metal interlayer dielectric layer can avoid the phenomenon of excessive etching during the subsequent formation of the dielectric window opening. In the metal In the interlayer dielectric layer, the protective layer added between the spin-on material layer and the oxide layer can be used as a honing stop layer for the honing oxide layer, which effectively controls the process of chemical mechanical planarization of the interlayer dielectric layer. After the metal interlayer dielectric layer is patterned to form an interlayer window opening and then ion implantation or plasma treatment is performed, the water-absorbing bond on the surface of the spin-coated material layer exposed by the interlayer window opening can be destroyed, avoiding subsequent In the manufacturing process, the venting of the interlayer window is caused, and the interlayer window is poisoned. In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, a better implementation is given below. And with the accompanying drawings, the detailed description is as follows: 6 This paper size is free from the Chinese National Standard (CNS) A4 specification (210x297 mm) --------- c _.— · (please first Mr Read the note on the back ^^ and fill in this page) Order _ 3253twf / 005 A7 B7 V. Description of the invention (7) Brief description of the drawings: Figures 1A to 1D show a conventional manufacturing process of an interconnect. Sectional view: and 2A to 2E circles are cross-sectional views showing the manufacturing process of a printed line of the Shellfish Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs in accordance with an embodiment of the present invention. : Substrates 102, 202: field effect transistors 104, 204: source / drain regions 106, 206: inner dielectric layers 110, 210: contact window openings 112, 212: contact window plugs 114, 214: metal layers 116, 124, 216, 224: dielectric layers 118, 218: spin-on material layers 126, 226: interlayer window openings 130, 230: adhesion / barrier layers 132, 232: metal layers 134, 234: contact window inserts Plug 208: Etch stop layer 220: Ion implant 222: Protective layer 228: Surface treatment step example N.1.J /. --------- rr ------ IT ------- < (谙 Please read the note on the backside before filling in this page) This paper standard uses the Chinese national standard ( CNS) A4 specification (2! 0X297 mm) 3253twf / 〇〇5 Α7 Β7 V. Description of the invention (() {Please note the $ on the back of Sijf before filling out this page) Figures 2A to 2E are shown in accordance with this Invented a cross-sectional view of the manufacturing process of the interconnect. First, referring to FIG. 2A, an inner dielectric layer 206 is formed on the substrate 200 on which the field effect transistor 202 has been formed, and then an etch stop layer 208 is formed on the inner dielectric layer 206. . Thereafter, the etch stop layer 208 and the inner dielectric layer 206 are patterned to form a contact window opening 21 and the source / drain region 204 of the field effect transistor 202 is exposed. Wherein, the material of the inner dielectric layer 206 includes silicon oxide, and a method for forming the inner dielectric layer 206 includes, for example, chemical vapor deposition. The material of the etching stop layer 2085 includes silicon nitride (SiNx), silicon oxynitride (SiOyNz), and aluminum oxide (Al2). 〇3) or molybdenum pentoxide (Ta205). Next, referring to FIG. 2B, a conductive material is inserted into the contact window opening 210 to form a contact window plug 212, which is electrically coupled to the source / drain region 204. Thereafter, a metal layer 214 is formed on the substrate 200 so as to be electrically coupled with the contact window plug 212. Next, a dielectric layer 216 is formed on the substrate 200 that is conformal to the surface of the device. Then, a spin-coated material layer is formed on the substrate 200. The Ministry of Economic Affairs, the Central Bureau of Standards, and the Consumer Cooperative Printing System cover it to cover the surface of the dielectric layer 216 and penetrate into the trench between the metal layers 214. Thereafter, curing and ion implantation 220 are performed to break the water-absorbing bonds on the surface of the spin-on material layer 218. The material of the metal layer 214 includes aluminum or metal copper; the material of the dielectric layer 216 and the etch stop layer 208 have different etch rates, and the material includes a dielectric material capable of adsorbing free ions (Mobile Ion), such as In order to form a method rich in silicon oxide (SiHcon Rich Oxide, SR〇), for example, silane (SiH4) is used as a gas source, and a chemical vapor deposition method is used for deposition; the spin-on material layer 218 includes The dielectric material of the dielectric constant is, for example, flowing oxide (Flowing 0xide), for example, spin on glass (S0G) or hydrogenation_ 8 (CNS) (210x297 ^ #) 3253twf / 〇〇5 A7 B7 ___ 5. Description of the invention (7) Hydrogen Silsesquioxane (HSQ), etc .; and ----------- (please fill in this page with the note ^^ on the back of 6 ^) The impurity used in the sub-planting 220 is, for example, arsenic or phosphorus, and its energy is about 50KeV ~ 500KeV. Next, please refer to FIG. 2C, and form a protective layer 222 and a dielectric layer 2M on the substrate 200. Among them, the protective layer 222 The material and the interlayer 224 have different honing rates. Including silicon nitride (SiNx), silicon oxynitride (SiOyNz), aluminum oxide (Al203) or pentoxide (Ta205); the material of the dielectric layer 224 includes silicon oxide, phosphosilicate glass (PSG) or borophosphorus Silicon glass (BPSG) is formed using a method such as tetraethoxysilane (TEOS) as a reaction gas to form a silicon oxide dielectric layer 224 by chemical vapor deposition. Next, please refer to FIG. 2D, A portion of the dielectric layer 224 is removed to planarize the device comprehensively. For example, by using a chemical mechanical honing technique, the protective layer 222 is used as a honing stop layer, and the dielectric layer 224 on the surface of the device is honed to remove the device. The surface M is flattened. Since the protective layer 222 can be used as a honing termination layer, the spin-coating material layer 218 under the protective layer 222 can be protected ′ to avoid the spin-coating material caused by the difference in the pattern density of the metal layer 214. The layer 218 is damaged, which makes the component unable to be completely flattened. After the installation of the print job consumer cooperation department of the Central Samples Bureau of the Ministry of Economic Affairs, please refer to Figure 2D and use the etch stop layer 208 as the end point of the etch. Dielectric layer 224a, The protective layer 222, the spin-on material layer 218, and the dielectric layer 216 are patterned to form the interlayer window opening 226, and the metal layer 214 is exposed. Then, a surface treatment step 22S is performed to destroy the exposed portion of the interlayer window opening 226. The spin-coated substance layer 218 has a water-absorbing bond on the surface to prevent subsequent insertion of the conductor material into the opening 226 of the interlayer window. Since the spin-coated substance layer 218 has 9 paper sizes, the Chinese National Standard (CNS) is used. A4 Regulation H10X297 mm 1 " " 3253twf / 005 A7 B7 __ 5. Description of the invention (again) the problem of poisoning of interlayer windows caused by gas phenomenon. The processing step 228 may be performed by ion implantation or plasma treatment. The impurities used for ion implantation include arsenic or phosphorus, whose energy is about 50KeV ~ 500KeV; and the gas source for plasma treatment is, for example, oxygen or hydrogen. Because the etch stop layer 208 can be used as the end point of the etching in the process of forming the dielectric window opening 226, preventing the dielectric layer 2 and the dielectric layer 206 and the dielectric layer 206 from being over-etched, resulting in the subsequent formation of the dielectric window plug and the The other conductor layers in the substrate 200 are short-circuited. Therefore, the present invention can be used to fabricate a non-adhered interstitial window opening to increase the area exposed to the interstitial window opening 226 and increase the contact area between the subsequently formed interstitial window plug and the metal layer to improve the conductivity of the device. . On the other hand, since the surface treatment step 22S performed after the interlayer window opening 226 is formed in the present invention, the water-absorbing bond on the surface of the spin-coated material layer 218 exposed by the interlayer window opening 226 can be destroyed. Although the opening of the interlayer window will expose a large number of spin-on material layers 218, it will not cause problems of outgassing and poisoning in subsequent processes. After that, referring to FIG. 2E, a via plug 234 is formed in the via window opening 226. A typical method is to first form a barrier layer / adhesive layer 23 on the substrate 200. The material is, for example, titanium / titanium nitride, so as to cover the dielectric layer 216 exposed by the dielectric window opening 226, and spin coating. Surfaces of the material layer 218, the dielectric layer 224, and the metal layer 214. Then, a metal layer 232 is formed on the substrate 200, and the material is, for example, metal aluminum, metal tungsten, or metal copper, so that it fills the interlayer window opening 226, and is electrically coupled to the first metal layer 214. Thereafter, the barrier layer / adhesive layer 230 and the metal layer 232 covered by the dielectric layer 224 are removed by etch-back or chemical mechanical honing, so that the openings in the interlayer window are left 226 Home Standards (CNS > A4 Specifications (210X297mm) --------- II (Notes on the back of Qianxian Mtl before filling out this page) Order the Printing of the Central Procurement Bureau of the Ministry of Lithuania and Consumer Cooperatives «. 3253twf / 005 A7 B7 V. The barrier layer / adhesive layer 230 and the metal layer 232 in the description of the invention (?) Form an interlayer window plug 234. Since the present invention performs the processing step 228 after the interlayer window opening 226 is formed Can destroy the water-absorbing bond on the surface of the spin-coated material layer 218 exposed in the opening 226 of the interlayer window, so the process of forming the interlayer window plug 234 will not cause the phenomenon of outgassing of the interlayer window, which will lead to poisoning. According to the above-mentioned preferred embodiments of the present invention, it can be known that the present invention has the following characteristics: 1. It can make the uniformity control of the chemical mechanical honing process easier. 2. Covering the spin-coating material layer with a protective layer can Stop the chemical mechanical honing process on the protective layer Ensure that the spin-on material layer will not be damaged in the honing process due to the difference in the pattern density of the metal layer, so that the component cannot be fully flattened. 3. After forming the opening of the interlayer window, pass the ion The spin-coated material layer exposed at the opening of the dielectric window can be removed by implantation or plasma treatment, which can remove the water-absorbing bond of the spin-coated material layer, so it can prevent the poisoning problem caused by the gas out phenomenon of the dielectric window in the subsequent process. 4. The etch stop layer added between the inner dielectric layer and the metal interlayer dielectric layer can avoid the phenomenon of excessive etching during the process of forming the dielectric window opening. Therefore, the present invention can be applied to the The contact element is then highly integrated into the element. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention. Various modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. The paper AA is applicable to the national standard of China ( CNS) Eight 4 evils _ (21 () χ 297 public and cumulative) -------- Q—- {Please read the "$" on the back before filling this page) -Order-OI. Central Ministry of Economic Affairs 橾Printed by the Bureau of Shellfish Consumer Cooperatives