569388 經濟部智悲財產局8工消费合作社印製 A7 B7 六、發明説明（1 ) 發明領域： 本發明關於一種形成雙層嵌入結構的方法。更明確地 說，關係於一種消除於形成雙層嵌入結構時之銅侵蝕的方法 〇 發明背景： 當積體電路趨向高積集度發展，晶片表面已經無法提供 足夠面積製作所需內連線時，爲了配合電晶體縮小後所增加 之內連線需求，兩層以上之金屬層設計已成爲許多積體電路 採用的方式，特別是一些較複雜的產品，如微處理器，甚至需 要四層或更多層金屬層，才得以完成各元件間之連接。 爲了避免於傳統銘線所造成之電遷移，銅已經被採用於 深次微米之元件中。由於低電阻率、低電遷移率及容易沉 積，銅已經大量用於製造多層內連線。一般而言，銅內連線係 以一雙層嵌入製程加以形成。該雙層嵌入製程包含有蝕刻 一介層洞開口，用以封閉在一介電層中之金屬內連線，然後將 該介層開口 iji：入金屬。此製程能在相當尚良率下，生產出高 品質的銅內連線。 第1 A至1 C圖例示出用以製造一傳統雙層嵌入結構的 步驟的剖面示意圖。如於第1 A圖所示，提供有一具有一導 體層102在其中之基材100。一介電層104係形成在基材 100及導體層102上。接著，進行光微影及蝕刻製程，以在介 電層104中形成一介層洞開口 105a及一溝渠105b，以曝露出 該導體層102的一部份。一保角阻障層106然後形成在該 本纸張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） I II I - - 1 - - I - 二-! I - I ^J- , ^ - 、-- (讀先閱讀背面之注意事項再填寫本頁)569388 Printed by the Industrial and Commercial Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 VI. Description of the Invention (1) Field of the Invention: The present invention relates to a method for forming a double-layer embedded structure. More specifically, it is related to a method for eliminating copper corrosion when forming a double-layer embedded structure. BACKGROUND OF THE INVENTION: When integrated circuits are developing towards a high degree of integration, the surface of the chip can no longer provide sufficient area for the required interconnects In order to meet the increased interconnect requirements after the transistor has shrunk, the design of two or more metal layers has become the method adopted by many integrated circuits, especially some more complex products, such as microprocessors, which even require four layers or More layers of metal can complete the connection between the components. In order to avoid electromigration caused by traditional name lines, copper has been used in sub-micron devices. Due to its low resistivity, low electromobility, and easy deposition, copper has been used in large quantities for the fabrication of multilayer interconnects. Generally, copper interconnects are formed using a two-layer embedded process. The double-layer embedding process includes etching a hole in a dielectric layer to close a metal interconnect in a dielectric layer, and then opening the dielectric layer into a metal. This process can produce high-quality copper interconnects at fairly high yields. Figures 1A to 1C illustrate schematic cross-sectional views of the steps used to fabricate a conventional double-layer embedded structure. As shown in FIG. 1A, a substrate 100 having a conductive layer 102 therein is provided. A dielectric layer 104 is formed on the substrate 100 and the conductor layer 102. Next, a photolithography and etching process is performed to form a via hole 105a and a trench 105b in the dielectric layer 104 to expose a part of the conductor layer 102. A conformal barrier layer 106 is then formed on this paper scale to apply Chinese National Standard (CNS) A4 specifications (210X 297 mm) I II I--1--I-II-! I-I ^ J-, ^-,-(Read the notes on the back before filling in this page)
-5- 569388 經濟部智Μ財產局S工消費合作社印製 Α7 Β7 六、發明説明（2 ) 開口 105a及溝渠105b與介電層104上，然後，一塡充該介層 洞開口 105a及溝渠105b之銅層108係形成在該介電層104 上。然後，執行一平坦化步驟，以去除在該介電層104上之阻 障層106及銅層108。該平坦化步驟係例如以一化學機械硏 磨加以進行。 由於銅原子可能很快速地擴散入介電層之氧化矽中並 可能容易地與矽反應，而產生銅·矽合金。因爲銅-矽合金可 能造成裝置故障或於相鄰金屬內連線間的短路，所以，有需要 該阻障層1 06來防止銅原子由銅層1 〇8擴散入介電層1 04中 〇 如於第1 B圖所示，一氮化矽層1 1 〇及一金屬層間介電 (IMD)層112係依序形成於該介電層104及銅層108上。氮 化矽也同時能防止銅原子擴散入該IMD層1 1 2中。 然後，一有圖案光阻層（未示出）係形成於該IMD層112 上。使用氮化矽層1 1 0作爲一蝕刻停止層，該IMD層1 1 2被 蝕亥!J，以形成一介層洞開口 114,其曝露出該氮化矽層110的 一部份。由於氮化砂層1 1 0之出現於介電層1 0 4及IM D層 112之間，所以可以防止IMD層112過度蝕刻入介電層104 中。然後，執行一第二蝕刻步驟，以去除在介層洞開口 1 14底 部的氮化矽層110,使得銅層108的一部份被曝露出，如於第 1C圖所示。 由於在介層洞開口 114形成後，氧電漿被用以去除殘留 光阻材料，因爲氧可能與銅層1 08中之銅反應而產生氧化銅， 形成在該銅層1 08的曝露部份上。當一阻障層隨後形成該 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） 訂 (請先閱讀背面之注意事項再填寫本頁)-5- 569388 Printed by Intellectual Property Bureau of the Ministry of Economic Affairs, S Industrial Consumer Cooperative, A7, B7 VI. Description of the invention (2) The opening 105a and the trench 105b and the dielectric layer 104 are then filled, and then the opening 105a and the trench of the dielectric layer are filled. A copper layer 108 of 105b is formed on the dielectric layer 104. Then, a planarization step is performed to remove the barrier layer 106 and the copper layer 108 on the dielectric layer 104. The planarization step is performed, for example, by a chemical mechanical honing. Since copper atoms may diffuse into the silicon oxide of the dielectric layer very quickly and may easily react with silicon, a copper-silicon alloy is generated. Because copper-silicon alloy may cause device failure or short circuit between adjacent metal interconnects, the barrier layer 106 is needed to prevent copper atoms from diffusing from the copper layer 108 into the dielectric layer 104. As shown in FIG. 1B, a silicon nitride layer 110 and a metal interlayer dielectric (IMD) layer 112 are sequentially formed on the dielectric layer 104 and the copper layer 108. At the same time, silicon nitride can prevent copper atoms from diffusing into the IMD layer 1 12. Then, a patterned photoresist layer (not shown) is formed on the IMD layer 112. The silicon nitride layer 110 is used as an etch stop layer, and the IMD layer 12 is etched to form a via hole 114, which exposes a part of the silicon nitride layer 110. Since the nitrided sand layer 110 appears between the dielectric layer 104 and the IMD layer 112, the IMD layer 112 can be prevented from being excessively etched into the dielectric layer 104. Then, a second etching step is performed to remove the silicon nitride layer 110 at the bottom of the via hole 114, so that a part of the copper layer 108 is exposed, as shown in FIG. 1C. After the formation of the via 114, the oxygen plasma is used to remove the residual photoresist material, because oxygen may react with the copper in the copper layer 108 to generate copper oxide, which is formed in the exposed portion of the copper layer 108 on. When a barrier layer is subsequently formed, this paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm). (Please read the precautions on the back before filling this page)
-6 - 569388 ___B7_ 六、發明説明（3 ) 銅層上時，該金屬內連線的導電率可能會下降並且也會增加 介層洞電阻。 (諳先閱讀背面之注意事項再填寫本頁} 另外，於介層洞開口 114形成後，也進行一淸洗步驟使得 沉積於開口 114側壁上的聚合物被去除。然而，多數有機淸 洗劑均包含水，其可能造成銅侵蝕及氧化。另外，在介層洞開 口壁面上之聚合物係藉由將晶圓浸在含淸洗溶液之化學槽 中。由於淸洗溶液之銅離子數量很難控制。所以，在該淸洗 溶液中之銅離子可能再沉積回到晶圓上，造成不想要的污染 〇 發明目的及槪沭： 經濟部智祛財產局5貝工消費合作社印災 因此，本發明提供一種消除雙層嵌入結構之銅侵蝕的方 法’包含步驟：在一基材中形成一導體層；在該基材上形成 一第一介電層；形成一雙層嵌入開口於該第一介電層中，以曝 露出該導體層，其中表面上，該雙層嵌入開口包含—第一介層 洞開口及一在該第一介層洞開口上之溝渠；沉積一第一阻障 層於該溝渠及該介層洞開口的側壁上；在該溝渠及介層洞開 口中，形成一銅層；沉積一第二阻障層覆蓋於該銅層及該第一 介電層；定義該第二阻障層圖案，以對準該銅層；沉積一蝕刻 停止層於該第二阻障層及第一介電層上；沉積一第二介電層 在該蝕刻停止層上；去除該第二介電層及蝕刻停止層的一部 份，以形成一第二介層洞開口，其曝露出該第二阻障層的一部 依據本發明之實施例，由於當介層洞開口以反應離子蝕 本紙張尺度適用+SB1家辟（CMS ) A4規格（210Χ297ϋ " 569388 A7 B7 六、發明説明（4 ) (請先閲讀背面之注意事項再填寫本頁) 刻（RIE)製程形成時，銅層係爲該蝕刻停止層所保護。所以電 漿粒子被阻隔開，因而避免基材及製程室的污染。再者，藉由 在曝露之銅層上形成該蝕刻停止層，藉由與周遭氣氛中之氧 反應而形成氧化銅的情形也可以加以避免。同時，由於蝕亥!J 停止層的出現，防止了當晶圓以浸於淸洗溶液中淸洗時之銅 的氧化及侵蝕。 圖式簡單說明= 第1A-1C圖爲用以生產傳統雙層嵌入結構的製程步驟 的剖面圖； 第2A-2E圖爲用以形成依據本發明第一較佳實施例的 雙層嵌入結構的步驟的剖面圖；及 第3A-3E圖爲用以形成依據本發明第二較佳實施例的 雙層嵌入結構的步驟的剖面圖。 圖號對照說明= 經濟部智慧財產局員工消費合作社印製 100 基材 102 導體層 104 介電層 105a 介層洞開 105b 溝渠 106 阻障層 108 銅層 110 氮化砂層 本紙張尺度適用中國國家標準（CNS ) A4規格（2】〇X 297公釐） -8- 569388 A7 B7 六、發明説明（5 ) 經濟部智延財產局員工消費合作社印製 112 金屬層間介電 114 介層洞開口 200 基材 202 導體層 204 介電層 205a 介層洞開口 205b 溝渠 206 阻障層 208 銅層 210 阻障層 210a 阻障材料層 212 光阻層 214 蝕刻停止層 216 金屬層間介電 218 介層洞開口 300 基材 302 導體層 304 介電層 305a 介層洞開口 305b 溝渠 306 阻障層 308 銅層 310 阻障層 310a 阻障材料層 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -9- 569388 A7 _____B7 六、發明説明（6) 311 鋁/銅金屬層 311a 金屬層 312 光阻層 314 蝕刻停止層 316 金屬層間介電層 318 介層洞開口 曼ja詳細說明： 現在將詳細說明本發明的各較佳實施例。其係被例示 於附圖中，其中，相同參考號係用以表示相同或類似之元件。 經濟部智慧財產局S工消費合作社印製 I m - ϋ^— if n^i —ϋ I I - { ϋϋ m i^n ^^^1 ^1J * 0¾ . (請先閱讀背面之注意事項再填寫本頁) 第2A至2E圖爲用以形成依據本發明第一較佳實施例 的雙層嵌入結構的步驟剖面圖。如第2A圖所示，提供有一 導體層202形成於其中之基材200。一例如氧化物層之介電 層204係形成於該導體層202上。該介電層204係被平坦化 。然後，一具有介層洞開口 205a及溝渠205b之雙層嵌入開 口被形成在該介電層204中，以曝露出導體層202。該雙層 嵌入開口之形成方法係例如以下述方法加以完成。形成一 第一圖案光阻層（未示出）以曝露出在導體層202上之想要介 層洞區域。該介電層204係使用該第〜圖案光阻層作爲遮 罩而加以蝕亥U，以形成曝露出該導體層202 —部份的介層洞 開口 20 5a。然後，去除第一圖案光阻層。在該介電層204上 形成一第二圖案光阻層（未示出）。使用該第二圖案光阻層作 爲遮罩，該介電層204被蝕刻，以形成溝渠205b。然後，去除 該第二圖案光阻層。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -10- 569388 A7 B7 六、發明説明（7 ) 然後，第一阻障層206係形成在該介電層204及該開口 205a及溝渠205b的內表面上。一銅層208然後形成在該基 材上，以塡充該溝渠205b及介層洞開口 205a。該銅層208係 被平坦化，並使用該介電層204作爲硏磨停止層，以形成一雙 層嵌入結構。 於本發明之實施例中，該銅層208可以例如藉由化學氣 相沉積或無銅電鍍加以形成。該第一阻障層206係例如藉 由化學氣相沉積一氮化鉅（TaN)層加以形成。因爲氮化鉬層 具有高抗擴散能力，所以可以防止銅原子擴散入該介電層 204 ° 如於第2B圖所示，一第二阻障層210係形成在該介電層 204及銅層208上。第二阻障層210可以由防止銅層208氧 化及銅原子擴散入後續形成之介電層的材料作成。於此實 施例中，該第二阻障層210可以例如爲一氮化鈦、鈦、鈦鎢 (TiW)合金及氮化鉬所形成。該阻障層係用以防止銅原子擴 散入附近之介電層中。然後，一有圖案之光阻層212係形成 在該第二阻障層210上。該光阻層212係直接形成在該雙 層嵌入結構上。 如於第2C圖所示，使用光阻層212作爲蝕刻遮罩，以反 應性離子蝕刻製程，將該阻障層210的一部份去除，以形成一 阻障材料層210a，以覆蓋住該雙層嵌入結構的銅層208。 然後，如於第2D圖所示，一保角蝕刻停止層214係形成 在該阻障材料層210a及介電層204上。一金屬層間介電 (IMD)層216係形成在該蝕刻停止層214上。蝕刻停止層 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -------,—— 餐-- (請先閲讀背面之注意事項再填寫本頁)-6-569388 ___B7_ VI. Description of the Invention (3) When the copper layer is on, the conductivity of the metal interconnects may decrease and increase the via resistance of the interlayer. (Please read the precautions on the back before filling this page} In addition, after the via opening 114 is formed, a cleaning step is also performed to remove the polymer deposited on the sidewall of the opening 114. However, most organic cleaning agents Both contain water, which may cause copper erosion and oxidation. In addition, the polymer on the opening wall surface of the via is immersed the wafer in a chemical bath containing a cleaning solution. Because the amount of copper ions in the cleaning solution is very large It is difficult to control. Therefore, the copper ions in the cleaning solution may be deposited back on the wafer, causing unwanted pollution. Purpose of the invention and: 印 The Intellectual Property Office of the Ministry of Economic Affairs and the 5 Bayan Consumer Cooperatives printed the disaster. The present invention provides a method for eliminating copper corrosion of a double-layer embedded structure, comprising the steps of: forming a conductive layer in a substrate; forming a first dielectric layer on the substrate; forming a double-layer embedded opening in the first A dielectric layer is used to expose the conductor layer. On the surface, the double-layer embedded opening includes a first dielectric hole opening and a trench on the first dielectric hole opening. A first barrier is deposited. Floor A trench is formed on the sidewall of the trench and the opening of the via; a copper layer is formed in the trench and the opening of the via; a second barrier layer is deposited to cover the copper layer and the first dielectric layer; defining the first Two barrier layer patterns to align the copper layer; deposit an etch stop layer on the second barrier layer and the first dielectric layer; deposit a second dielectric layer on the etch stop layer; remove the first A portion of the two dielectric layers and the etch stop layer to form a second dielectric hole opening, which exposes a portion of the second barrier layer according to an embodiment of the present invention. Ion etched paper size applicable + SB1 Jiapi (CMS) A4 specification (210 × 297ϋ " 569388 A7 B7 VI. Description of the invention (4) (Please read the precautions on the back before filling this page) When the RIE process is formed, copper The layer is protected by the etch stop layer. Therefore, plasma particles are blocked, thereby avoiding contamination of the substrate and the process chamber. Furthermore, by forming the etch stop layer on the exposed copper layer, and by surrounding the atmosphere The reaction of oxygen in the formation of copper oxide can also be applied. At the same time, due to the appearance of the etching stop layer J, copper oxidation and corrosion are prevented when the wafer is immersed in a rinsing solution. Brief description of the drawings = Figures 1A-1C are used for production Sectional views of manufacturing steps of a conventional double-layer embedded structure; Figures 2A-2E are sectional views of steps for forming a double-layered embedded structure according to the first preferred embodiment of the present invention; and Figures 3A-3E are used for A cross-sectional view of a step of forming a double-layer embedded structure according to a second preferred embodiment of the present invention. Comparative illustration of drawing numbers = printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 100 substrate 102 conductor layer 104 dielectric layer 105a dielectric hole opening 105b Ditch 106 Barrier layer 108 Copper layer 110 Nitrided sand layer The paper size is applicable to Chinese National Standard (CNS) A4 specification (2) 0X 297 mm -8- 569388 A7 B7 6. Description of the invention (5) Ministry of Economic Affairs Printed by Yanchang Property Bureau, Consumer Cooperative, 112 Interlayer dielectric 114 Interlayer hole opening 200 Substrate 202 Conductor layer 204 Dielectric layer 205a Intermediate hole opening 205b Trench 206 Barrier layer 208 Copper layer 210 Barrier layer 210a Barrier material Layer 212 Photoresist layer 214 Etch stop layer 216 Interlayer dielectric 218 Interlayer hole opening 300 Substrate 302 Conductor layer 304 Dielectric layer 305a Interlayer hole opening 305b Trench 306 Barrier layer 308 Copper layer 310 Barrier layer 310a Barrier Material layer (please read the precautions on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) -9- 569388 A7 _____B7 VI. Description of the invention (6) 311 Aluminum / Copper The metal layer 311a, the metal layer 312, the photoresist layer 314, the etch stop layer 316, the metal interlayer dielectric layer 318, the interlayer hole opening, and the detailed description: Now, the preferred embodiments of the present invention will be described in detail. It is exemplified in the drawings, where the same reference numerals are used to indicate the same or similar elements. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, S Industry Consumer Cooperative, I m-ϋ ^ — if n ^ i —ϋ II-{ϋϋ mi ^ n ^^^ 1 ^ 1J * 0¾. (Please read the notes on the back before filling in this (Pages) 2A to 2E are cross-sectional views of steps for forming a double-layer embedded structure according to the first preferred embodiment of the present invention. As shown in FIG. 2A, a substrate 200 having a conductive layer 202 formed therein is provided. A dielectric layer 204, such as an oxide layer, is formed on the conductor layer 202. The dielectric layer 204 is planarized. Then, a double-layer embedding opening having a via hole 205a and a trench 205b is formed in the dielectric layer 204 to expose the conductive layer 202. The method for forming the double-layered insertion opening is performed, for example, by the following method. A first patterned photoresist layer (not shown) is formed to expose the desired via hole area on the conductor layer 202. The dielectric layer 204 is etched by using the ~ patterned photoresist layer as a mask to form a dielectric hole opening 20 5a exposing a part of the conductive layer 202. Then, the first patterned photoresist layer is removed. A second patterned photoresist layer (not shown) is formed on the dielectric layer 204. Using the second patterned photoresist layer as a mask, the dielectric layer 204 is etched to form a trench 205b. Then, the second patterned photoresist layer is removed. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -10- 569388 A7 B7 VI. Description of the invention (7) Then, the first barrier layer 206 is formed on the dielectric layer 204 and the opening 205a And the inner surface of the trench 205b. A copper layer 208 is then formed on the substrate to fill the trench 205b and the via hole opening 205a. The copper layer 208 is planarized, and the dielectric layer 204 is used as a honing stop layer to form a double-layer embedded structure. In an embodiment of the present invention, the copper layer 208 may be formed by, for example, chemical vapor deposition or copper-free plating. The first barrier layer 206 is formed by, for example, chemical vapor deposition of a giant nitride (TaN) layer. Because the molybdenum nitride layer has high anti-diffusion ability, copper atoms can be prevented from diffusing into the dielectric layer 204. As shown in FIG. 2B, a second barrier layer 210 is formed on the dielectric layer 204 and the copper layer. 208 on. The second barrier layer 210 may be made of a material that prevents oxidation of the copper layer 208 and diffusion of copper atoms into a subsequently formed dielectric layer. In this embodiment, the second barrier layer 210 may be formed of, for example, titanium nitride, titanium, titanium tungsten (TiW) alloy, and molybdenum nitride. The barrier layer is used to prevent copper atoms from diffusing into a nearby dielectric layer. Then, a patterned photoresist layer 212 is formed on the second barrier layer 210. The photoresist layer 212 is directly formed on the double-layer embedded structure. As shown in FIG. 2C, using the photoresist layer 212 as an etching mask, a part of the barrier layer 210 is removed by a reactive ion etching process to form a barrier material layer 210a to cover the Copper layer 208 of double-layer embedded structure. Then, as shown in FIG. 2D, a conformal etch stop layer 214 is formed on the barrier material layer 210a and the dielectric layer 204. A metal interlayer dielectric (IMD) layer 216 is formed on the etch stop layer 214. Etching stop layer This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) -------, ---- Meal-(Please read the precautions on the back before filling this page)
JT 經濟部智慈財產局員工消費合作社印製 -11 - 569388 A7 __ _B7_ 六、發明説明（8 ) 2 1 4及IMD層2 1 6係由具有不同蝕刻率之材料所形成。倉虫 刻停止層214較佳由化學氣相沉積法所作成之氮化矽或氧 氮化矽。而IMD層216較佳爲由低介電常數材料所作成，例 如氧化矽、摻氟氧化矽或磷矽玻璃。因爲氮化矽層214爲 一緊密材料，所以可以更進一步抑制銅原子擴散入該IMD層 。因此，確保了裝置的可靠度。 然後，IMD層216的一部份係被去除，以曝露出蝕刻停止 層214的一部份。該IMD層216係藉由傳統光微影及蝕刻 製程加以去除。由於該鈾刻停止層214的保護，可以防止該 介電層204的過度鈾刻。然後，蝕刻該停止層214的一部份， 以形成一介層洞開口 21 8,該開口會曝露出該阻障材料層 2 10a，如第2E圖所示。該蝕刻停止層214較佳係藉由例如反 應離子蝕刻之乾鈾刻法加以去除。然後，氧電漿被用以去除 殘留之光阻材料。因爲銅層208並未露出，所以銅層208將 不會在電漿蝕刻時被氧化。因此，可以維持住金屬內連線的 導電率及介層洞電阻。同時，也不會有銅離子被濺射出，以污 染晶圓及製程室的問題。另外，也由於銅層208係完全密封， 所以可以防止銅被氧電漿所氧化及銅被淸洗溶液所侵蝕。 第3A至3E圖爲用以形成依據本發明第二較佳實施例 的雙層嵌入結構的步驟剖面圖。如第3A圖所示，提供有一 導體層302形成於其中之基材300。一例如氧化物層之介電 層3 04係形成於該導體層302上。該介電層3 04係被平坦化 。然後，一具有介層洞開口 305a及溝渠305b之雙層嵌入開 口被形成在該介電層304中，以曝露出導體層302。該雙層 本紙張尺度適用中國國家標準（CNS ) μ規格（210X 297公飨） (請先閱讀背面之注意事項再填寫本頁) 裝. •V户 經濟部智慧財產局員工消費合作社印製 -12- 569388 A7 _^___ B7 五、發明説明（9 ) 嵌入開口之形成方法係例如以下述方法加以完成。形成一 弟一^圖案光阻層（未不出）以曝露出在導體層302上之想要介 層洞區域。該介電層304係使用該第一圖案光阻層作爲遮 罩而加以蝕刻。然後，形成曝露出該導體層302 —部份的介 層洞開口 305a。然後，去除第一圖案光阻層。在該介電層 304上形成一第二圖案光阻層（未示出）。使用該第二圖案光 阻層作爲遮罩，該介電層304被蝕亥[J，以形成溝渠305b。然後 ，去除該第二圖案光阻層。 然後，第一阻障層306係形成在該介電層304及該介層 洞開口 305a及溝渠305b的內表面上。一銅層308然後形成 在該基材上，以塡充該溝渠305b及介層洞開口 305a。該銅 層308係被平坦化，並使用該介電層304作爲硏磨停止層，以 形成一雙層嵌入結構。 於本發明之實施例中，該銅層308可以例如藉由化學氣 相沉積或無銅電鍍加以形成。該第一阻障層306係例如藉 由化學氣相沉積一氮化鈦（TiN)層加以形成。 如於第3 B圖所示，一第二阻障層3 1 0係形成在該介電層 304及銅層308上。該第二阻障層310可以由防止銅層308 氧化及銅原子擴散入後續形成之介電層的材料作成。於此 實施例中，該第二阻障層310可以例如爲一氮化鈦、鈦、鈦 鎢（TiW)合金及氮化鉅所形成。該阻障層係用以防止銅原子 擴散入附近之介電層中。然後，沉積一層鋁/銅金屬層311於 該第二阻障層3 1 0上。一有圖案之光阻層3 1 2係形成在該 絕/銅金屬層3 1 1上。該光阻層3 1 2係直接形成在該雙層嵌 本紙張尺度適财關家縣（CNS ) M規格( 2i〇x297公麓） " -13 - 沐衣-- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 569388 經濟部智慈財產局员工消費合作社印製 A7 B7 六、發明説明（1〇 ) 入結構上。除了該銘/銅合金外，也可以沉積C u、A1C u S i合 金或鎢加以進行。 然後，使用光阻層3 1 2作爲蝕刻遮罩，以反應性離子鈾亥[j 製程，將該鋁/銅金屬層311及阻障層310的一部份去除，以形 成一金屬層3 1 1 a及阻障材料層3 1 0a，以覆蓋住該雙層嵌入結 構的銅層308,如於第3C圖所示。 然後，如於第3D圖所示，一保角蝕刻停止層314係形成 在該鋁/銅金屬層311a及阻障材料層310a及介電層304上 。一第二介電層，即金屬層間介電（IMD)層316係形成在該蝕 刻停止層3 1 4上。蝕刻停止層3 1 4及IMD層3 1 6係由具有 不同蝕刻率之材料所形成。蝕刻停止層3 14較佳由化學氣 相沉積法所作成之氮化矽或氧氮化砂。而IMD層3 1 6較佳 爲由低介電常數材料所作成，例如氧化矽、摻氟氧化矽或磷 矽玻璃。因爲氮化矽層3 14爲一緊密材料，所以可以更進一 步抑制銅原子擴散入該IMD層3 1 6。因此，確保了裝置的可 靠度。 如於第3E圖所示，IMD層316的一部份係被去除，以形 成一介層洞開口 3 1 8,其曝露出該金屬層3 1 1 a的一部份。該 IMD層316係藉由傳統光微影及蝕刻製程加以去除。由於 該蝕刻停止層314的保護，可以防止該介電層304的過度蝕 刻。該蝕刻停止層3 1 4較佳係藉由例如反應離子蝕刻之乾 鈾刻法加以去除。然後，氧電漿被用以去除殘留之光阻材料 。因爲銅層308並未露出，所以銅層308將不會在電漿蝕刻 時被氧化。因此，可以維持住金屬內連線的導電率及介層洞 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公楚：） :丨·-裝 ^--訂-------^ (請先閲讀背面之注意事項再填寫本頁) -14- 569388 kl __ _B7_______ 六、發明説明（11 ) 電阻。同時，也不會有銅離子被濺射出，以污染晶圓及製程室 的問題。另外，也由於銅層308係完全密封，所以可以防止銅 被氧電漿所氧化及銅被淸洗溶液所侵蝕。 綜上所陳，第二阻障層除了保護銅層208、308外，也可 以作爲抗反射塗層（ARC)，以防止當銅層208、308的表面於 後續曝光時之不想要的反射。 熟習於本技藝者可以知道，各種修改及變化可以在不脫 離本發明的範圍及精神下加以完成。因此，本發明包含在以 下申請專利範圍及其等效範圍內的修改及變化。 τ.. 訂iv (請先閲讀背面之注意事項再填寫本頁) 經濟部智祛財產局員工消費合作社印製 本纸張尺度適用中國國家標準（CNS ) μ規格 Τ~210Χ 297公釐)' -15-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs -11-569388 A7 __ _B7_ VI. Description of Invention (8) 2 1 4 and IMD layer 2 1 6 are formed of materials with different etching rates. The barn etch stop layer 214 is preferably silicon nitride or silicon oxynitride formed by a chemical vapor deposition method. The IMD layer 216 is preferably made of a low dielectric constant material, such as silicon oxide, fluorine-doped silicon oxide, or phosphosilicate glass. Because the silicon nitride layer 214 is a compact material, the diffusion of copper atoms into the IMD layer can be further suppressed. Therefore, the reliability of the device is ensured. Then, a part of the IMD layer 216 is removed to expose a part of the etch stop layer 214. The IMD layer 216 is removed by a conventional photolithography and etching process. Due to the protection of the uranium etch stop layer 214, excessive uranium etch of the dielectric layer 204 can be prevented. Then, a part of the stop layer 214 is etched to form a via hole opening 21 8, and the opening will expose the barrier material layer 2 10 a, as shown in FIG. 2E. The etch stop layer 214 is preferably removed by a dry uranium etching method such as reactive ion etching. The oxygen plasma is then used to remove the remaining photoresist material. Because the copper layer 208 is not exposed, the copper layer 208 will not be oxidized during plasma etching. Therefore, the conductivity of the metal interconnects and the via resistance can be maintained. At the same time, there is no problem of copper ions being sputtered out to pollute wafers and process chambers. In addition, since the copper layer 208 is completely sealed, it is possible to prevent the copper from being oxidized by the oxygen plasma and the copper from being corroded by the cleaning solution. 3A to 3E are cross-sectional views of steps for forming a double-layered embedded structure according to a second preferred embodiment of the present invention. As shown in FIG. 3A, a substrate 300 having a conductive layer 302 formed therein is provided. A dielectric layer 304 such as an oxide layer is formed on the conductor layer 302. The dielectric layer 304 is planarized. Then, a double-layer embedding opening having a via hole 305a and a trench 305b is formed in the dielectric layer 304 to expose the conductor layer 302. This double-layer paper size applies the Chinese National Standard (CNS) μ specification (210X 297 cm) (Please read the precautions on the back before filling out this page). • Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs- 12- 569388 A7 _ ^ ___ B7 V. Description of the invention (9) The method for forming the embedded opening is accomplished by, for example, the following method. A photoresist layer (not shown) is formed to expose the desired via hole area on the conductor layer 302. The dielectric layer 304 is etched using the first patterned photoresist layer as a mask. Then, a via hole 305a is formed to expose a part of the conductive layer 302. Then, the first patterned photoresist layer is removed. A second patterned photoresist layer (not shown) is formed on the dielectric layer 304. Using the second patterned photoresist layer as a mask, the dielectric layer 304 is etched to form a trench 305b. Then, the second patterned photoresist layer is removed. Then, a first barrier layer 306 is formed on the dielectric layer 304 and the inner surfaces of the dielectric hole openings 305a and the trenches 305b. A copper layer 308 is then formed on the substrate to fill the trench 305b and the via hole opening 305a. The copper layer 308 is planarized, and the dielectric layer 304 is used as a honing stop layer to form a double-layered embedded structure. In an embodiment of the present invention, the copper layer 308 may be formed by, for example, chemical vapor deposition or copper-free plating. The first barrier layer 306 is formed by, for example, chemical vapor deposition of a titanium nitride (TiN) layer. As shown in FIG. 3B, a second barrier layer 3 10 is formed on the dielectric layer 304 and the copper layer 308. The second barrier layer 310 can be made of a material that prevents oxidation of the copper layer 308 and copper atoms from diffusing into a subsequently formed dielectric layer. In this embodiment, the second barrier layer 310 may be formed of, for example, titanium nitride, titanium, titanium tungsten (TiW) alloy, and nitride nitride. The barrier layer is used to prevent copper atoms from diffusing into a nearby dielectric layer. Then, an aluminum / copper metal layer 311 is deposited on the second barrier layer 3 1 0. A patterned photoresist layer 3 1 2 is formed on the insulating / copper metal layer 3 1 1. The photoresist layer 3 1 2 is directly formed on the double-layer embedded paper scale of Shicai Guanjia County (CNS) M specification (2i〇x297 feet) " -13-Muyi-(Please read the back Please fill in this page for the matters needing attention) Order printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 569388 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 VI. Description of the invention (1) Enter the structure. In addition to this Ming / copper alloy, Cu, AlCuSi alloy or tungsten can also be deposited. Then, a photoresist layer 3 1 2 is used as an etching mask, and a part of the aluminum / copper metal layer 311 and the barrier layer 310 is removed by a reactive ion uranium halide process to form a metal layer 3 1 1 a and the barrier material layer 3 1 0a to cover the copper layer 308 of the double-layer embedded structure, as shown in FIG. 3C. Then, as shown in FIG. 3D, a conformal etch stop layer 314 is formed on the aluminum / copper metal layer 311a, the barrier material layer 310a, and the dielectric layer 304. A second dielectric layer, namely, an intermetal dielectric (IMD) layer 316 is formed on the etch stop layer 3 1 4. The etch stop layer 3 1 4 and the IMD layer 3 1 6 are formed of materials having different etching rates. The etch stop layer 3 14 is preferably silicon nitride or oxynitride sand formed by a chemical vapor deposition method. The IMD layer 3 1 6 is preferably made of a low dielectric constant material, such as silicon oxide, fluorine-doped silicon oxide, or phosphosilicate glass. Since the silicon nitride layer 3 14 is a compact material, the diffusion of copper atoms into the IMD layer 3 1 6 can be further suppressed. Therefore, the reliability of the device is ensured. As shown in FIG. 3E, a part of the IMD layer 316 is removed to form a via hole opening 3 1 8 which exposes a part of the metal layer 3 1 1 a. The IMD layer 316 is removed by a conventional photolithography and etching process. Due to the protection of the etch stop layer 314, the dielectric layer 304 can be prevented from being over-etched. The etch stop layer 3 1 4 is preferably removed by a dry uranium etching method such as reactive ion etching. An oxygen plasma is then used to remove the remaining photoresist material. Because the copper layer 308 is not exposed, the copper layer 308 will not be oxidized during plasma etching. Therefore, the electrical conductivity of the metal interconnects and the interstitial holes can be maintained. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297): 丨 ·-装 ^-Order ------- ^ (Please read the precautions on the back before filling this page) -14- 569388 kl __ _B7_______ 6. Description of the invention (11) Resistance. At the same time, there is no problem that copper ions are sputtered out to contaminate the wafer and process chamber. In addition, since the copper layer 308 is completely sealed, it is possible to prevent the copper from being oxidized by the oxygen plasma and the copper from being corroded by the washing solution. In summary, in addition to protecting the copper layers 208 and 308, the second barrier layer can also be used as an anti-reflective coating (ARC) to prevent unwanted reflection of the surfaces of the copper layers 208 and 308 during subsequent exposures. Those skilled in the art will recognize that various modifications and changes can be made without departing from the scope and spirit of the invention. Therefore, the present invention includes modifications and changes within the scope of the following patent applications and their equivalents. τ .. Order iv (please read the notes on the back before filling out this page) Printed by the Employees 'Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs This paper is printed in accordance with the Chinese National Standard (CNS) μ size T ~ 210X 297 mm)' -15-