494530 A7 5373twf.doc/008 B7 五、發明說明（丨） 本發明是有關於一種半導體元件的製造方法，且特 別是有關於一種多重金屬內連線的製造方法。 隨著積體電路元件的高度積集化，元件的尺寸逐漸 縮小，其所需的金屬內連線數目也隨之而增加。目前，半 導體元件製程使用電遷移效應極小之銅金屬作爲金屬內連 線之材料。由於銅金屬本身具有低電阻率、高抗電遷移性 以及可以以化學氣相沈積與電鍍方式成長的優點，因此在 深次微米元件其多層金屬連線的運用上備受矚目。 形成多重金屬內連線的方法之一爲雙重金屬鑲嵌製 程。其係在基底上先形成一絕緣層後，依照所需之金屬導 線的圖案以及介層窗開口的位置，蝕刻絕緣層，以形成一 水平溝渠和一垂直介層窗開口；亦即蝕刻下層絕緣層至暴 露出其下方基底之元件區或導線，以形成一垂直介層窗開 口，並且餽刻上層絕緣層，而形成一水平溝渠。然後，於 基底上沈積一金屬層，使其塡滿水平溝渠與垂直介層窗開 口，以同時形成導線與介層窗。最後，以化學機械硏磨法 將元件的表面平坦化，並再進行另一個雙重金屬鑲嵌結構 的形成，亦即水平溝渠與垂直介層窗開口的金屬鑲嵌即爲 一雙重金屬鑲嵌製程。 然而，當使用銅做爲雙重金屬鑲嵌結構之材料時， 由於後續欲形成另一介層窗開口，並暴露出銅雙重金屬鑲 嵌結構所進行的蝕刻步驟，例如反應性離子鈾刻步驟，其 電漿所產生的高能粒子可能轟擊裸露的銅金屬表面，使得 銅金屬離子濺出而沉積於開口之側壁或機台，造成產品與 3 本紙張尺度適用中國國家標準（CN’S)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂---------線494530 A7 5373twf.doc / 008 B7 V. Description of the Invention (丨) The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a multi-metal interconnect. With the integration of integrated circuit components, the size of the components has gradually decreased, and the number of metal interconnects required has also increased. Currently, semiconductors are manufactured using copper metal with minimal electromigration as the material for metal interconnects. Because copper metal has the advantages of low resistivity, high resistance to electromigration, and can be grown by chemical vapor deposition and electroplating, it has attracted much attention in the application of multilayer metal connections for deep sub-micron devices. One method of forming a multi-metal interconnect is a dual metal damascene process. It is to form an insulating layer on the substrate first, and then etch the insulating layer according to the required pattern of the metal wires and the position of the opening of the via window to form a horizontal trench and a vertical via window; that is, to etch the lower insulating layer Layer to expose the component area or conductor of the underlying substrate to form a vertical via window opening, and feed the upper insulating layer to form a horizontal trench. Then, a metal layer is deposited on the substrate so as to fill the openings of the horizontal trench and the vertical interlayer window, so as to form the wires and the interlayer window at the same time. Finally, the surface of the element is planarized by chemical mechanical honing, and then another double metal damascene structure is formed, that is, the metal damascene of the horizontal trench and the vertical interlayer window opening is a double metal damascene process. However, when copper is used as the material for the dual metal damascene structure, the subsequent etching steps, such as the reactive ion uranium engraving step, and the plasma performed by the copper dual metal damascene structure are to be followed by the formation of another interlayer window opening. The generated high-energy particles may bombard the bare copper metal surface, causing copper metal ions to splash out and deposit on the side walls or the machine of the opening, resulting in products and 3 paper sizes that are applicable to Chinese National Standard (CN'S) A4 (210 X 297) Li) (Please read the notes on the back before filling this page) Order --------- line
經濟部智慧財產局員工消費合作社印製 494530 A7 5373twf.d〇c/008 B7 經濟部智慧財產局員工消費合作社印剩衣 五、發明說明（>) 機台均有銅污染的問題發生。 再者，由於在後續介層窗開口蝕刻完後需利用氧電 槳去除殘留的光阻層，因氧易與銅金屬產生氧化反應，造 成所裸露的銅金屬氧化生成鬆散之氧化銅，導致後續形成 阻障層會有問題，且致使金屬連線的導電性降低以及介層 窗之阻値（via resistance)增加。 此外，一般於介層窗開口形成之後，通常會進行溶 劑淸洗步驟，以去除沉積於介層窗開口側壁之聚合物。然 而’—般有機溶劑皆含有水份，易造成銅腐蝕(Cu Coirosion) 與銅氧化而生成氧化銅問題的發生，而目前用來淸除沉積 於介層窗開口側壁之聚合物所使用的浸沒式(bath type)化 學槽，由於其溶劑內殘留之銅含量不易控制，可能將銅金 屬離子再次沉積於晶片，造成後續晶片的污染而無法適 用。 因此，本發明提出一種多重金屬內連線的製造方法， 其係於基底上形成一具有雙重金屬鑲嵌開口之第一介電 層’其中雙重金屬鑲嵌開口係包括一第一介層窗開口與一 溝渠，第一介層窗開口暴露出下方部分之基底。之後，在 溝渠與介層窗開口的側壁形成一共形的第一阻障層，並於 溝渠與介層窗開口中塡入一導電層。然後，過度硏磨導電 層，於導電層之表面形成一凹槽，續於導電層與第一介電 層上形成第二阻障層，其後，於基底上形成第二介電層’ 定義第二介電層，而於第二介電層中形成第二介層窗，暴 露部分第二阻障層。 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ----- 訂---------線Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 494530 A7 5373twf.doc / 008 B7 Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (>) The machine has copper pollution. In addition, since the remaining photoresist layer needs to be removed by using an oxygen paddle after the subsequent etching of the opening of the interlayer window, the oxygen easily reacts with the copper metal, causing the exposed copper metal to oxidize to form loose copper oxide, which leads to subsequent The formation of the barrier layer is problematic and results in a decrease in the conductivity of the metal wiring and an increase in the via resistance of the via. In addition, after the formation of the via window, a solvent washing step is usually performed to remove the polymer deposited on the sidewall of the via window. However, the general organic solvents all contain water, which can easily cause copper corrosion (Cu Coirosion) and copper oxidation to generate copper oxide. At present, it is used to eliminate the immersion of the polymer deposited on the sidewall of the opening of the interlayer window. Bath type chemical tanks, because the copper content remaining in the solvent is not easy to control, copper metal ions may be deposited on the wafer again, resulting in contamination of subsequent wafers and making it unsuitable. Therefore, the present invention proposes a method for manufacturing a multi-metal interconnect, which forms a first dielectric layer having a double metal damascene opening on a substrate, wherein the double metal damascene opening includes a first dielectric window opening and a Trench, the opening of the first interlayer window exposes the underlying substrate. After that, a conformal first barrier layer is formed on the sidewall of the trench and the opening of the via, and a conductive layer is inserted into the trench and the opening of the via. Then, the conductive layer is excessively honed to form a groove on the surface of the conductive layer, a second barrier layer is formed on the conductive layer and the first dielectric layer, and then a second dielectric layer is formed on the substrate. A second dielectric layer, and a second dielectric window is formed in the second dielectric layer, exposing part of the second barrier layer. 4 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ----- Order --------- line
494530 A7 5373twf.doc/ 008 R7 五、發明說明（巧） 此外，本發明亦可於形成第二阻障層之後，於第二 阻障層與第一介電層上形成一蝕刻終止層，塡滿該凹槽。 另外，本發明亦可於形成該第二阻障層，對第二阻 障層進行化學機械硏磨步驟之後，在第二阻障層與第一介 電層上形成一蝕刻終止層。 當本發明進行蝕刻以形成介層窗開口時，位於銅導 電層上的阻障層可防止銅導電層外露，以阻擋銅金屬離子 在蝕刻過程中被高能粒子濺出，而造成產品與機台銅污染 的問題發生。 依照本發明所提出之一種雙重金屬鑲嵌的製造方 法，其係在形成銅導電層之後，於銅導電層上覆蓋一層阻 障層，用來隔絕銅導電層與空氣，以防止氧化銅的發生。 又，由於本發明之雙重金屬鑲嵌的製造方法，其銅 導電層上的阻障層可防止銅導電層外露，故無銅氧化成氧 化銅與銅腐蝕的問題發生。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 第1A至1D圖繪示依照本發明一第一較佳實施例的 一種多重金屬內連線的製造流程剖面圖； 第2A至2B圖繪示依照本發明一第二較佳實施例的 一種多重金屬內連線的製造流程剖面圖；以及 第3A至3C圖繪示依照本發明一第二較佳實施例的 一種多重金屬內連線的製造流程剖面圖。 5 (請先閱讀背面之注意事項再填寫本頁) 訂---------線494530 A7 5373twf.doc / 008 R7 V. Description of the Invention (Invention) In addition, the present invention can also form an etch stop layer on the second barrier layer and the first dielectric layer after forming the second barrier layer. Fill the groove. In addition, the present invention can also form an etch stop layer on the second barrier layer and the first dielectric layer after the second barrier layer is formed, and the second barrier layer is subjected to a chemical mechanical honing step. When the present invention is etched to form an interlayer window opening, the barrier layer on the copper conductive layer can prevent the copper conductive layer from being exposed to prevent copper metal ions from being splashed out by high-energy particles during the etching process, causing products and machines. The problem of copper pollution occurred. According to the present invention, a method for manufacturing a dual-metal damascene is formed by forming a copper conductive layer and then covering the copper conductive layer with a barrier layer to isolate the copper conductive layer from the air to prevent the occurrence of copper oxide. In addition, due to the manufacturing method of the dual metal damascene of the present invention, the barrier layer on the copper conductive layer can prevent the copper conductive layer from being exposed, so there is no problem of copper oxidation to copper oxide and copper corrosion. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail in conjunction with the accompanying drawings as follows: Figures 1A to 1D illustrate a first embodiment of the present invention. A cross-sectional view of a manufacturing process of a multi-metal interconnect in a first preferred embodiment; FIGS. 2A to 2B are cross-sectional views of a manufacturing process of a multi-metal interconnect in accordance with a second preferred embodiment of the present invention; and 3A to 3C are cross-sectional views illustrating a manufacturing process of a multi-metal interconnect according to a second preferred embodiment of the present invention. 5 (Please read the notes on the back before filling this page) Order --------- line
經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 45 9 ο 經濟部智慧財產局員工消費合作社印製 A7 5 37 3twf.doc/ 0 0 8 B7 -------------------—-- 、發明說明（4) 圖式之簡單說明： 1〇〇 :基底 102 :金屬內連線結構 104、110 :阻障層 106、112 :介電層 108 :凹槽 110a :自動對準阻障層 114 :介層窗 212、212a :蝕刻終止層 第一實施例 第1A至1D圖繪示依照本發明一較佳實施例的一種 多重金屬內連線的製造流程剖面圖 請參照第1A圖，首先，提供一基底100，基底100 上例如已形成元件或導線（未繪示）。之後，形成一金屬內 連線結構102,其例如爲銅金屬內連線結構。銅金屬內連 線結構102較佳是利用雙重金屬鑲嵌技術形成。金屬內連 線結構102的形成方法例如包括在基底100上先形成一介 電層106，並將其平坦化後，再依照所需之導線的圖案以 及介層窗開口的位置，蝕刻介電層1〇6，以形成一水平溝 渠和一垂直介層窗開口（未標示於圖中）；亦即蝕刻下層絕 緣層至暴露出其下方基底1〇〇之元件區或導線，以形成一 垂直介層窗開口，並且蝕刻上層絕緣層，而形成一水平溝 渠。然後，形成一共形之阻障層（未繪示）於介電層106、 水平溝渠與垂直介層窗開口，其後，於基底100上沈積一 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） (請先閱讀背面之注意事項再填寫本頁) -------- 訂----- 線#- 494530 5373twf·doc/008 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（< ) 導電層（未繪示），使其塡滿水平溝渠與垂直介層窗開口， 以同時形成導線與介層窗。導電層之材質例如爲銅，其例 如以濺鍍法形成。阻障層之材質例如包括氮化鈦(TiN)、氮 化鎢（WN)或氮化钽（TaN)，而其例如以化學氣相沈積法形 成。其後，進行一平坦化步驟，例如是化學機械硏磨步驟， 去除部分的阻障層與介電層106表面上之導電層，以形成 阻障層104與一金屬內連線結構102。 對金屬內連線結構102進行一過度硏磨步驟，以於 金屬內連線102表面上形成一凹槽1〇8。 請參照第1B圖，於介電層1 〇6與金屬內連線1 〇2上， 形成一阻障層110，並塡滿凹槽108。阻障層11〇之材質 例如爲鈦、氮化鈦、钽、氮化鉅、鎢、氮化鎢及其合金或 其任意組合。阻障層110例如以濺鍍法形成。 請參照第1C圖，進行一化學機械硏磨步驟，去除介 電層106上之阻障層110，以於金屬內連線1〇2上，形成 一自動對準阻障層110a。 請參照第1D圖，於基底1〇〇上形成另一介電層112， 覆蓋介電層106與金屬內連線1〇2上之自動對準阻障層 ll〇a。之後，定義介電層ip，其例如先形成一光阻層(未 繪示於圖中），然後進行蝕刻以於介電層U2中形成一介 層窗Π4，並暴露出部分之自動對準阻障層u〇a。其中蝕 刻以形成介層窗114較佳的方式包括乾式蝕刻法，例如是 以反應性離子蝕刻法形成。 e 接著，在介層窗開口 114蝕刻完後即利用氧電漿去 7 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱) ----一- (請先閱讀背面之注意事項再填寫本頁) --------#· 線#- 494530 A7 5373twf.d〇c/008 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（心） 除殘留的光阻層。由於導電層102上方覆蓋有阻障層 110a，導電層102並無外露，故銅導電層102不會因氧電 漿而氧化生成鬆散之氧化銅，所以亦不會造成金屬連線的 導電性降低以及介層窗之阻値增加的問題發生。最後，通 常會進行一道淸除的步驟，以去除位於介層窗開口 114側 壁之聚合物。 本發明的特徵在於銅導電層102上形成有一阻障層 110a，而在介層窗開口 114的蝕刻過程中，因蝕刻停止在 阻障層ll〇a，而避免了銅導電層1〇2之銅金屬離子的濺 出，故產品與機台均無銅污染的問題發生。 另外，本發明之介層窗開口 114的製程與現有製程 相同，故相容性高，極適合廠商的生產與安排。 再者，因銅導電層102無外露，故不會發生銅氧化 生成氧化銅，以及在淸洗步驟中，溶劑所引發之銅腐蝕與 銅氧化的問題。 此外，因銅導電層102無外露，銅污染的問題不會 發生，故目前所使用的化學槽可繼續使用，而無銅金屬離 子再次沉積於晶片，污染後續晶片之虞慮。 而且，以目前金屬內連線的製作而言，採蝕刻停止 於金屬內連線上方之阻障層之製程（stop on top-barrier)所 形成的元件較爲穩定，其因爲頂端阻障層可以發揮阻擋的 功能’以避免銅原子發生電遷移而擴散至介電層中，而得 以維持元件的可靠度。 第二實施例 8 (請先閱讀背面之注意事項再填寫本頁)Printed on the paper by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The paper standard is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 45 9 ο Printed by the Employees’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 0 8 B7 -----------------------, Description of the invention (4) Brief description of the drawings: 100: Substrate 102: Metal interconnect structure 104 , 110: barrier layer 106, 112: dielectric layer 108: groove 110a: automatic alignment barrier layer 114: dielectric window 212, 212a: etch stop layer The first embodiment, 1A to 1D, is shown in accordance with this A cross-sectional view of a manufacturing process of a multi-metal interconnect according to a preferred embodiment of the present invention is shown in FIG. 1A. First, a substrate 100 is provided. For example, a component or a wire (not shown) is formed on the substrate 100. After that, a metal interconnect structure 102 is formed, which is, for example, a copper metal interconnect structure. The copper metal interconnect structure 102 is preferably formed using a dual metal damascene technique. The method for forming the metal interconnect structure 102 includes, for example, first forming a dielectric layer 106 on the substrate 100 and planarizing it, and then etching the dielectric layer in accordance with the pattern of the required wires and the position of the opening of the dielectric window. 106 to form a horizontal trench and a vertical via window opening (not shown in the figure); that is, the underlying insulating layer is etched to expose the component area or wiring of the underlying substrate 100 to form a vertical via The layer window is opened, and the upper insulating layer is etched to form a horizontal trench. Then, a conformal barrier layer (not shown) is formed on the dielectric layer 106, the horizontal trench and the vertical interstitial window openings. Thereafter, a 6 paper size is applied to the Chinese National Standard (CNS) A4. Specifications (210 x 297 mm) (Please read the notes on the back before filling this page) -------- Order ----- Line #-494530 5373twf · doc / 008 B7 Intellectual Property Bureau, Ministry of Economic Affairs Printed by Employee Consumer Cooperatives 5. Invention Description (<) A conductive layer (not shown) that fills horizontal trenches and vertical interstitial window openings to form wires and interstitial windows simultaneously. The material of the conductive layer is, for example, copper, and it is formed, for example, by a sputtering method. The material of the barrier layer includes, for example, titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN), and it is formed, for example, by a chemical vapor deposition method. Thereafter, a planarization step, such as a chemical mechanical honing step, is performed to remove part of the barrier layer and the conductive layer on the surface of the dielectric layer 106 to form the barrier layer 104 and a metal interconnect structure 102. An excessive honing step is performed on the metal interconnect structure 102 to form a groove 108 on the surface of the metal interconnect structure 102. Referring to FIG. 1B, a barrier layer 110 is formed on the dielectric layer 106 and the metal interconnect 100, and the groove 108 is filled. The material of the barrier layer 110 is, for example, titanium, titanium nitride, tantalum, nitride nitride, tungsten, tungsten nitride, or an alloy thereof or any combination thereof. The barrier layer 110 is formed by, for example, a sputtering method. Referring to FIG. 1C, a chemical mechanical honing step is performed to remove the barrier layer 110 on the dielectric layer 106 to form an automatic alignment barrier layer 110a on the metal interconnection line 102. Referring to FIG. 1D, another dielectric layer 112 is formed on the substrate 100 to cover the dielectric layer 106 and the automatic alignment barrier layer 110a on the metal interconnects 102. After that, a dielectric layer ip is defined. For example, a photoresist layer (not shown in the figure) is formed first, and then etching is performed to form a dielectric window Π4 in the dielectric layer U2, and a part of the automatic alignment resistance is exposed. Barrier layer u〇a. The preferred method for etching to form the interlayer window 114 includes dry etching, such as, for example, reactive ion etching. e Then, after the opening 114 of the interlayer window is etched, the oxygen plasma is used to remove the 7 paper size. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297 public love) ---- One-(Please read the back first Please fill in this page for the matters needing attention) -------- # · 线 #-494530 A7 5373twf.d〇c / 008 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Photoresist layer. Since the conductive layer 102 is covered with a barrier layer 110a and the conductive layer 102 is not exposed, the copper conductive layer 102 will not be oxidized by the oxygen plasma to form loose copper oxide, so the conductivity of the metal wiring will not be reduced. And the problem of increased resistance of the interlayer window occurs. Finally, an eradication step is usually performed to remove the polymer located on the side wall of the via 114 of the via. The invention is characterized in that a barrier layer 110a is formed on the copper conductive layer 102, and during the etching of the via 114 of the interlayer window, the etching stops at the barrier layer 110a, thereby avoiding the copper conductive layer 102. Copper metal ions are spattered, so there is no copper pollution problem in the product and the machine. In addition, the manufacturing process of the interlayer window opening 114 of the present invention is the same as the existing manufacturing process, so it has high compatibility and is very suitable for manufacturers' production and arrangement. In addition, since the copper conductive layer 102 is not exposed, the problems of copper corrosion and copper oxidation caused by the solvent during the rinsing step will not occur due to copper oxidation. In addition, since the copper conductive layer 102 is not exposed, the problem of copper contamination will not occur. Therefore, the chemical tank currently used can continue to be used, and no copper metal ions are deposited on the wafer again, which may contaminate subsequent wafers. Moreover, in terms of the current production of metal interconnects, the elements formed by the process of stop on top-barrier etched to stop above the metal interconnects are relatively stable, because the top barrier layer can Play a blocking function 'to prevent copper atoms from electromigrating and diffusing into the dielectric layer, thereby maintaining the reliability of the device. Second Embodiment 8 (Please read the precautions on the back before filling in this page)
•I · 線#1 本紙張义度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 494530 A7 5373twf.doc/008 β7 五、發明說明（Q ) 第2A至2B圖繪示依照本發明一第二較佳實施例的 一種多重金屬內連線的製造流程剖面圖。 請參照第2A圖，首先，提供一如第ic圖所示之結 構，於阻障層110a形成於金屬內連線1〇2及塡滿金屬內 連線102表面的凹槽之後，於基底10〇上形成一蝕刻終止 層212，覆蓋介電層106與金屬內連線102上方之阻障層 ll〇a。蝕刻終止層212之材質例如爲氮化矽，其例如以電 漿加強化學氣相沈積法(PECVD)形成。 請參照第2B圖，藉由光阻層（未繪示於圖）之定義， 利用微影與蝕刻製程，去除部分介電層112以暴露出部分 飩刻終止層212。由於介電層1〇6與介電層112之間具有 一蝕刻終止層212，故蝕刻介電層112時，可控制蝕刻深 度，不至於不慎而過度蝕刻到介電層1〇6。 接著，再利用一蝕刻製程，去除部分蝕刻終止層212， 以形成一暴露出部分自動對準阻障層ll〇a之介層窗開口 114 ’其較佳的方式包括乾式蝕刻法，例如是以反應性離 子鈾刻法形成。 値得一提的，本實施例中蝕刻終止層212亦可於第1B 圖形成阻障層110之後，平坦化蝕刻終止層212以形成第 1C圖之結構之前形成，如第3A圖中所繪示。亦即可先於 形成阻障層110覆蓋介電層106與金屬內連線1〇2，之後 於阻障層110上形成一蝕刻終止層212。接著，請參照第 3B圖，續進行一平坦化步驟，去除部分蝕刻終止層212 與金屬內連線102上的阻障層110，以於金屬內連線ι〇2 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --------訂--------- 494530 A7 B7 5373twf.doc/008 五、發明說明（7) 上开夕成触刻終止層212a與阻障層11 〇a。此平坦化步驟例 如以化學機械硏磨法進行。 (請先閱讀背面之注意事項再填寫本頁) 之後，請參照第3C圖，於基底100上形成介電層112， 定義介電層112以暴露出部分蝕刻終止層212a。接著，再 過度蝕刻以去除暴露出的蝕刻終止層212,以形成一介層 窗開口 114，暴露出部分自動對準阻障層n〇a。此步驟較 佳的方式包括乾式蝕刻法，例如是以反應性離子蝕刻法形 成。 接著，在介層窗開口 114蝕刻完後即利用氧電漿去 除殘留的光阻層。由於導電層1〇2上方覆蓋有阻障層110a 與蝕刻終止層212a，導電層1〇2並無外露，故銅導電層1〇2 不會因氧電漿而氧化生成鬆散之氧化銅，所以亦不會造成 金屬連線的導電性降低以及介層窗之阻値增加的問題發 生。最後，通常會進行一道淸除的步驟，以去除位於介層 窗開口 114側壁之聚合物。 經濟部智慧財產局員工消費合作社印製 本發明的特徵在於銅導電層102上形成有一阻障層 ll〇a，而在介層窗開口 114的蝕刻過程中，因蝕刻停止在 阻障層110a，而避免了銅導電層1〇2之銅金屬離子的濺 出，故產品與機台均無銅污染的問題發生。 另外，本發明之介層窗開口 114的製程與現有製程 相同，故相容性高，極適合廠商的生產與安排。 再者，因銅導電層102無外露，故不會發生銅氧化 生成氧化銅，以及在淸洗步驟中，溶劑所引發之銅腐蝕與 銅氧化的問題。 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 494530• I · Line # 1 This paper is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 494530 A7 5373twf.doc / 008 β7 V. Description of the invention (Q 2A to 2B are cross-sectional views illustrating a manufacturing process of a multi-metal interconnect according to a second preferred embodiment of the present invention. Please refer to FIG. 2A. First, a structure as shown in FIG. Ic is provided. After the barrier layer 110a is formed on the metal interconnection line 102 and the groove on the surface of the metal interconnection line 102, the substrate 10 is formed. An etch stop layer 212 is formed thereon to cover the dielectric layer 106 and the barrier layer 110a over the metal interconnect 102. The material of the etch stop layer 212 is, for example, silicon nitride, which is formed by, for example, plasma enhanced chemical vapor deposition (PECVD). Referring to FIG. 2B, by using the definition of a photoresist layer (not shown), a part of the dielectric layer 112 is removed by using a lithography and etching process to expose a part of the etch stop layer 212. Since there is an etch stop layer 212 between the dielectric layer 106 and the dielectric layer 112, when the dielectric layer 112 is etched, the etching depth can be controlled so as not to accidentally overetch the dielectric layer 106. Then, an etching process is used to remove a part of the etch stop layer 212 to form a via window opening 114 'that exposes a part of the automatic alignment barrier layer 110a. A preferred method includes dry etching, such as Reactive ion uranium etching method is formed. It should be mentioned that, in this embodiment, the etch stop layer 212 may be formed after the barrier layer 110 is formed in FIG. 1B, and the etch stop layer 212 is planarized to form the structure in FIG. 1C, as shown in FIG. 3A Show. That is, first, the barrier layer 110 is formed to cover the dielectric layer 106 and the metal interconnects 102, and then an etch stop layer 212 is formed on the barrier layer 110. Next, referring to FIG. 3B, a planarization step is continued to remove a part of the etch stop layer 212 and the barrier layer 110 on the metal interconnect 102, so that the metal interconnect ι02 9 This paper is applicable to China Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) -------- Order --------- 494530 A7 B7 5373twf.doc / 008 V. Description of the invention (7) The upper etch stop layer 212a and the barrier layer 11a are formed. This planarization step is performed, for example, by a chemical mechanical honing method. (Please read the precautions on the back before filling this page) After that, please refer to FIG. 3C to form a dielectric layer 112 on the substrate 100 and define the dielectric layer 112 to expose a part of the etch stop layer 212a. Next, over-etching is performed to remove the exposed etch stop layer 212 to form a via window opening 114, and the exposed portion is automatically aligned with the barrier layer noa. A preferred method of this step includes dry etching, for example, by reactive ion etching. Then, after the via 114 of the via is etched, the remaining photoresist layer is removed by using an oxygen plasma. Since the conductive layer 102 is covered with the barrier layer 110a and the etching stop layer 212a, the conductive layer 102 is not exposed, so the copper conductive layer 102 will not be oxidized by the oxygen plasma to form loose copper oxide, so It also does not cause problems such as a decrease in the conductivity of the metal wiring and an increase in the resistance of the interlayer window. Finally, an eradication step is usually performed to remove the polymer located on the sidewall of the via 114 of the via. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the present invention is characterized in that a barrier layer 110a is formed on the copper conductive layer 102, and during the etching of the via 114 of the interlayer window, the etching stops at the barrier layer 110a. And the copper metal ions of the copper conductive layer 102 are prevented from splattering, so the problem of no copper pollution occurs in the product and the machine. In addition, the manufacturing process of the interlayer window opening 114 of the present invention is the same as the existing manufacturing process, so it has high compatibility and is very suitable for manufacturers' production and arrangement. In addition, since the copper conductive layer 102 is not exposed, the problems of copper corrosion and copper oxidation caused by the solvent during the rinsing step will not occur due to copper oxidation. 10 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 494530
五、發明說明（q ) 此外，因銅導電層102無外露，銅污染的問題不會 發生，故目前所使用的化學槽可繼繪使用，而無銅金屬離 子再次沉積於晶片，污染後續晶片之虞慮° 而且，以目前金屬內連線的製作而言，採蝕刻停止 於金屬內連線上方之阻障層之製程（st0p on t0P_barrier)所 形成的元件較爲穩定，其因爲頂端阻障層可以發揮阻擋的 功能，以避免銅原子發生電遷移而擴散至介電層中，而得 以維持元件的可靠度。 雖然本發明已以兩個較佳實施例揭露如上，然其並 非用以限定本發明，任何熟習此技藝者，在不脫離本發明 之精神和範圍內，當可作各種之更動與潤飾，因此本發明 之保護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) • --------訂---------線V. Description of the invention (q) In addition, since the copper conductive layer 102 is not exposed, the problem of copper pollution will not occur. Therefore, the chemical tanks currently used can be used for subsequent painting, and copper-free metal ions are deposited on the wafer again, which will pollute subsequent wafers Concerns ° Furthermore, in terms of the current production of metal interconnects, the components formed by the process of stabilizing the barrier layer (st0p on t0P_barrier) stopped above the metal interconnects are relatively stable due to the top barrier The layer can function as a barrier to prevent copper atoms from electromigrating and diffusing into the dielectric layer, thereby maintaining the reliability of the device. Although the present invention has been disclosed as above with two preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) • -------- Order --------- line
經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm)