3048twf/005 ； 43Π〇〇 0 A7 B7 虹"部中""ίτ而m τ,消於合竹.^印5<· 五、發明説明（J ) 本發明是有關於一種介層窗（Via)的製造方法，且特 別是有關於一種增加未接著介層窗（Unlanded Via)之接觸 面積的方法。 隨著積體電路中所需導線層數目的增加，兩層以上的金 屬層設計，便逐漸的成爲許多積體電路所必需採用的方 式。在金屬層之間常以內金屬介電層（Inter-Metal Dielectric ; IMD)加以隔離，其中用來連接上下兩層金屬 層的導線，在半導體工業上即稱之爲介層窗。 傳統的內連線製作方法是在用以隔離金屬層的絕緣層 上，例如氧化矽層，沈積一層金屬層後，再將金屬層定義 出預定的導線圖案，繼之使導線層之間形成一垂直連接的 介層窗。然後於介層窗開口中塡入與導電層相同材質或不 同材質的金屬，用以完成導線層的垂直連接。 習知製造介層窗和內連線的方法，通常是介層窗和內連 線分兩步驟完成，即在金屬層上方形成介電層，之後在介 電層上方定義光阻（Photoresist)層，然後利用蝕刻技術完 成介層窗開口，並利用沈積法在此介層窗開口中沈積導電 材料以完成介層窗的製做，之後沈積金屬層’並定義金屬 層，最後再沈積內金屬介電層。 然而，隨著半導體製程線寬的減小與積集度的增加’相 對的在定義介電層以形成介層窗開口時，極易發生對準失 ，誤（Misalignment)的現象，進而使後續形成於介層窗開口 中的插塞（Plug)與金屬導線的接觸面積減小’因此造成其 接觸電阻値的增加。 本紙張尺度適州中國國家標率（CNS ) A4規格（210X 297公楚) (請先閱讀背面之注意事項再填寫本f} r ^〇48twi7〇05 r 43 / 0 0 0 at ____' ____B7___ 五、發明説明（〆） 第1A圖至第IE圖係繪示傳統式未接著介層窗之製造 流程的剖面示意圖。 請參照第1A圖，首先提供具有一平坦表面的基底結構 100 (基底結構100中的元件並未完全畫出），並且於基底 結構100上形成一層導電層〗02，例如以濺鍍（sputtermg) 的方式或化學氣相沈積法（CVD)形成的弟、鋁、鋁銅合 金等金屬材料所構成的導電層102。 請參照第1B圖，利用傳統的微影、蝕刻製程定義導電 層102 ’例如以非等向性的蝕刻法，而在基底結構1〇〇上形 成導線 102a, 102b, 102c。 請參照第1C圖，在基底結構100上形成一層介電層 104，例如以化學氣相沈積法（CVD)沈積的氧化矽層，且 覆蓋導線102a, 102b, 102c。之後，進行介電層1〇4的平坦 化，例如以化學機械硏磨法（CMP)，直到導線l〇2b上之 介電層104的厚度，約與後續欲形成之介層窗的高度相當。 請參照第1D圖，利用傳統的微影、蝕刻程序，在介電 層104a中形成一介層窗開口 106，且暴露出部份導線l〇2b 的表面。由於在定義介層窗開口 106時，發生了_對準失誤， 所以介電層l〇4a中的介層窗開口 106並未完全地暴露出導 線l〇2b的表面，因而形成赛接著的介層窗開口。當蝕刻時 間過長的時候，甚至會造成介電層l〇4a的蝕穿，進而到達 基底結構100中的另一導電區（圖中未顯示）。如此一來， 在後續形成介層窗之後’會造成不正常的導通，而引起元 件的失效。 4 ---------餐--------訂|-----0 (誚先Μ讀背面之注意事項再填巧本頁} 本紙张尺度適Λ]中國國家標準（CNS ) Λ4規格（210X 297公釐） A7 437000 s_______ 五·、發明説明（）） 請參照第1E圖，於蝕刻介電層104a所形成的介層窗 開口 106中，沈積一層與介層窗開口 106的表面共形的 (Conformal)黏著/阻障層11〇,例如是鈦/氮化魅（Τι/ΤιΝ)、 Λ/氮it鉅（Ta/TaN)等的導電材料’用以增加隨後沈積的 導電層與其他材質間的附著力。 接著，在介電層l〇4a上沈積一層導電層，例如是以化 學氣相沈積法（CVD)形成_金屬曆，且塡滿介層窗開 口 106，進而與金屬線l〇2b電性耦接。之後，移除介電層 l〇4a上過剩的導電層，例如使用回蝕刻（Etching Back)的 方式或以化學機械硏磨法（CMP)，用以移除介電層104a 上過剩的導電層，而在介電層104a中形成與金屬線102b 電性耦接的介JS窗插塞1丨2。 如上所述，因爲在定義介層窗開口時，發生了對準失 誤，所以造成了未接著介層窗開口，在後續形成介層窗之 後，介層窗插塞與下層導線的接觸面積縮小，因而引起介 層窗插塞與下層導線之接觸電阻値增加的問題。 有鑑於此，本發明的主要目的就是在提供一種_增加走擅 著介層窗之接觸面積的方法，在因爲對準失誤而形成未接 著介層窗的情況之下，仍然可以增加介層窗插塞與導線之 間的菽觸積，介__層窗插_導線_之間的捽.觸電阻 値。 ， 根據本發明的主要目的，提出一種，包括：提供一基底 結構’並且於基底結構上形成一導線。之後，在導線上形 成-層介電層，續於介電層中形成一介層窗開口，且暴露 5 本纸張尺度適州中因國家標芈（CNS Μ4規格（210X297公楚） I I I I I I 訂 «—i tt [ . 絲 (讀先閱讀背面之注意事項再填寫本頁) -"'"屮呔ίτ·4(·^::=ί-τ消於合竹如印來 3 04i<twtV〇〇5 437 0 0 0 a? B7 五、發明説明（十） 出部份的導線。接著，去除介層窗開口_中叛屋霞之部份 —的導線’而形成一凹陷區。然後，在介層窗開口和凹陷區 中形成與導線電性耦接的插塞。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂’下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖至第1E圖係繪示傳統式未接著介層窗之製造 流程的剖面示意圖；以及 第2A圖至第2F圖係繪示根據本發明之一較佳實施 例’一種增加未接著介層窗之接觸面積之製造流程的剖面 示意圖。 圖式之標記說明： 100, 200 基底結構| 102, 202 導電層 102a, 102b, 102c, 202a, 202b, 202c 導線 104, 104a, 204, 204a 介電層 106, 206 介層窗開U 110,210 黏著/阻障層 112,212 插塞 208 凹陷區 實施例 第2A圖至第2F圖係繪示根據本發明之一較佳實施 例，一種增加未接著介層窗之接觸面積之製造流程的剖面 ---------裝-------訂-------線 (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度诚扣中國國家樣準< CNS ) Α4規格（2丨0Χ 297公釐） 3048twt'/005 f ' 437 Q0 0 A7 ____；_____ B7 五、發明説明（Γ) 示意圖。 請參照第2A圖，首先提供具有一平坦表面的基底結構 200 (基底結構200中的元件並未完全畫出），並且於基底 結構200上形成一層導電層202,例如以濺鍍的方式或化學 氣相沈積法（CVD)形成的銅、鋁' 鋁銅合金等金屬材料 所構成的導電層202。 請參照第2B圖’利用傳統的微影、蝕刻製程定義導電 層202，例如以非等向性的蝕刻法，而在基底結構200上形 成導線 202a，202b, 202c。 請參照第2C圖，在基底結構200上形成一層介電層 204，例如以化學氣相沈積法（CVD)沈積的氧化矽層，且 覆蓋導線202a, 202b, 202c。之後，進行介電層204的平坦 化，例如以化學機械硏磨法（CMP)，直到導線202b上之 介電層204的厚度，約與後續欲形成之介層窗的高度相當。 請參照第2D圖，利用傳統的微影、蝕刻程序，例如是 非等向性蝕刻法，在介電層204a中形成一介層窗開口 206，且暴露出部份導線202b的表面。由於在定義介層窗 開口 206時，發生了對準失誤，所以介電層204a中的介層 窗開口 206並未完全地暴露出導線202b的表面，因而形成 未接著介層窗開口。 請參照第2E圖，去除部份的導線202b，例如使用濕式 蝕刻法（Wet Etching)，選擇對於導線202b具有較高蝕刻 率的蝕刻劑，蝕刻掉介層窗開口 2〇6中所暴露出之部份的 導線202b，而在導線202b與介層窗開口 206相接處形成凹 7 本纸張尺度適扣中·^圏家標準（CNS)Α4规格（210x297公釐） —--------¾---------訂-------0 (詞先閱讀背面之注意事颂再填踔本頁} ^ 0 481wf 005 43 ^ U 0 0 A7 B7 其 五、發明説明（“） 陷區208，進而使介層窗開口 2〇6中所暴露出之_線 的面積增大。如此一來，在後續所形成之介層窗插寒， 與導線202b之接觸面積將增加。 參照第2F圖，在介電層204a中的介層窗開口 υ6輿叫 陷區2〇8中，沈積一層與介層窗開口 2〇6的表面和凹^ 208的表面共形的黏著/阻障層210，例如是鉄 (Ti/TiN)、鉅/氮化钽（Ta/TaN)等的導電材料， 现 I ί曾 加隨後沈積的導電層與其他材質間的附著力。 接著，在基底結構200上沈積一層導電層，例如是以化 學氣相沈積法（CVD)形成的鎢金屬層’且至少塡滿介層 窗開口 206和凹陷區208，進而與導線202b暴露於凹陷區 208的表面相接觸。之後’移除介電層2〇4a上的部份導電 層，例如使用回蝕刻的方式或化學機械硏磨法（CMP)， 直到暴露出介電層204a’而在介電層204a中形成與導線 202b電性耦接的介層窗插塞212。 綜上所述，本發明的特徵在於： 1.習知在定義介層窗開口，如果發生了對準失誤，而 造成了未接著介層窗開口時，其在後繪形成介靥窗之後， 介層窗插塞與下層導線的接觸面積會減小’因而引起介層 窗插塞與下層導線之接觸電阻値增加的問題° 而本發明的方法可以增加層尋_， , 接觸匣·積，亦即在對準失誤的介層窗開口形成後，去除介 層窗開口所暴露出之部份的下層導線’而在導線與介層窗 開U相接處形成凹陷區’此凹陷區在塡入導電材料以形成 ，丨^ 裳--^------ίτ~------線 「筇先閑讀背面之注意事項再镇ίξ本頁) ΐίΜ 部中呔^u Τ,ί/J於合竹itiF^. 本紙張尺度適川中國國家榇準（CNS ) A4規格（210x297公釐} 3〇48twf/005 437 u υ 〇 A7 B7 五、發明説明（]) 插塞後，可以i曾加導線與介jf窗龜直之_.間_的.接觸面.積，因 此可以避免因爲對準失誤而引起之導線與介層窗插塞之間 的§觸電阻値开高的問題。 2.本發明的製程均與現有的製程相容，極適合廠商的 生產安排。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內’當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (誚先閱讀背面之注意事項再填寫本頁) . 、-° 本紙張尺度適用中圈國家標準（CNS ) Λ4規格（210X297公釐）3048twf / 005; 43Π〇〇0 A7 B7 Rainbow " Ministry " " ίτ Er m τ, disappear in combination with bamboo. ^ 印 5 < · V. Description of the invention (J) The present invention relates to an interlayer window (Via) manufacturing method, and in particular, relates to a method for increasing a contact area of an unlanded via. With the increase in the number of conductor layers required in integrated circuits, the design of two or more metal layers has gradually become the necessary method for many integrated circuits. Intermetallic layers (IMD) are often used for isolation between metal layers. The wires used to connect the upper and lower metal layers are called dielectric windows in the semiconductor industry. The traditional method of making interconnects is to deposit a metal layer on an insulating layer used to isolate a metal layer, such as a silicon oxide layer, and then define the metal layer to define a predetermined wire pattern, and then form a wire between the wire layers. Vertically connected vias. Then insert a metal of the same material or a different material from the conductive layer into the opening of the via window to complete the vertical connection of the wire layer. Known methods for manufacturing dielectric windows and interconnects are usually completed in two steps, that is, forming a dielectric layer above the metal layer, and then defining a photoresist layer above the dielectric layer , And then use an etching technique to complete the opening of the interlayer window, and use a deposition method to deposit a conductive material in the interlayer window opening to complete the fabrication of the interlayer window, then deposit a metal layer and define the metal layer, and finally deposit the inner metal interlayer Electrical layer. However, with the decrease of the semiconductor process line width and the increase of the accumulation degree, when the dielectric layer is defined to form the opening of the dielectric window, misalignment and misalignment are extremely easy to occur, which in turn makes subsequent The contact area between the plug formed in the opening of the via and the metal wire is reduced, thus increasing its contact resistance 値. This paper is suitable for China National Standards (CNS) A4 size (210X 297 cm) (please read the notes on the back before filling in this f) r ^ 〇48twi7〇05 r 43/0 0 0 at ____ '____B7___ 5 1. Description of the Invention (〆) Figures 1A to IE are schematic cross-sectional views showing the manufacturing process of a conventional non-adhered window. Please refer to Figure 1A, and firstly provide a base structure 100 (base structure 100) having a flat surface. Components are not completely drawn), and a conductive layer is formed on the base structure 100, such as aluminum, aluminum, aluminum-copper alloys formed by sputtering or chemical vapor deposition (CVD). And a conductive layer 102 made of a metal material. Please refer to FIG. 1B, and define the conductive layer 102 using a conventional lithography and etching process. For example, an anisotropic etching method is used to form a conductive line 102a on the base structure 100. 102b, 102c. Referring to FIG. 1C, a dielectric layer 104 is formed on the base structure 100, such as a silicon oxide layer deposited by a chemical vapor deposition (CVD) method, and covers the conductive lines 102a, 102b, and 102c. After that, Plan the dielectric layer 104 Tempering, for example, by chemical mechanical honing (CMP), until the thickness of the dielectric layer 104 on the wire 102b is about the same as the height of the subsequent dielectric window to be formed. Please refer to FIG. 1D, using the traditional Lithography and etching procedures, a dielectric window opening 106 is formed in the dielectric layer 104a, and a part of the surface of the conductive line 102b is exposed. Because the _alignment error occurred when defining the dielectric window opening 106, the dielectric The dielectric window opening 106 in the electrical layer 104a does not completely expose the surface of the wiring 102b, thus forming a subsequent dielectric window opening. When the etching time is too long, the dielectric layer 1 may even be caused. 〇4a erosion, and then reach another conductive region (not shown in the figure) in the base structure 100. In this way, after the subsequent formation of the interlayer window, it will cause abnormal conduction and cause component failure. 4 --------- Meal -------- Order | ----- 0 (I read the notes on the back first and then fill out this page} This paper is suitable for Λ] Chinese national standard (CNS) Λ4 specification (210X 297 mm) A7 437000 s_______ V. Description of the invention () Please refer to Figure 1E for the corrosion In the dielectric window opening 106 formed by the etched dielectric layer 104a, a conformal adhesive / barrier layer 11 is deposited on the surface of the dielectric window opening 106, such as titanium / nitride (Ti / TιN). ), Λ / nitrogen it (Ta / TaN) and other conductive materials' to increase the adhesion between the subsequently deposited conductive layer and other materials. Next, a conductive layer is deposited on the dielectric layer 104a, for example A metal calendar is formed by a chemical vapor deposition (CVD) method, and fills the interstitial window opening 106, and is then electrically coupled to the metal line 102b. After that, the excess conductive layer on the dielectric layer 104a is removed, for example, an etch back method or a chemical mechanical honing method (CMP) is used to remove the excess conductive layer on the dielectric layer 104a. A dielectric JS window plug 1 2 is formed in the dielectric layer 104 a, which is electrically coupled to the metal line 102 b. As mentioned above, because the misalignment occurred when defining the opening of the via, it caused the opening of the via not to be followed. After the subsequent formation of the via, the contact area between the via plug and the lower conductor was reduced. Therefore, the problem that the contact resistance between the via plug of the interlayer window and the lower-layer wire increases is increased. In view of this, the main purpose of the present invention is to provide a method for increasing the contact area of a via window, which can still increase the via window even in the case of a missed via window due to misalignment. The contact product between the plug and the conductor, the contact resistance between the __layer window insert_the conductor_. According to the main object of the present invention, a method is provided, including: providing a base structure 'and forming a conductive line on the base structure. After that, a -layer dielectric layer was formed on the wire, and a dielectric window opening was formed in the dielectric layer, and exposed to 5 paper-size Shizhou Zhongyin National Standards (CNS M4 Specification (210X297)) IIIIII Order « —I tt [. Silk (Read the precautions on the back before filling this page)-" '" 屮 呔 ίτ · 4 (· ^ :: = ί-τ 消 于 合 竹 如 印 来 3 04i < twtV 〇〇5 437 0 0 0 a? B7 V. Description of the invention (10) Part of the wire. Then, remove the wire in the interlayer window opening _ part of the rebel house—the wire 'to form a recessed area. Then, Plugs electrically coupled to the wires are formed in the openings and recessed areas of the interlayer window. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and In conjunction with the drawings, the detailed description is as follows: Brief description of the drawings: Figures 1A to 1E are schematic cross-sectional views showing the manufacturing process of a traditional type without interlayer window; and Figures 2A to 2F Illustrates a manufacturing process for increasing the contact area of an unattached via window according to a preferred embodiment of the present invention Sectional schematic diagram of the diagram. Description of the symbols of the diagram: 100, 200 base structure | 102, 202 conductive layers 102a, 102b, 102c, 202a, 202b, 202c wires 104, 104a, 204, 204a dielectric layers 106, 206 dielectric window opening U 110,210 Adhesive / barrier layer 112,212 Plug 208 Example of recessed area Figures 2A to 2F are cross-sections illustrating a manufacturing process for increasing the contact area of an unbonded window according to a preferred embodiment of the present invention. --------- install ------- order ------- line (please read the precautions on the back before filling this page) This paper size is based on Chinese national standards & lt CNS) A4 specification (2 丨 0 × 297 mm) 3048twt '/ 005 f' 437 Q0 0 A7 ____; _____ B7 V. Description of the invention (Γ) Please refer to Figure 2A, first provide a substrate with a flat surface Structure 200 (elements in the base structure 200 are not fully drawn), and a conductive layer 202 is formed on the base structure 200, such as copper, aluminum, aluminum formed by sputtering or chemical vapor deposition (CVD) A conductive layer 202 made of a metal material such as a copper alloy. Please refer to FIG. 2B for the use of conventional lithography and etching. The conductive layer 202 is defined, for example, an anisotropic etching method is used to form wires 202a, 202b, and 202c on the base structure 200. Referring to FIG. 2C, a dielectric layer 204 is formed on the base structure 200. A silicon oxide layer deposited by chemical vapor deposition (CVD) and covers the wires 202a, 202b, 202c. Thereafter, the dielectric layer 204 is planarized, for example, by a chemical mechanical honing method (CMP), until the thickness of the dielectric layer 204 on the conductive wire 202b is approximately equal to the height of the dielectric window to be formed subsequently. Referring to FIG. 2D, a conventional lithography and etching process, such as anisotropic etching, is used to form a dielectric window opening 206 in the dielectric layer 204a, and a portion of the surface of the conductive wire 202b is exposed. Since an alignment error occurred when defining the via window opening 206, the via window opening 206 in the dielectric layer 204a did not completely expose the surface of the conductive line 202b, and thus a via window opening was not formed. Please refer to FIG. 2E to remove a part of the conductive wire 202b. For example, using wet etching (Wet Etching), select an etchant with a higher etching rate for the conductive wire 202b, and etch away the exposed portion of the interlayer window opening 206. Part of the wire 202b, and a recess is formed at the junction of the wire 202b and the interstitial window opening 206. The paper size is appropriate. ^ Home Standard (CNS) A4 specification (210x297 mm) ------ ---- ¾ --------- Order ------- 0 (Read the words on the back of the song and then fill out this page) ^ 0 481wf 005 43 ^ U 0 0 A7 B7 its V. Description of the invention (") The recessed area 208 further increases the area of the _ line exposed in the opening of the interlayer window 206. In this way, the interlayer window formed later is inserted cold, and the wire 202b The contact area will increase. Referring to FIG. 2F, in the dielectric window opening υ6 in the dielectric layer 204a, the depression area 208 is deposited with a surface of the dielectric window opening 206 and a concave surface 208. Conformal adhesion / barrier layer 210, for example, is a conductive material such as yttrium (Ti / TiN), giant / tantalum nitride (Ta / TaN), etc. The adhesion between the subsequently deposited conductive layer and other materials Next, a conductive layer is deposited on the base structure 200, such as a tungsten metal layer formed by a chemical vapor deposition (CVD) method, and at least fills the via window opening 206 and the recessed region 208, and is then exposed to the wiring 202b. The surface of the recessed area 208 is in contact with each other. Then, 'a portion of the conductive layer on the dielectric layer 204a is removed, for example, using an etch-back method or a chemical mechanical honing method (CMP), until the dielectric layer 204a is exposed and A dielectric window plug 212 electrically coupled to the wire 202b is formed in the dielectric layer 204a. In summary, the present invention is characterized by: 1. It is known to define a dielectric window opening if an alignment error occurs When the opening of the via is not followed, the contact area between the via plug and the lower conductor will be reduced after the via window is formed in the back drawing, thus causing the contact resistance between the via plug and the lower conductor.値 Increasing problems ° The method of the present invention can increase the layer search, contact box, product, that is, after the formation of the misaligned via window opening, remove the lower layer wires exposed by the via window opening 'While opening the U-phase between the wire and the interlayer window A recessed area is formed at the junction. 'This recessed area is formed by injecting conductive materials. (This page) ΐίΜ 部 中 呔 ^ u Τ, ί / J 于 合 竹 itiF ^. This paper is suitable for Sichuan National Standards (CNS) A4 (210x297 mm) 3〇48twf / 005 437 u 〇A7 B7 V. Description of the invention (]) After the plug, you can add the wire and the _. Between _. Contact surface. Product of the wire and the jf window turtle straight, so you can avoid the wire and the interlayer window plug caused by misalignment. The problem between § contact resistance is high. 2. The manufacturing process of the present invention is compatible with the existing manufacturing process, and is very suitable for manufacturers' production arrangements. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (诮 Please read the precautions on the back before filling in this page.),-° This paper size is applicable to the Central National Standard (CNS) Λ4 specification (210X297 mm)