511239 A7511239 A7
五、發明說明（ 本發明是有關於一種半導體元件的製造方法，旦特別 是有關於一種溝渠式導線(Trencll Conductor Line)的製造方 7859twf. doc/009 法。 通常金屬內連線之製作，係利用微影蝕刻製程以先形 成溝渠或接觸窗開口，之後再於溝渠或接觸窗開口中塡入 一金屬並利用化學機械硏磨製程進行平坦化，以形成溝渠 式導線或接觸窗插塞。然而，隨著積體電路之積集度逐漸 的提昇，半導體元件之尺寸亦必須隨之縮減。因此，要精 確的控制溝渠式導線與接觸窗插塞之關鍵尺寸（Critical 以1116首n 與涑度（Depth)是非常不容易的。其中，溝 渠式與介層窗插塞之關鍵尺寸主要係受到微影製程與 蝕刻製程中，關鍵尺寸之限制（CD Limitation)與製程變異 (二；:ar，lon)的影響。而溝渠式導線與介層窗i塞； ίί影^_化學機製程以及蝕刻製程中製程變 #圊弟1圖所示，其繪示爲習知溝渠式導線的結構剖面示 基底=形成溝渠式導線的方法，係先在 在介電層電層1G2之後，利用微影軸刻的方式 入-仝屬成―_，接著於介電層上_渠中塡 渠式導再以化學__法進行平坦化，以形成溝 π二^所形成的溝渠式導線104，其關鍵尺吁 休f制是非常重要的。然而，導線104之關鎌R计 w g又到微影製程與義製程中，關鍵尺寸之限^與各製 (請先閱讀背面之注意事項寫本頁) -線； 經濟部智慧財產局員工消費合作社印則农 本紙張尺度刺中關(CNS)A4祕⑵G 公釐） 511239 7859twf.doc/009 _B7__ 五、發明說明（>") 程變異的影響；而所形成之導線104的深度D會受到蝕刻 製程與化學機械硏磨製程中，各製程變異的影響。因此， 習知形成溝渠式導線的方法，對於控制導線之關鍵尺寸與 深度具有相當的困難度，且對於控制導線之均勻度，意即 對於導線頂部與底部寬度之一致性之控制亦具有相當的困 難度。 此外，習知形成雙重鑲嵌結構的方法，係先利用微影 蝕刻製程以在介電層中形成雙重鑲嵌開口之後，再於雙重 鑲嵌開口中塡入金屬層，並以化學機械硏磨法進行平坦化， 以形成雙重鑲嵌結構。然而，習知形成雙重鑲嵌結構時， 對於其溝渠式導線與介層窗也是有關鍵尺寸與深度不易控 制的問題。此外，倘若欲形成之雙重鑲嵌結構具有較高的 深寬比(Aspect Ratio)時，將更提高了製作的困難度。 因此，本發明的目的就是在提供一種溝渠式導線的製 造方法，以避免以習知方法形成溝渠式導線時，有不易控 制導線之關鍵尺寸與深度之問題。 本發明的另一目的是提供一種雙重鑲嵌結構的製造方 法，以避免以習知方法形成雙重鑲嵌結構時，有不易控制 雙重鑲嵌結構之關鍵尺寸與深度之問題。 本發明的再一目的是提供一種金屬內連線的製造方 法，以使所形成之導線與雙重鑲嵌結構具有較佳之均勻度。 本發明提出一種溝渠式導線的製造方法，其係首先在 所提供之一基底上依序形成一蝕刻終止層、一介電層以及 --硏磨終止層。接著，圖案化硏磨終止層與介電層，以形 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------1 ----Γ! ---* 裝--- (請先閱讀背面之注意事項寫本頁) 舍0. 經濟部智慧財產局員工消費合作社印製 511239 7 8 59twf. doc/009 經濟部智慧財產局員工消費合作社印製 五、發明說明（、） 成一溝渠，暴露出触刻終止層。然後，在硏磨終止層上與 溝渠中形成一共形介電層。之後，去除部分的共形介電層， 以使硏磨終止層與溝渠中之蝕刻終止層暴露出來。然後， 於硏磨終止層上與溝渠中形成一導電層，再平坦化此導電 層，直到硏磨終止層暴露出來，以形成一溝渠式導線。 本發明提出一種溝渠式導線的製造方法，其係首先在 所提供之一基底上依序形成一蝕刻終止層、一介電層以及 一硏磨終止層。接著，圖案化硏磨終止層與介電層以形成 一溝渠，暴露出蝕刻終止層。然後，於硏磨終止層上與溝 渠中形成一導電層，再平坦化此導電層，直到硏磨終止層 暴露出來，以形成一溝渠式導線。 本發明提出一種雙重鑲嵌結構的製造方法，其係首先 在所提供之一基底上形成一第一導電結構與一第二導電結 構。接著在基底上形成一第一介電層，並覆蓋第一導電結 構與第二導電結構。然後依序在第一介電層上形成一蝕刻 終止層、一第二介電層與一硏磨終止層。之後圖案化硏磨 終止層與第二介電層，以形成一第一溝渠與一第二溝渠， 其中第一溝渠與第二溝渠係暴露出蝕刻終止層。接著，圖 案化蝕刻終止層與第一介電層，以形成一第一介層窗開口 與一第二介層窗開口，其中第一介層窗開口係暴露出第一 導電結構，而第二介層窗開口係暴露出基底且其係形成於 第二導電結構之一側邊，而第一溝渠與第一介層窗開口係 組成一第一雙重鑲嵌開口，第二溝渠與第二介層窗開口係 組成一第二雙重鑲嵌開口。之後在硏磨終止層上、第一雙 5 本紙張尺度適用中國國家標準（CNS)A4規格(2〗〇 χ 297公釐） (請先閱讀背面之注音？事項期填寫本頁) 71· rl裝 訂： 511239 經濟部智慧財產局員工消費合作社印製 7859twf.doc/009 A7 五、發明說明（& ) 重鑲嵌開口與第二雙重鑲嵌開口中形成一共形介電層。接 著移除部分共形介電層，以使硏磨終止層、第一雙重鑲嵌 開口中之第一導電結構與第二雙重鑲嵌開口中之基底暴露 出來。之後，在硏磨終止層上與第一雙重鑲嵌開口及第二 雙重鑲嵌開口中形成一導電層，再平坦化此導電層，直到 硏磨終止層暴露出來。 本發明提出一種雙重鑲嵌結構的製造方法，其係首先 在所提供之一基底上形成一第一導電結構與一第二導電結 構。接著在基底上形成一第一介電層，並覆蓋第一導電結 構與第二導電結構。然後依序在第一介電層上形成一蝕刻 終止層、一第二介電層與一硏磨終止層。之後圖案化硏磨 終止層、第二介電層、蝕刻終止層與第一介電層，以形成 一第一介層窗開口與一第二介層窗開口，其中第一介層窗 開口係暴露出第一導電結構，而第二介層窗開口係暴露出 基底且其係形成於第二導電結構之一側邊。接著，圖案化 硏磨終止層與第二介電層，以形成一第一溝渠與一第二溝 渠，其中第一溝渠與第二溝渠係暴露出蝕刻終止層。且第 一溝渠與第一介層窗開口係組成一第一雙重鑲嵌開口，第 二溝渠與第二介層窗開口係組成一第二雙重鑲嵌開口。之 後在硏磨終止層上、第一雙重鑲嵌開口與第二雙重鑲嵌開 口中形成一共形介電層。接著移除部分共形介電層，以使 硏磨終止層、第一雙重鑲嵌開口中之第一導電結構與第二 雙重鑲嵌開口中之基底暴露出來。之後，在硏磨終止層上 與第一雙重鑲嵌開口及第二雙重鑲嵌開口中形成一導電 -----^---l·-----裝—— (請先閱讀背面之注咅？事^11 填寫本頁) •線！ 本紙張尺度適用中國國家標準（CNS)A4規格（2〗0 X 297公釐） 511239 7859twf.doc/009 _B7__ 五、發明說明（^ ) 層，再平坦化此導電層，直到硏磨終止層暴露出來' 本發明利用一蝕刻終止層與一硏磨終止層，可精確的 控制所形成之溝渠式導線之深度與雙重鑲嵌結構中之溝渠 的深度。 本發明在溝渠與雙重鑲嵌開口中形成一共形介電層， 利用此共形介電層之厚度，可精確的控制所形成之溝渠式 導線與雙重鑲嵌結構之關鍵尺寸。 本發明所形成之溝渠式導線與雙重鑲嵌結構，較習知 所形成之導線與雙重鑲嵌結構具有較佳之均勻度。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖爲習知溝渠式導線的結構剖面示意圖； 第2A圖至第2E圖是依照本發明第一實施例之溝渠式 導線的製造流程剖面示意圖； 第3圖爲依照本發明第一較佳實施例之另一種形成溝 渠式導線的剖面示意圖；以及 第4A圖至第4E圖是依照本發明第二實施例之雙重鑲 嵌結構的製造流程剖面示意圖。 圖式之標示說明= 100、2Θ0、300 ··基底 102 ' 202、208、306、307 :介電層 104、204、302、304 ·•導電結構 7 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項砰填寫本頁) S· rl裝 經濟部智慧財產局員工消費合作社印製 511239 經濟部智慧財產局員工消費合作社印製 7859twf·d〇c/009 A7 一— ------ B7_____五、發明說明（V?) 206、310 :蝕刻終止層 210、308 :硏磨終止層 212、212a :溝渠 214、214a、318、318a、318b ··共形介電層 216、211 :溝渠式導線 314、316' 314a、316a:雙重鑲嵌開口 320、322 :雙重鑲嵌結構 D :深度 W:關鍵尺寸 第一實施例 桌2A Η至弟2E圖，其繪示爲依照本發明第一佳實施 例之溝渠式導線的製造方法。 請參照第2Α圖，首先提供一基底200，其中基底2〇〇 上已形成有一導電結構202，此導電結構202例如爲一聞 極結構。之後在基底200上形成一第一介電層204，並覆 蓋導電結構202，第一介電層2〇4之材質例如爲氧化矽。 接著，在第一介電層204上形成一蝕刻終止層206，其中 蝕刻終止層206之材質例如爲氮化矽，其厚度例如爲2〇埃 至50埃。之後在蝕刻終止層206上形成一第二介電層208， 其中第二介電層208之材質例如爲氧化矽，其厚度係依照 導線之需求而定，例如爲1000埃至3000埃。然後，在第 二介電層208上形成一硏磨終止層210,其中硏磨終止層210 之材質例如爲氮化矽，其厚度例如爲20埃至50埃。 之後，請參照第2Β圖，圖案化硏磨終止層210與第二 8 (請先閲讀背面之注咅？事填寫本頁) -裝 訂： •f- 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 511239 7859twf. doc/〇〇9 A7 _---—---- B7 五、發明說明（c\ ) 介電層208，以形成一溝渠212，暴露出蝕刻終止層206。 由於触刻終止層206之蝕刻速率低於第二介電層208之蝕 刻速率’因此圖案化硏磨終止層210與第二介電層208之 蝕刻步驟將自動停止於蝕刻終止層206。如此一來，所形 成之溝渠212的深度便得以精確的控制。 然後，請參照第2C圖，在硏磨終止層210與溝渠212 中形成一共形介電層214,其材質例如爲氮化矽或氮氧化 石夕。其中所形成之共形介電層214之厚度係依照所形成之 溝渠212之寬度而調整，例如當形成溝渠212之寬度較寬， 則可形成厚度較厚之共形介電層214，以使溝渠212a之寬 度符合關鍵尺寸之要求；當形成溝渠212之寬度較窄，則 可形成厚度較薄之共形介電層214，以使溝渠212a之寬度 符合關鍵尺寸之要求。 接著，請參照第2D圖，移除部分的共形介電層214， 以使硏磨終止層210與溝渠212a中之蝕刻終止層206暴露 出來，而僅保留溝渠212a側壁的共形介電層214a。其中 移除部分的共形介電層214之方法例如爲一乾式蝕刻製 程。 之後，請參照第2E圖，在溝渠212a中塡入一導電層， 以形成一溝渠式導線216。其中導電層之材質例如金屬鎢。 而形成溝渠式導線216之方法例如爲在硏磨終止層210上 與溝渠212a中形成一導電層，之後以化學機械硏磨製程移 除部分的導電層，直到硏磨終止層210暴露出來。由於硏 磨終止層210之硏磨速率低於導電層之硏磨速率，因此去 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐）V. Description of the invention (The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a trecll conductor (Trencll Conductor Line) 7859twf. Doc / 009 method. Generally, the production of metal interconnects, The lithographic etching process is used to form a trench or contact window opening, and then a metal is inserted into the trench or contact window opening and planarized by a chemical mechanical honing process to form a trench-type wire or contact window plug. However, As the integration degree of integrated circuits gradually increases, the size of semiconductor components must also be reduced accordingly. Therefore, the critical dimensions of trench wires and contact window plugs must be accurately controlled (Critical uses 1116 n and 涑 degrees). (Depth) is very difficult. Among them, the key dimensions of trench and via plugs are mainly subject to CD Limitation and process variation in lithography and etching processes (II;: ar, lon). And trench-type wires and interlayer window plugs are shown in Figure 化学 _Chemical mechanism process and etching process process change # 变 弟 1 Figure, which is shown as a habit The structural cross-section of the trench-type conductor shows the base = the method of forming the trench-type conductor. After the dielectric layer 1G2, the lithography axis is used to enter-all belong to -_, and then on the dielectric layer_ The channel guide in the channel is then planarized by the chemical method to form the channel guide 104 formed by the channel π. The key rule of the channel 104 is very important. However, the barrier 104 of the guide 104 Calculate wg again in the lithography process and the free-form process, the key dimensions are limited ^ and each system (please read the precautions on the back to write this page)-line; The secret of Zhongguan (CNS) A4 (G mm) 511239 7859twf.doc / 009 _B7__ V. The effect of the > > process variation; and the depth D of the formed wire 104 will be affected by the etching process and chemical machinery. The impact of various process variations during the grinding process. Therefore, it is quite difficult to control the critical size and depth of the conductor, and to control the uniformity of the conductor, that is, the top and bottom of the conductor. Consistency of width Control is also quite difficult. In addition, the conventional method for forming a dual damascene structure is to use a lithographic etching process to form a dual damascene opening in a dielectric layer, and then insert a metal layer into the dual damascene opening, and Chemical mechanical honing is used to planarize to form a dual damascene structure. However, when it is known to form a dual damascene structure, it is also difficult to control the size and depth of its trench-type wires and interlayer windows. In addition, if you want to When the formed dual mosaic structure has a high aspect ratio, it will increase the difficulty of production. Therefore, an object of the present invention is to provide a method for manufacturing a trench-type conductor, so as to avoid the problem that it is difficult to control the critical size and depth of the conductor when the trench-type conductor is formed by a conventional method. Another object of the present invention is to provide a method for manufacturing a dual mosaic structure, so as to avoid the problem that it is difficult to control the critical size and depth of the dual mosaic structure when the dual mosaic structure is formed by the conventional method. Another object of the present invention is to provide a method for manufacturing a metal interconnect, so that the formed wires and the dual damascene structure have better uniformity. The present invention provides a method for manufacturing a trench-type wire. First, an etching stop layer, a dielectric layer, and a honing stop layer are sequentially formed on a provided substrate. Next, pattern the honing stop layer and the dielectric layer, and apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) to the paper size ------ 1 ---- Γ! --- * Packing --- (Please read the notes on the back to write this page). 0. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511239 7 8 59twf. Doc / 009 Printed by the Employees’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs DESCRIPTION OF THE INVENTION (,) forms a trench, exposing the contact termination layer. A conformal dielectric layer is then formed on the honing stop layer and in the trench. After that, a portion of the conformal dielectric layer is removed to expose the honing stop layer and the etch stop layer in the trench. Then, a conductive layer is formed on the honing stop layer and in the trench, and the conductive layer is planarized until the honing stop layer is exposed to form a trench-type wire. The invention provides a method for manufacturing a trench-type wire. First, an etching stop layer, a dielectric layer, and a honing stop layer are sequentially formed on a provided substrate. Next, the honing stop layer and the dielectric layer are patterned to form a trench, and the etch stop layer is exposed. Then, a conductive layer is formed on the honing stop layer and in the trench, and the conductive layer is planarized until the honing stop layer is exposed to form a trench-type wire. The present invention provides a method for manufacturing a dual damascene structure. First, a first conductive structure and a second conductive structure are formed on a provided substrate. Next, a first dielectric layer is formed on the substrate, and the first conductive structure and the second conductive structure are covered. An etching stop layer, a second dielectric layer, and a honing stop layer are sequentially formed on the first dielectric layer. Thereafter, the honing stop layer and the second dielectric layer are patterned to form a first trench and a second trench, wherein the first trench and the second trench expose an etching stop layer. Next, the etch stop layer and the first dielectric layer are patterned to form a first dielectric window opening and a second dielectric window opening, wherein the first dielectric window opening exposes the first conductive structure, and the second The opening of the interlayer window exposes the substrate and is formed on one side of the second conductive structure, and the first trench and the first interlayer window opening form a first double mosaic opening, and the second trench and the second interlayer The window opening constitutes a second double inlay opening. After that, on the honing termination layer, the first double 5 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (2〗 〇χ297 mm) (Please read the phonetic on the back? Please fill in this page during the matter period) 71 · rl Binding: 511239 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7859twf.doc / 009 A7 V. Description of the Invention (&) A conformal dielectric layer is formed in the re-mosaic opening and the second double-mosaic opening. Then, a part of the conformal dielectric layer is removed to expose the honing stop layer, the first conductive structure in the first double damascene opening and the substrate in the second double damascene opening. After that, a conductive layer is formed on the honing stop layer and the first double damascene opening and the second double damascene opening, and then the conductive layer is planarized until the honing stop layer is exposed. The present invention provides a method for manufacturing a dual damascene structure. First, a first conductive structure and a second conductive structure are formed on a provided substrate. Next, a first dielectric layer is formed on the substrate, and the first conductive structure and the second conductive structure are covered. An etching stop layer, a second dielectric layer, and a honing stop layer are sequentially formed on the first dielectric layer. Thereafter, the honing stop layer, the second dielectric layer, the etching stop layer and the first dielectric layer are patterned to form a first dielectric window opening and a second dielectric window opening. The first dielectric window opening is The first conductive structure is exposed, and the second interlayer window opening exposes the substrate and is formed on one side of the second conductive structure. Then, the honing stop layer and the second dielectric layer are patterned to form a first trench and a second trench, wherein the first trench and the second trench expose an etch stop layer. And the first trench and the first interstitial window opening form a first double mosaic opening, and the second trench and the second interstitial window opening form a second double mosaic opening. A conformal dielectric layer is then formed on the honing termination layer in the first double damascene opening and the second double damascene opening. A portion of the conformal dielectric layer is then removed to expose the honing stop layer, the first conductive structure in the first double damascene opening, and the substrate in the second double damascene opening. After that, a conductive ----- ^ --- l · ----- installation is formed on the honing stop layer with the first double inlay opening and the second double inlay opening-- (Please read the note on the back first咅？ 事 ^ 11 Fill out this page) • Online! This paper size applies the Chinese National Standard (CNS) A4 specification (2〗 0 X 297 mm) 511239 7859twf.doc / 009 _B7__ 5. Description of the invention (^) layer, and then flatten the conductive layer until the honing stop layer is exposed Out 'The present invention utilizes an etch stop layer and a honing stop layer to accurately control the depth of the trench-type wire formed and the depth of the trench in the dual damascene structure. The present invention forms a conformal dielectric layer in a trench and a dual mosaic opening. By using the thickness of the conformal dielectric layer, the key dimensions of the formed trench-type wire and the dual mosaic structure can be accurately controlled. The trench-type wire and the double-inlaid structure formed by the present invention have better uniformity than the conventionally-formed wire and the double-inlaid structure. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 FIG. 2A to FIG. 2E are cross-sectional schematic diagrams of a manufacturing process of a trench-type conductor according to the first embodiment of the present invention; and FIG. 3 is a schematic diagram of the first preferred embodiment of the present invention. Another schematic cross-sectional view of forming a trench-type wire; and FIGS. 4A to 4E are schematic cross-sectional views illustrating a manufacturing process of a dual damascene structure according to a second embodiment of the present invention. Description of the drawing labeling = 100, 2Θ0, 300 ·· Substrate 102 '202, 208, 306, 307: Dielectric layer 104, 204, 302, 304 · Conductive structure 7 This paper size applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) (Please read the notes on the back first and fill out this page) S · rl Printed by the Employees 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511239 Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7859twf · d〇 c / 009 A7 I------- B7_____ V. Description of the invention (V?) 206, 310: Etching stop layer 210, 308: Honing stop layer 212, 212a: trench 214, 214a, 318, 318a, 318b · conformal dielectric layers 216, 211: trench-type conductors 314, 316 ', 314a, 316a: double damascene openings 320, 322: double damascene structure D: depth W: key dimensions First embodiment table 2A Η to 2E FIG. Shows a method for manufacturing a trench-type wire according to the first preferred embodiment of the present invention. Referring to FIG. 2A, a substrate 200 is first provided. A conductive structure 202 has been formed on the substrate 2000. The conductive structure 202 is, for example, an electrode structure. A first dielectric layer 204 is then formed on the substrate 200 and covers the conductive structure 202. The material of the first dielectric layer 204 is, for example, silicon oxide. Next, an etch stop layer 206 is formed on the first dielectric layer 204. The material of the etch stop layer 206 is, for example, silicon nitride, and its thickness is, for example, 20 angstroms to 50 angstroms. Then, a second dielectric layer 208 is formed on the etch stop layer 206. The material of the second dielectric layer 208 is, for example, silicon oxide, and its thickness is determined according to the requirements of the wires, for example, 1000 angstroms to 3000 angstroms. Then, a honing stop layer 210 is formed on the second dielectric layer 208. The material of the honing stop layer 210 is, for example, silicon nitride, and its thickness is, for example, 20 angstroms to 50 angstroms. After that, please refer to Figure 2B, patterning the honing termination layer 210 and the second 8 (Please read the note on the back first? Fill in this page first)-Binding: • f- This paper size applies Chinese National Standard (CNS) A4 Specifications (210x297 mm) 511239 7859twf. Doc / 〇〇9 A7 _-------- B7 V. Description of the Invention (c \) Dielectric layer 208 to form a trench 212, and the etch stop layer 206 is exposed . Since the etching rate of the etching stop layer 206 is lower than the etching rate of the second dielectric layer 208, the etching steps of the patterned honing stop layer 210 and the second dielectric layer 208 will automatically stop at the etching stop layer 206. In this way, the depth of the formed trench 212 can be accurately controlled. Then, referring to FIG. 2C, a conformal dielectric layer 214 is formed in the honing termination layer 210 and the trench 212, and the material is, for example, silicon nitride or oxynitride. The thickness of the conformal dielectric layer 214 formed therein is adjusted according to the width of the trench 212 formed. For example, when the width of the trench 212 is formed, a thicker conformal dielectric layer 214 can be formed so that The width of the trench 212a meets the requirements of critical dimensions; when the width of the trench 212 is formed to be narrower, a thinner conformal dielectric layer 214 can be formed so that the width of the trench 212a meets the requirements of critical dimensions. Next, referring to FIG. 2D, a part of the conformal dielectric layer 214 is removed, so that the honing stop layer 210 and the etch stop layer 206 in the trench 212a are exposed, leaving only the conformal dielectric layer on the sidewall of the trench 212a. 214a. A method in which a portion of the conformal dielectric layer 214 is removed is, for example, a dry etching process. After that, referring to FIG. 2E, a conductive layer is inserted into the trench 212 a to form a trench-type wire 216. The material of the conductive layer is, for example, metal tungsten. The method of forming the trench-type wire 216 is, for example, forming a conductive layer on the honing termination layer 210 and the trench 212a, and then removing a part of the conductive layer by a chemical mechanical honing process until the honing termination layer 210 is exposed. Since the honing rate of the honing stop layer 210 is lower than the honing rate of the conductive layer, the paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 meals)
(請先閱讀背面之注音？事S 裝--- ^填寫本頁) ->-0· 經濟部智慧財產局員工消費合作社印製 511239 7859twf. doc/009 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（¾ ) 除溝渠212a以外的導電層之化學機械硏磨製程，會自動停 止在硏磨終止層21 0。如此一來，便可精確的控制所形成 之導線216之厚度。 第3圖所示，其繪不爲依照本發明第一較佳實施例之 另一種形成溝渠式導線的剖面示意圖。 本實施例亦可在第2B圖中形成溝渠212之後，直接在 溝渠212中塡入導電層（如第3圖所示），以形成溝渠式導 線211。其中導電層之材質例如爲金屬鎢，形成溝渠式導 線211之方法例如爲先在硏磨終止層21〇上與溝渠212中 形成一導電層，再以化學機械硏磨製程去除部分導電層， 直到硏磨終止層210暴露出來。 本實施例利用蝕刻終止層206以精確的控制所形成的 溝渠212之深度，再利用硏磨終止層210與鈾刻終止層206 之配合，以精確的掌握所形成的導線211之深度。此外， 本實施例可先形成寬度較大的溝渠212,再利用共形介電 層214來調整溝渠之寬度，以符合關鍵尺寸之要求，如此 一來，可使所形成之溝渠式導線216具有較佳之均勻度， 意即所形成之溝渠式導線216之頂部與底部具有較一致的 寬度。 第二實施例 第4A圖至第4E圖所示，其繪示爲依照本發明第二實 施例之雙重鑲嵌結構的製造流程剖面示意圖° 請參照第4A圖，首先在所提供之一基底300上形成 第一導電結構302與第二導電結構304,其中導電結構3〇2、 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）(Please read the phonetic note on the back? Matt S --- ^ Fill in this page)-> -0 · Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511239 7859twf. Doc / 009 A7 B7 Employee Consumption of the Intellectual Property Bureau of Ministry of Economic Affairs Printed by the cooperative V. Description of the invention (¾) The chemical mechanical honing process of the conductive layer other than the trench 212a will automatically stop at the honing termination layer 210. In this way, the thickness of the formed wire 216 can be precisely controlled. As shown in FIG. 3, it is not a schematic cross-sectional view of forming another trench-type conductive wire according to the first preferred embodiment of the present invention. In this embodiment, after the trench 212 is formed in FIG. 2B, a conductive layer (as shown in FIG. 3) is directly inserted into the trench 212 to form a trench-type wiring 211. The material of the conductive layer is, for example, metal tungsten, and the method of forming the trench-type wire 211 is, for example, first forming a conductive layer on the honing stop layer 21 and the trench 212, and then removing a part of the conductive layer by a chemical mechanical honing process until The honing termination layer 210 is exposed. This embodiment uses the etching stop layer 206 to precisely control the depth of the trench 212 formed, and then uses the combination of the honing stop layer 210 and the uranium etching stop layer 206 to accurately grasp the depth of the formed wire 211. In addition, in this embodiment, a trench 212 having a larger width can be formed first, and then the conformal dielectric layer 214 can be used to adjust the width of the trench to meet the requirements of key dimensions. In this way, the formed trench type conductor 216 can have The better uniformity means that the top and bottom of the formed trench-shaped conducting wire 216 have a more consistent width. The second embodiment is shown in FIGS. 4A to 4E, which are schematic cross-sectional views showing the manufacturing process of a dual damascene structure according to the second embodiment of the present invention. Please refer to FIG. 4A, first on a provided substrate 300 Form a first conductive structure 302 and a second conductive structure 304, in which the conductive structure 302, 10 paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm)
(請先閱讀背面之注意事X 裝--- f填寫本頁) 1^7· 川239 7859twf.doc/009 幻 _B7 _ 五、發明說明（' ) 304例如爲閘極結構。之後在基底300上形成一介電層306， 並覆蓋導電結構302、304。接著，依序在介電層306上形 成一蝕刻終止層310、一介電層307與一硏磨終止層308。 其中介電層306、307之材質例如爲氧化矽。蝕刻終止層310 之材質例如爲氮化矽，其厚度例如爲20埃至50埃。硏磨 終止層308之材質例如爲氮化矽，其厚度例如爲20埃至50 埃。 之後，請參照第4B圖，在介電層306、蝕刻終止層310、 介電層307與一硏磨終止層308中形成一第一雙重鑲嵌開 口 314與一第二雙重鑲嵌開口 316。其中第一雙重鑲嵌開 口 314係暴露出第一導電結構3〇2，第二雙重鑲嵌開口 316 係暴露出基底300,且其係形成於第二導電結構304之一 側邊。 形成此第一雙重鑲嵌開口 314與一第二雙重鑲嵌開口 316之方法，例如先圖案化硏磨終止層308與介電層307， 以形成第一溝渠與第二溝渠，暴露出蝕刻終止層310。之 後再圖案化蝕刻終止層310與介電層306，以形成第一介 層窗開口與第二介層窗開口，其中第一介層窗開口與第一 溝渠係組成第一雙重鑲嵌開口 314,第二介層窗開口與第 二溝渠係組成第二雙重鑲嵌開口 316。 另一種形成第一雙重鑲嵌開口 314與一第二雙重鑲嵌 開口 316之方法，係首先圖案化硏磨終止層308、介電層 3〇7、蝕刻終止層310與介電層306，以形成第一介層窗開 口與第二介層窗開口。之後再圖案化硏磨終止層3〇8與介 本紙張歧翻中關家鮮（CNS)A4規格（210 (請先閱讀背面之注意事^ -1 - I I f填寫本頁) 經濟部智慧財產局員工消費合作社印製 297公釐） 511239 7859twf.doc/009 _B7_ 五、發明說明) 電層307，以形成第一溝渠與第二溝渠，暴露出蝕刻終止 層310。其中第一介層窗開口與第一溝渠係組成第一雙重 鑲嵌開口 314,第二介層窗開口與第二溝渠係組成第二雙 重鑲嵌開口 316。 然後，請參照第4C圖，在硏磨終止層308上與第一雙 重鑲嵌開口 314及第二雙重鑲嵌開口 316中形成一共形介 電層3 1 8，其材質例如爲氮化矽或氮氧化矽。其中所形成 之共形介電層318之厚度係依照所形成之第一雙重鑲嵌開 口 314與第二雙重鑲嵌開口 316之寬度而調整，例如當形 成第一雙重鑲嵌開口 314與第二雙重鑲嵌開口 316之寬度 較寬時，則可形成厚度較厚之共形介電層318，以使第一 雙重鑲嵌開口 314a與第二雙重鑲嵌開口 316a之寬度符合 關鍵尺寸之要求；當形成第一雙重鑲嵌開口 314與第二雙 重鑲嵌開口 316之寬度較窄時，則可形成厚度較薄之共形 介電層318，以使第一雙重鑲嵌開口 314a與第二雙重鑲嵌 開口 316a之寬度符合關鍵尺寸之要求。 接著，請參照第4D圖，移除部分的共形介電層318， 以使硏磨終止層308與第一雙重鑲嵌開口 314a中之第一導 電結構302及第二雙重鑲嵌開口 316a中之基底300暴露出 來，而僅保留第一雙重鑲嵌開口 314a及第二雙重鑲嵌開口 316a側壁的共形介電層318a、318b。其中移除部分的共形 介電層318之方法例如爲一乾式蝕刻製程。 之後，請參照第4E圖，在第一雙重鑲嵌開口 314a與 第二雙重鑲嵌開口 316a中塡入一導電層，以分別形成第一 12 本紙張尺度適用中國國家標準（CNS)A4規格（2】〇χ 297公釐）(Please read the precautions on the back of the X device --- f to fill out this page) 1 ^ 7 · 川 239 7859twf.doc / 009 Magic _B7 _ V. Description of the invention (') 304 is a gate structure, for example. A dielectric layer 306 is then formed on the substrate 300 and covers the conductive structures 302 and 304. Next, an etch stop layer 310, a dielectric layer 307, and a honing stop layer 308 are sequentially formed on the dielectric layer 306. The material of the dielectric layers 306 and 307 is, for example, silicon oxide. The material of the etch stop layer 310 is, for example, silicon nitride, and its thickness is, for example, 20 angstroms to 50 angstroms. The material of the honing stop layer 308 is, for example, silicon nitride, and its thickness is, for example, 20 angstroms to 50 angstroms. After that, referring to FIG. 4B, a first double damascene opening 314 and a second double damascene opening 316 are formed in the dielectric layer 306, the etch stop layer 310, the dielectric layer 307, and a honing stop layer 308. The first double damascene opening 314 exposes the first conductive structure 302, and the second double damascene opening 316 exposes the substrate 300, and it is formed on one side of the second conductive structure 304. The method of forming the first double damascene opening 314 and a second double damascene opening 316, such as patterning the honing stop layer 308 and the dielectric layer 307 first, to form a first trench and a second trench, exposing the etch stop layer 310. . Thereafter, the etch stop layer 310 and the dielectric layer 306 are patterned to form a first dielectric window opening and a second dielectric window opening, wherein the first dielectric window opening and the first trench system constitute a first double mosaic opening 314, The second interlayer window opening and the second trench system form a second double mosaic opening 316. Another method of forming the first double damascene opening 314 and a second double damascene opening 316 is to first pattern the honing stop layer 308, the dielectric layer 307, the etch stop layer 310, and the dielectric layer 306 to form a first A via window opening and a second via window opening. Then pattern the honing termination layer 308 and the paper, and turn it over to Zhongguanxian (CNS) A4 specification (210 (please read the notes on the back first -1-II f to fill in this page) Intellectual Property of the Ministry of Economic Affairs 297 mm printed by the Bureau ’s Consumer Cooperative) 511239 7859twf.doc / 009 _B7_ V. Description of the invention) Electrical layer 307 to form a first trench and a second trench, exposing the etch stop layer 310. The first via window opening and the first trench system form a first double inlay opening 314, and the second via window opening and the second trench system form a second double inlay opening 316. Then, referring to FIG. 4C, a conformal dielectric layer 3 1 8 is formed on the honing termination layer 308 with the first double damascene opening 314 and the second double damascene opening 316. The material is, for example, silicon nitride or oxynitride. Silicon. The thickness of the conformal dielectric layer 318 formed therein is adjusted according to the width of the first double mosaic opening 314 and the second double mosaic opening 316 formed, for example, when the first double mosaic opening 314 and the second double mosaic opening are formed. When the width of 316 is wider, a thicker conformal dielectric layer 318 can be formed so that the widths of the first double damascene opening 314a and the second double damascene opening 316a meet the requirements of key dimensions; when the first double damascene is formed When the widths of the openings 314 and the second double damascene opening 316 are narrower, a thinner conformal dielectric layer 318 can be formed, so that the widths of the first double damascene opening 314a and the second double damascene opening 316a meet the critical dimensions. Claim. Next, referring to FIG. 4D, a part of the conformal dielectric layer 318 is removed, so that the honing stop layer 308 and the first conductive structure 302 in the first double damascene opening 314a and the substrate in the second double damascene opening 316a. 300 is exposed, leaving only the conformal dielectric layers 318a, 318b of the sidewalls of the first double damascene opening 314a and the second double damascene opening 316a. The method of removing a portion of the conformal dielectric layer 318 is, for example, a dry etching process. Then, referring to FIG. 4E, a conductive layer is inserted into the first double-inlaid opening 314a and the second double-inlaid opening 316a to form the first 12 paper standards, which are applicable to China National Standard (CNS) A4 specifications (2) 〇χ 297 mm)
(請先閱讀背面之注意事S 丨裝—— Ρ寫本頁) ->-0· 經濟部智慧財產局員工消費合作社印製 511239 7859twf.doc/009 A7 _B7 五、發明說明（Λ ) 雙重鑲肷結構32〇與第一雙重鑲嵌結構η2。其中導電層 之材質例如金屬鎢。而形成第一雙重鎮嵌結構no與第二 雙重鑲嵌結構322之方法例如爲在硏磨終止層谓上與第 -雙重鑲嵌開□ 314a與第3顏鑲嵌開日遍中形成一 導電層，之後以化學機械硏磨製程移除部分導電層，直到 硏磨終止層308暴露出來，以形成一第一雙重鑲嵌結構32〇 與一第二雙重鑲嵌結構322。本實施例之形成雙重鑲嵌結 構的方法中由於硏磨終止層308之硏磨速率低於導電層之 硏磨速率，因此去除部分導電層之化學機械硏磨製程，會 自動停止在硏磨終止層308。由於硏磨終止層308與蝕刻 終止層310之作用’因此可精確的控制所形成之第一雙重 鑲嵌結構320與一第二雙重鑲嵌結構322中溝渠式導線之 深度。 本實施例在第二雙重鑲嵌結構322之側壁形成有共形 介電層318b，此共形介電層318b可用來防止第二雙重鑲 嵌結構322與第二導電結構304之間產生短路之情形。 綜合以上所述，本發明具有下列優點： 1. 本發明利用一蝕刻終止層與一硏磨終止層，以精確 的控制所形成之溝渠式導線之深度與雙重鑲嵌結構中溝渠 式導電之深度。 2. 本發明在開口中形成一共形介電層，利用此共形介 電層之厚度，以精確的控制所形成之溝渠式導線與雙重鑲 嵌結構之關鍵尺寸。 3. 本發明所形成之溝渠式導線與雙重鑲嵌結構，較習 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） (請先閱讀背面之注意事項5(填寫本頁) F1裝 經濟部智慧財產局員工消費合作社印製 511239 7 8 5 9twf. doc/009 _B7__ 五、發明說明（0^) 知所形成之導線與雙重鑲嵌結構具有較佳之均勻度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事填寫本頁) 裝 線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐）(Please read the note S on the back first-write this page)-> -0 · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511239 7859twf.doc / 009 A7 _B7 V. Description of the Invention (Λ) Double The inlay structure 32 and the first double inlay structure η2. The material of the conductive layer is, for example, metal tungsten. The method of forming the first double-embedded structure no and the second double-embedded structure 322 is, for example, to form a conductive layer on the honing termination layer with the first-double-embedded structure 314a and the third-color embedded structure, and thereafter A part of the conductive layer is removed by a chemical mechanical honing process until the honing termination layer 308 is exposed to form a first double damascene structure 32 and a second double damascene structure 322. In the method of forming a dual damascene structure in this embodiment, since the honing rate of the honing stop layer 308 is lower than the honing rate of the conductive layer, the chemical mechanical honing process of removing a part of the conductive layer will automatically stop at the honing stop layer. 308. Due to the function of the honing stop layer 308 and the etch stop layer 310, the depths of the trench-type wires in the first double damascene structure 320 and the second double damascene structure 322 formed can be accurately controlled. In this embodiment, a conformal dielectric layer 318b is formed on the side wall of the second dual damascene structure 322. This conformal dielectric layer 318b can be used to prevent a short circuit between the second dual damascene structure 322 and the second conductive structure 304. To sum up, the present invention has the following advantages: 1. The present invention uses an etch stop layer and a honing stop layer to precisely control the depth of the trench-type wire formed and the depth of trench-type conduction in the dual damascene structure. 2. The present invention forms a conformal dielectric layer in the opening, and uses the thickness of the conformal dielectric layer to precisely control the critical dimensions of the formed trench-type wires and the dual-embedded structure. 3. The trench-type wire and double-inlay structure formed by the present invention are more suitable for Chinese National Standards (CNS) A4 (210 x 297 mm) than the paper size (please read the note 5 on the back first (fill in this page) F1 is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511239 7 8 5 9twf. Doc / 009 _B7__ V. Description of the Invention (0 ^) It is known that the formed wire and the double mosaic structure have better uniformity. Although the present invention has been The preferred embodiment is disclosed as above, but it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be regarded as The attached patent application scope is subject to the definition. (Please read the notes on the back and fill in this page first.) Assembly line · Printed by the Intellectual Property Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification ( 210 x 297 mm)