1223409 玖、發明說明： 【發明所屬之技術領域】 本I明係有關於一種動態隨機存取記憶體(DRAM)之製造方法，更明 確而言，係有關於一種DRAM位元線與位元線接觸結構的形成方法。 【先前技術】 半，體裝置的製程中，導線以及導線接觸點的形成係大量使用。在 _製程中，係在單元結構中形成接_ ’填人複晶材料形成插塞並 加以化學機械研磨以構成位元線接觸點。此階段之結構大致與圖以所 而目前製程中，所構成的位元線接觸點之接觸面積較大。鲁 現耆Μ日益緊密化，位元線之間的間距縮小。參見圖i，當位元線 3點12之接觸區域較大時，由於位元線n對位元線接觸點12之覆 =生不，，如位元線财涵，則容綠生不麵橋接現象而造成異 吊位兀線纟構。因此，需要有賴克服此_題的方法。 【發明内容】 . 本毛明之目的係在於提供—齡元線接騎構形成方法，所形成的 位元線接觸點係具有較小的接觸區域。 另目的係在於提供一種位元線及位元線接觸結構形成 方法，其可提升位元線龍元線獅狀妓性，_紐生位元線 之間的不當短路。 根據本發明之-方面，—齡元職騎_成方法，轉觸窗已 填入複晶插塞之半成品結構為基礎，該方法包括步驟有移除部分氧化 層，以使該插塞突出；使該插塞之突出部分之暴露部分氧化；以及移 除該插塞之氧化部分。 J:\menu\pending-92\92208.doc 5 以】之另L —種位元線與位元線接觸結構形成方法， ’、口p刀乳化層，以使該插塞突出；使該插之 之氧化部分；形成第—介電層於整體&之 露出；形成第二介電層於包含插塞上表面之第-介雷 第二介電層上塗覆光阻劑，加以曝光、顯影、_， ^、疋圖案之溝渠，以及於該溝渠填入金屬，以形成位元線。 【實施方式】 圖2a係顯示一動態隨機存取記憶體(麵)單元中間產品之部分結 構截面圖，其中參考號碼2G表示基f，22為複晶插塞，㈣為氧化 層於棚中，所顯示為複晶插塞22係填入接觸窗中之結構。複晶插 塞22之上表面可藉由例如為化學機械研雜MP)加以平坦化處理。 芩見圖此，先藉由濕钱刻或是乾餘刻移除部分氧化層24,以使複晶 插塞22突出。 然後，使複晶插塞22之突出部分氧化而形成氧化部分23，如圖2c 所示。此氧化處理可_任何適#的方式實施。 接著，利用像是濕姓刻法等移除方式去除複晶插塞烈之氧化部分 23 ’如圖2d所示。 參見圖2e，在移除複晶插塞22之氧化部分烈之後，係在整個結構 上沉積一第—介電層26 妓任何適當的簡。複晶織22 f絲出。贿結構之表面 可It由CMP加以平坦化處理。今繁 ^ 4第一介電層26係可作為平坦化處理之 停止層。 J ：\menu\pending-92\92208 .doc 6 ,:、在第"電層26之上，再沉積一層第二介電層28，如圖 2f所示。該第二介電層28可為氧化層。-般而言，第二介電層沈之 才料係/、帛”電層26不同。當材料不同時，該第一介電層26係可 作為後讀辑製作步驟巾之侧停止層。但第二介電層沈亦可採用 與弟-介電層相同的材料，本案之方法仍可適用。 之後則進行—般位元線製作程序，在第二介電層26上形成光阻劑 作為光罩，經過曝光、顯影、钱刻等步驟之後，在第二介電層％形成 預定圖案之溝渠，然後在溝渠中填人金屬，構成位元線，最後移除光 阻d如月所述第一介電層26可在形成溝渠時，作為侧停止層。圖 、員τ祕光賴之後的結構，此目係由位元線部份喊面視之。 於顧中，參考號碼29即表示構成位元線之部分。位元線部分29之 材料可為鋼、鎢或任何適合的材料。 。、圖所7F本㈣之方摘形成的結構中，複晶插塞&之上表面 品或相車乂於白用技術為小，亦即，位元線接觸點的臨界尺寸變小。如 回斤丁 Φ於位70線接觸點的上表面面積變小，提昇位元線對位元 2接觸點之覆蓋性，使位元線間之_有較大餘裕，即使位元線猶有 ’幫曲，仍不致發生短路。 技蓺去W ? 並非麟關本發明。熟知此項 實4- 1 不1^離本發明之精神與範的各種修正、變更均可 貝仃。本發明之保護範圍係如所附之中請專利範圍所界定。 【圖式簡單說明】 J:\menu\pending-92\92208.doc 7 1223409 圖1係顯示習用技術中dram位元線對位元線接觸點之覆蓋性示 意圖； 圖％至2g係顯示本發明之方法的各個步驟之截面圖；及 圖3係顯示根據本發明之方法形成之位元線對位元線接觸點之覆蓋 性示意圖。 疋件符號說明 13 位元線 14 20 24 25 24 27 28 30 31 32 位元線接觸點 基質 複晶插塞 氧化部分 氧化層 第一介電層 第二介電層 位7L線部分 位元線 位元線接觸點 8 J:\menu\pending-92\92208.doc1223409 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a dynamic random access memory (DRAM). More specifically, it relates to a DRAM bit line and bit line. Method for forming contact structure. [Prior art] In the manufacturing process of body devices, the formation of wires and contact points of wires is widely used. In the _ manufacturing process, the contact structure is formed in the unit structure by filling the polycrystalline material with plugs and chemical mechanical polishing is performed to form the bit line contact points. The structure at this stage is roughly the same as the figure. Therefore, the contact area of the bit line contact points formed in the current process is relatively large. Lu Xun has become increasingly compact, and the spacing between bit lines has decreased. Referring to Figure i, when the contact area of the bit line at 3:12 is large, since the bit line n's coverage of the bit line contact point 12 = no birth, if the bit line is rich, then Rong Lusheng will not face The bridging phenomenon caused the structure of different hanging positions. Therefore, there is a need to overcome this problem. [Summary of the Invention]. The purpose of this Maoming is to provide a method for forming an age line connection structure. The formed bit line contact points have a smaller contact area. Another object is to provide a bit line and a method for forming a bit line contact structure, which can improve the lion-like prostitutes of the bit line, the dragon line, and the improper short circuit between the bit lines. According to one aspect of the present invention, the method of ageing a rider, based on a semi-finished structure in which a contact window has been filled with a compound plug, the method includes the step of removing a portion of the oxide layer so that the plug protrudes; Oxidizing an exposed portion of a protruding portion of the plug; and removing the oxidized portion of the plug. J: \ menu \ pending-92 \ 92208.doc 5 In addition, another method is to form the contact structure between the bit line and the bit line. 'Emulsion layer of mouth knife to make the plug protrude; make the plug protrude. The oxidized part; forming the first dielectric layer on the whole & the exposure; forming the second dielectric layer coating the photoresist on the second dielectric layer including the upper surface of the plug, exposing and developing , _, ^, And 疋 trenches, and fill the trench with metal to form bit lines. [Embodiment] FIG. 2a is a cross-sectional view showing a partial structure of a dynamic random access memory (surface) unit intermediate product, wherein the reference number 2G represents a base f, 22 is a polycrystalline plug, and 氧化 is an oxide layer in a shed. The structure shown is a compound plug 22 filled into the contact window. The upper surface of the polycrystalline silicon plug 22 may be planarized by, for example, chemical mechanical polishing (MP). As shown in this figure, firstly, a part of the oxide layer 24 is removed by wet money engraving or dry etch to make the polycrystalline silicon plug 22 protrude. Then, the protruding portion of the polycrystalline plug 22 is oxidized to form an oxidized portion 23, as shown in FIG. 2c. This oxidation treatment can be performed in any suitable manner. Next, the oxidized portion 23 'of the polycrystalline plug plug is removed by using a removal method such as a wet surname engraving method, as shown in FIG. 2d. Referring to Fig. 2e, after removing the oxidized portion of the polycrystalline plug 22, a first-dielectric layer 26 is deposited on the entire structure to any suitable structure. Compound crystal weaving 22 f silk out. The surface of the bribe structure can be flattened by CMP. The first dielectric layer 26 is a stop layer for planarization. J ： \ menu \ pending-92 \ 92208 .doc 6,: On top of the electrical layer 26, a second dielectric layer 28 is deposited, as shown in FIG. 2f. The second dielectric layer 28 may be an oxide layer. -In general, the second dielectric layer Shen Zhicai is a different dielectric layer 26. When the materials are different, the first dielectric layer 26 can be used as a side stop layer for the post-reading production step. The second dielectric layer 26 can also be made of the same material as the brother-dielectric layer, and the method in this case is still applicable. After that, a general-bit line manufacturing process is performed to form a photoresist on the second dielectric layer 26 as light. After the mask is exposed, developed, and engraved, a trench with a predetermined pattern is formed in the second dielectric layer%, and then a metal is filled in the trench to form a bit line. Finally, the photoresist d is removed as described in the first month. The dielectric layer 26 can be used as a side stop layer when a trench is formed. The structure after the figure and the member τ are hidden from view, this item is viewed by the bit line part. In Gu Zhong, the reference number 29 indicates the composition The part of the bit line. The material of the bit line part 29 can be steel, tungsten, or any suitable material. In the structure formed by the abstract of Figure 7F, the polycrystalline plug & The technology used for the phase car is small, that is, the critical size of the bit line contact point becomes smaller. The upper surface area of the contact point of the bit 70 line becomes smaller, improving the coverage of the bit line to the bit 2 contact point, so that there is a large margin between the bit lines, even if the bit line still has the help It will not cause a short circuit. It is not a matter of technology to go to W? It is well known to the present invention. Various modifications and changes can be made without departing from the spirit and scope of the present invention. The scope of protection of the present invention It is as defined in the attached patent. [Simplified description of the figure] J: \ menu \ pending-92 \ 92208.doc 7 1223409 Figure 1 shows the contact point of the bit line of the bit line of the bit line in the conventional technology. Coverage diagram; Figures 2 to 2g are cross-sectional views showing various steps of the method of the present invention; and Figure 3 is a diagram showing the coverage of bit line-to-bit line contact points formed according to the method of the present invention. Description 13 bit line 14 20 24 25 24 27 28 30 31 32 bit line contact point matrix compound plug oxide part of oxide layer first dielectric layer second dielectric layer 7L line part bit line bit line contact Point 8 J: \ menu \ pending-92 \ 92208.doc