KR19990017573A - Manufacturing method of DRAM cell - Google Patents

Abstract

A manufacturing method for simplifying the fabrication of DRAM cells is disclosed. The disclosed method comprises applying a nitride film on sidewalls and top of the gate after forming a gate of an access transistor, sequentially forming an oxide film and a nitride film over the exposed active region, and forming an oxide film over the entire substrate. And planarizing the oxide layer, and simultaneously forming a storage electrode forming contact hole and a bit line contact plug contact hole, applying a barrier metal to the contact holes, and then applying the bit line contact plug contact. Applying a conductive metal to the contact holes until all the holes are filled, removing metals on the oxide film, applying a capacitor dielectric film as a whole, and then applying a plate electrode forming metal; Patterning the plate electrode forming metal to complete the plate electrode and to expose the exposed dielectric film. Sir is the step and, characterized by covering the insulating film by photolithography and having a step, forming a bit line to cover the contact holes and the insulating film to form a bit line contact hole.

Description

Manufacturing method of DRAM cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly to a method for more simply manufacturing a cell of a dynamic random access memory.

In general, semiconductor memory devices tend to be highly integrated and high speed in order to meet consumer demand. In particular, the dynamic random access memory, which is commonly used as a main memory of a computer, is being integrated at a faster speed than other memory devices. With integration, design rules are reduced, which reduces the size of the memory cells and makes the manufacturing process more difficult. In a DRAM cell consisting of one access transistor and one storage capacitor, a reduction in cell size causes a reduction in capacitance. Therefore, much research has been done in the art for simply manufacturing a capacitor having a larger capacity in a smaller area in a simpler process. Among the various prior arts, U.S. Patent No. 5,332,685, issued in the United States on June 26, 1994, discloses a technique for manufacturing contact holes for storage electrodes and contact holes for bit line contact plugs at the same time to simplify the manufacture of DRAM cells. Is disclosed. Although the above-described prior art manufactures contact holes at once, the manufacturing process of the storage electrodes and the bit line contact plugs of the capacitors are manufactured in different processes, so the manufacturing process is still a complicated problem.

Accordingly, an object of the present invention is to provide a method for manufacturing a DRAM cell having a simpler manufacturing process.

Another object of the present invention is to provide a cell manufacturing method capable of simultaneously forming a storage electrode and a bit line contact plug of a capacitor.

It is still another object of the present invention to provide a storage electrode of a capacitor and a bit line contact plug simultaneously, as well as a method of simply manufacturing a plate electrode and a metal wiring.

1 to 6 are cross-sectional views illustrating a manufacturing process of a DRAM cell according to an embodiment of the present invention.

According to an aspect of the present invention, there is provided a method of manufacturing a DRAM cell, including forming a gate of an access transistor in an active region of a substrate, and then applying a nitride film to the sidewalls and the upper portion of the gate, Sequentially forming an oxide film and a nitride film on the upper surface, forming an oxide film on the entire substrate to cover the nitride films, and planarizing the oxide film and then performing a photolithography process to form a storage electrode contact hole and a bit line contact. Simultaneously forming a plug contact hole and applying a barrier metal to the contact holes to simultaneously form the storage electrode of the capacitor and the bit line contact plug, and then the bit line contact plug contact holes are filled. Applying a conductive metal to the contact holes until Removing the cores and applying the capacitor dielectric layer as a whole, and then applying a plate electrode forming metal; patterning the plate electrode forming metal to complete the plate electrode and etching the exposed dielectric layer; And forming a bit line contact hole through which the upper portion of the bit line contact plug is exposed by photo etching a portion of the insulating film, and forming a bit line covering the contact hole and the insulating film. do.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, description of preferred embodiments according to the present invention will be described with reference to the accompanying drawings. It should be noted that like reference numerals in the drawings indicate the same material or the same layer wherever possible.

1 to 6 are cross-sectional views showing the manufacturing procedure of the cell formation according to an embodiment of the present invention. In FIG. 1, a drain and a source, which are active regions of an access transistor, are formed between the field oxide films 20 of the semiconductor substrate 10. Here, the gate insulating film of the transistor is shown. The gate 30 of the access transistor is located on the gate insulating layer in the active region of the substrate 10 of FIG. 1. A nitride layer 32 is coated on the sidewalls and the upper portion of the gate 30, and an oxide layer 33 and a nitride layer 34 are sequentially formed on the exposed active region. Subsequently, a thick oxide film 40 of about 5000 GPa or more is formed on the entire substrate to cover the nitride films 32 and 34. The oxide film 40 is planarized by a planarization process such as CMP for high resolution of the photolithography process when the photoresist is applied in a subsequent process. FIG. 2 shows a pattern in which the photoresist 50 is entirely coated on the oxide layer 40 and then patterned by photo development. After the photographing process as shown in FIG. 2 is completed, an anisotropic etching process is performed to simultaneously form the storage electrode forming contact hole C1 and the bit line contact plug contact hole C2 as shown in FIG. 3. In order to simultaneously form the storage electrode 71 and the bit line contact plug 70 of the capacitor of FIG. 4, a barrier metal 60 is applied to the contact holes as shown in FIG. 3. The barrier metal 60 is a conventional metal material well known as a barrier metal. In FIG. 4, when a conductive metal such as tungsten is applied to the contact holes C1 and C2 until all of the bit line contact plug contact holes C2 are filled, the contact holes C1 may be formed by the difference in size between the contact holes. The stainless metal is not completely filled and an opening is left. As a result, the storage electrode of the capacitor and the bit line contact plug are simultaneously formed, thereby simplifying the manufacturing process. After removing the metals present on the oxide layer 40 and applying the capacitor dielectric layer 65 as a whole, the metal 80 for plate electrode formation is coated. The resultant of FIG. 4 is obtained by patterning the plate electrode forming metal 80 to complete the plate electrode and etching the exposed dielectric layer 65. Subsequently, a bit line contact hole 92 is formed to cover the insulating film 90 over the entire surface and photo-etch a portion of the insulating film 90 to expose the upper portion of the bit line contact plug 70 to obtain the result of FIG. 5. 6, a process of forming a bit line 96 covering the contact hole 92 and the insulating layer 90 is performed.

Although the above description has been made with one DRAM cell as an example, the present invention is not limited thereto, and various changes and modifications are possible.

As described above, according to the present invention, the DRAM cell can be more easily manufactured by simultaneously forming the storage electrode and the bit line contact plug of the capacitor and simply forming the plate electrode and the metal wiring.

Claims (2)

A method of manufacturing a DRAM cell, comprising: forming a gate of an access transistor in an active region of a substrate, applying a nitride film to sidewalls and an upper portion of the gate, and sequentially forming an oxide film and a nitride film on an exposed active region And forming an oxide film over the entire substrate to cover the nitride films, and simultaneously forming the storage electrode forming contact hole and the bit line contact plug contact hole by planarizing the oxide film and performing a photolithography process. In order to simultaneously form a storage electrode of the capacitor and the bit line contact plug, a barrier metal is applied to the contact holes, and then a conductive metal is applied to the contact holes until all the contact holes for the bit line contact plug are filled. Applying and removing metals on top of the oxide film and depositing a capacitor dielectric film. Applying a metal for forming a plate electrode and then applying a metal for forming a plate electrode; patterning the plate electrode forming metal to complete a plate electrode and etching the exposed dielectric layer; And forming a bit line contact hole through which the upper portion of the bit line contact plug is exposed by photo etching, and forming a bit line covering the contact hole and the insulating layer. The method of claim 1, wherein the storage electrode and the bitline contact plug comprise a tungsten metal layer.