KR100464540B1 - Capacitor Manufacturing Method for Semiconductor Devices - Google Patents

Capacitor Manufacturing Method for Semiconductor Devices Download PDF

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Publication number
KR100464540B1
KR100464540B1 KR1019960079989A KR19960079989A KR100464540B1 KR 100464540 B1 KR100464540 B1 KR 100464540B1 KR 1019960079989 A KR1019960079989 A KR 1019960079989A KR 19960079989 A KR19960079989 A KR 19960079989A KR 100464540 B1 KR100464540 B1 KR 100464540B1
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South Korea
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conductive layer
film
insulating film
capacitor
forming
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KR1019960079989A
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Korean (ko)
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KR19980060627A (en
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김대영
박철수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 반도체 기판 상부에 제 1절연막을 형성하고 제 1콘택홀을 형성하여 제 1도전층으로 매립한 다음, 그 상부에 제 2절연막을 형성하고 제 2콘택홀을 형성하여 전표면에 제 2도전층과 반구형 다결정 실리콘막을 형성한 후, 반구형 다결정 실리콘막과 제 2도전층 및 제 2절연막을 식각하여 제 1절연막이 노출되는 캐패시터를 형성함으로써 고집적화된 반도체 소자를 형성하여도 캐패시터의 정전용량을 증대시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, wherein a first insulating layer is formed on a semiconductor substrate, a first contact hole is formed and embedded in a first conductive layer, and a second insulating layer is formed on the second conductive layer. After forming a contact hole to form a second conductive layer and a semispherical polycrystalline silicon film on the entire surface, the semiconductor is highly integrated by forming a capacitor to expose the first insulating film by etching the hemispherical polycrystalline silicon film, the second conductive layer and the second insulating film. The present invention relates to a technology capable of increasing the capacitance of a capacitor even when an element is formed.

Description

반도체 소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 보다 상세하게는 반도체 소자의 메모리 제조공정에서 캐패시터를 형성시 캐패시터간의 이격거리를 충분히 확보하여 고집적화되는 반도체 소자를 형성하여도 캐패시터 용량을 증대시킬 수 있는 기술에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, a capacitor capacity can be increased even when a high density integrated semiconductor device is formed by sufficiently securing a separation distance between capacitors when a capacitor is formed in a memory manufacturing process of a semiconductor device. It is about technology.

일반적으로, 반도체 소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고 있다. 특히, 단위셀이 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게하면서 면적을 줄이는 것이 디램소자의 고집적화에 중요한 요인이 된다.In general, with the trend toward higher integration of semiconductor devices, the cell size is reduced, making it difficult to form capacitors with sufficient capacitance. In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, reducing the area while increasing the capacitance of a capacitor, which occupies a large area on a chip, is an important factor for high integration of the DRAM device.

그리고, 캐패시터의 정전용량을 증가시키기 위하여 유전상수가 높은 물질을 저장전극으로 사용하거나 저장전극의 두께를 얇게 하거나 또는 캐패시터의 표면적을 증가시키는 등의 방법을 사용하였다.In order to increase the capacitance of the capacitor, a method of using a material having a high dielectric constant as a storage electrode, reducing the thickness of the storage electrode, or increasing the surface area of the capacitor is used.

그러나, 이러한 방법들은 각각의 문제점을 가지고 있다. 즉, 높은 유전상수를 갖는 유전물질, 예를 들어 Ta2O5, TiO2 또는 SrTiO3 등은 신뢰도 및 박막 특성이 확실하게 확인되지 않아 실제 소자에 적용하기에는 어렵다.However, these methods have their respective problems. That is, a dielectric material having a high dielectric constant, such as Ta2O5, TiO2 or SrTiO3, is difficult to be applied to an actual device because reliability and thin film characteristics are not surely confirmed.

도 la 내지 도 1c는 종래 기술에 따른 반도체 소자의 캐패시터 제조공정도이다.La to 1c illustrate a manufacturing process of a capacitor of a semiconductor device according to the prior art.

먼저, 반도체 기판(10) 상부에 산화막으로 이루어진 일정 두께의 제 1절연막(12)을 형성한 다음, 콘택마스크로 식각하여 제 l콘택홀(14)을 형성한다.First, the first insulating layer 12 having a predetermined thickness formed of an oxide film is formed on the semiconductor substrate 10, and then the first contact hole 14 is formed by etching with a contact mask.

그 다음, 상기 구조의 전표면에 일정 두께의 제 1도전층(16)으로 상기 제 1콘택홀(14)을 매립한 다음, 일정 두께의 희생산화막(18)을 형성한다.(도 la 참조)Then, the first contact hole 14 is filled with the first conductive layer 16 having a predetermined thickness on the entire surface of the structure, and then a sacrificial oxide film 18 having a predetermined thickness is formed (see FIG. La).

다음, 노광마스크로 식각하여 희생산화막(18)패턴을 형성한 후 일정 두께의 제 2도전층(도시안됨)을 형성하여 상기 희생산화막(18)패턴의 측벽에 제 2도전층 스페이서(20)를 형성한다.(도 1b참조)Next, the sacrificial oxide film 18 is formed by etching with an exposure mask, and then a second conductive layer (not shown) having a predetermined thickness is formed to form a second conductive layer spacer 20 on the sidewall of the sacrificial oxide film 18. (See FIG. 1B).

그 다음, 상기 희생산화막(18)패턴을 제거한 다음 전표면에 반구형 다결정 실리콘막(22)을 형성하여 저장전극을 형성한다.Next, after removing the sacrificial oxide film 18 pattern, a hemispherical polycrystalline silicon film 22 is formed on the entire surface to form a storage electrode.

후속공정으로 유전체막(도시안됨)과 플레이트 전극(도시안됨)을 형성하여 캐패시터 공정을 완료한다.(도 1c 참조)In a subsequent process, a dielectric film (not shown) and a plate electrode (not shown) are formed to complete the capacitor process (see FIG. 1C).

상기한 바와 같이 종래 기술에 따르면 반도체 기판에 형성되는 캐패시터와 캐패시터간의 이격거리가 좁으므로 캐패시터간의 쇼트(short)될 위험이 존재하여 후속 공정을 실시하는 데 어려움이 있으며, 고집적화되는 반도체 소자를 형성하기 어려운 문제점이 있다.As described above, according to the related art, since the separation distance between the capacitor and the capacitor formed on the semiconductor substrate is narrow, there is a risk of shorting between the capacitors, which makes it difficult to perform a subsequent process and to form a highly integrated semiconductor device. There is a difficult problem.

본 발명은 상기한 문제점을 해결하기 위한 것으로 반도체 소자의 캐패시터 형성시 캐패시터 내측에만 반구형 다결정 실리콘막으로 형성하여 캐패시터간의 이격거리를 충분히 확보함으로써 고집적화에 충분한 정정용량을 확보할 수 있는 반도체소자를 형성할 수 있도록 하는 반도체 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and when forming a capacitor of a semiconductor device, a semiconductor device capable of securing a sufficient capacitance for high integration by forming a hemispherical polycrystalline silicon film only inside the capacitor to ensure sufficient separation distance between capacitors can be formed. It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device.

상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 캐패시터 제조방법은,Capacitor manufacturing method of a semiconductor device according to the present invention to achieve the above object,

반도체 기판 상부에 제 1절연막을 형성하는 공정과,Forming a first insulating film on the semiconductor substrate;

상기 제 1절연막을 통하여 상기 반도체기판에 접속되는 콘택플러그를 제1도전층으로 형성하는 공정과,Forming a contact plug connected to the semiconductor substrate through the first insulating film as a first conductive layer;

상기 제1도전층을 노출시키는 제 2절연막을 형성하는 공정과,Forming a second insulating film exposing the first conductive layer;

상기 제1도전층에 접속되는 제2도전층을 전체표면상부에 형성하는 공정과,Forming a second conductive layer connected to the first conductive layer on the entire surface;

상기 제2도전층의 표면에 반구형 다결정실리콘막을 형성하는 공정과,Forming a hemispherical polysilicon film on the surface of the second conductive layer;

상기 제2절연막 상측의 반구형 다결정실리콘막 및 제2도전층을 제거하는 공정과,Removing the hemispherical polysilicon film and the second conductive layer on the upper side of the second insulating film;

상기 제2절연막을 제거하여 저장전극을 형성하는 공정을 포함하는 것을 특징으로 한다.And removing the second insulating layer to form a storage electrode.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 캐패시터 제조 방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명의 일실시예에 따른 반도체 소자의 캐패시터 제조공정도이다.2A to 2E are diagrams illustrating a capacitor manufacturing process of a semiconductor device according to an embodiment of the present invention.

먼저, 반도체 기판(30) 상부에 산화막으로 이루어진 제 1절연막(32)을 형성한다.First, a first insulating film 32 made of an oxide film is formed on the semiconductor substrate 30.

콘택마스크를 이용한 사진식각공정으로 상기 제1절연막(32)을 식각하여 콘택부분으로 예정되는 제 1콘택홀(34)을 형성한다.(도 2a 참조)The first insulating layer 32 is etched by a photolithography process using a contact mask to form a first contact hole 34 intended as a contact portion (see FIG. 2A).

다음, 상기 구조의 전표면에 다결정 실리콘으로 이루어진 제1 도전층(36)을 형성하고 전면식각하여 상기 제 1콘택홀(43)을 매립하는 콘택플러그를 제1도전층(36)으로 형성한다. 이때, 상기 제 1도전층(36)의 전면식각공정은 상기 제1절연막(32)의 표면이 완전히 상기 표면이 노출되도록 실시한다.(도 2b 참조)Next, the first conductive layer 36 made of polycrystalline silicon is formed on the entire surface of the structure, and the entire surface is etched to form a contact plug for filling the first contact hole 43 as the first conductive layer 36. At this time, the entire surface etching process of the first conductive layer 36 is performed so that the surface of the first insulating layer 32 is completely exposed (see FIG. 2B).

그 다음, 전체표면상부에 제2절연막(38)을 형성하고 저장전극 마스크를 이용한 사진식각공정으로 상기 제2절연막(38)을 식각하는 상기 제 1도전층(36)으로 형성된 콘택플러그를 노출시키는 제 2콘택홀(40)을 형성한다. 이때, 상기 제2콘택홀(40)은 캐패시터의 저장전극이 형성될 영역을 말한다.Next, a second insulating film 38 is formed over the entire surface, and the contact plug formed of the first conductive layer 36 for etching the second insulating film 38 is exposed by a photolithography process using a storage electrode mask. The second contact hole 40 is formed. In this case, the second contact hole 40 refers to a region where the storage electrode of the capacitor is to be formed.

다음, 전체표면상부에 다결정 실리콘으로 이루어진 제 2도전층(42)을 형성하고 그 상부에 반구형 다결정 실리콘막(44)을 형성한다. (도 2c 참조)Next, a second conductive layer 42 made of polycrystalline silicon is formed on the entire surface, and a hemispherical polycrystalline silicon film 44 is formed thereon. (See Figure 2c)

그 다음, 전체표면상부에 산화막(도시안됨)이나 감광막(도시안됨)을 도포하고 상기 제2절연막(38)이 노출되도록 화학기계연마 (chemical mechanical polishing, 이하에서 CMP 라 함 ) 공정을 실시한 다음, 상기 산화막이나 제거한다.Then, an oxide film (not shown) or a photoresist (not shown) is applied over the entire surface, and a chemical mechanical polishing (hereinafter referred to as CMP) process is performed to expose the second insulating film 38. The oxide film is removed.

이때, 상기 화학기계연마 공정 대신 에치백 공정으로 상기 제2절연막(38)을 노출시키고 남는 산화막이나 감광막을 제거한다. (도 2d 참조)In this case, the second insulating layer 38 is exposed by an etch back process instead of the chemical mechanical polishing process, and the remaining oxide or photosensitive layer is removed. (See FIG. 2D)

다음, 상기 도 2d 의 공정으로 노출된 상기 제 2절연막(38)을 제거하여 상기 제 1절연막(32)의 상부 표면을 노출시키는 동시에 저장전극을 형성한다.Next, the second insulating layer 38 exposed by the process of FIG. 2D is removed to expose the upper surface of the first insulating layer 32 to form a storage electrode.

후속공정으로, 상기 저장전극의 포면에 유전체막(도시안됨)과 플레이트전극(도시안됨)을 형성하여 캐패시터를 형성함으로써 이웃하는 캐패시터간에 충분한 이격거리를 확보할 수 있도록 하는 동시에 반도체소자의 고집적화에 충분한 정전용량을 확보할 수 있도록 한다. (도 2e 참조)In a subsequent process, a dielectric film (not shown) and a plate electrode (not shown) are formed on the surface of the storage electrode to form a capacitor to ensure sufficient separation distance between neighboring capacitors and at the same time sufficient for high integration of semiconductor devices. Make sure to secure the capacitance. (See Figure 2E)

상기한 바와 같이 본 발명에 따른 반도체 소자의 캐패시터 제조방법은, 캐패시터간의 표면적을 충분히 확보하여 캐패시터 용량을 증대시키며, 후속 공정을 용이하게 실시할 수 있도록 캐패시터 간의 거리를 확보할 수 있어 반도체소자의 생산성과 수율을 향상시키며 그에 따른 반도체 소자를 고집적화하는 가능하게 하는 효과를 제공한다.As described above, in the method of manufacturing a capacitor of a semiconductor device according to the present invention, the surface area between capacitors is sufficiently secured to increase the capacity of the capacitor, and the distance between the capacitors can be secured so that subsequent processes can be easily performed. And improves the yield and thus enables the integration of semiconductor devices into high integration.

도 la 내지 도 1c는 종래 기술에 따른 반도체 소자의 캐패시터 제조공정도.La to Figure 1c is a capacitor manufacturing process of the semiconductor device according to the prior art.

도 2a 내지 도 2e는 본 발명의 일실시예에 따른 반도체 소자의 캐패시터 제조공정도.2a to 2e is a capacitor manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

10, 30 : 반도체 기판 12, 32 : 제 1절연막10, 30: semiconductor substrate 12, 32: first insulating film

14, 34 : 제 1콘택홀 16, 36 : 제 1도전층14, 34: first contact hole 16, 36: first conductive layer

18 : 희생산화막 20 : 도전층스페이서18: sacrificial oxide film 20: conductive layer spacer

22, 14 : 반구형 다결정 실리콘막 38 : 제 2절연막22, 14 hemispherical polycrystalline silicon film 38: second insulating film

40 : 제 2콘택홀 42 : 제 2도전층.40: second contact hole 42: second conductive layer.

Claims (5)

반도체 기판 상부에 제 1절연막을 형성하는 공정과,Forming a first insulating film on the semiconductor substrate; 상기 제 1절연막을 통하여 상기 반도체기판에 접속되는 콘택플러그를 제1도전층으로 형성하는 공정과,Forming a contact plug connected to the semiconductor substrate through the first insulating film as a first conductive layer; 상기 제 1도전층을 노출시키는 제 2절연막을 형성하는 공정과,Forming a second insulating film exposing the first conductive layer; 상기 제1도전층에 접속되는 제2도전층을 전체표면상부에 형성하는 공정과,Forming a second conductive layer connected to the first conductive layer on the entire surface; 상기 제2도전층의 표면에 반구형 다결정실리콘막을 형성하는 공정과,Forming a hemispherical polysilicon film on the surface of the second conductive layer; 상기 제2절연막 상측의 반구형 다결정실리콘막 및 제2도전층을 제거하는 공정과,Removing the hemispherical polysilicon film and the second conductive layer on the upper side of the second insulating film; 상기 제2절연막을 제거하여 저장전극을 형성하는 공정을 포함하는 반도체소자의 캐패시터 제조방법.And removing the second insulating layer to form a storage electrode. 청구항 1 에 있어서,The method according to claim 1, 상기 제 1도전층 및 제 2도전층은 다결정 실리콘으로 이루어진 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The first conductive layer and the second conductive layer is a capacitor manufacturing method of a semiconductor device, characterized in that made of polycrystalline silicon. 청구항 1 에 있어서,The method according to claim 1, 상기 제2절연막 상측의 반구형 다결정실리콘막 및 제2도전층의 제거 공정은 전체표면상부에 감광막을 도포하고 상기 제2절연막이 노출시키는 에치백을 실시한 다음, 남은 감광막을 제거하는 것임을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The semi-spherical polysilicon film and the second conductive layer on the upper side of the second insulating film is removed, the photoresist is applied over the entire surface, and subjected to the etch back to expose the second insulating film, and then the remaining photosensitive film is removed. Capacitor manufacturing method of device. 청구항 1 에 있어서,The method according to claim 1, 상기 제2절연막 상측의 반구형 다결정실리콘막 및 제2도전층의 제거 공정은 전체표면상부에 산화막을 도포하고 상기 제2절연막이 노출시키는 에치백한 다음, 남은 산화막을 제거하는 것임을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The removal process of the hemispherical polysilicon film and the second conductive layer on the upper side of the second insulating film is to apply an oxide film on the entire surface, to etch back to expose the second insulating film, and then to remove the remaining oxide film. Capacitor manufacturing method. 청구항 1 에 있어서,The method according to claim 1, 상기 제2절연막 상측의 반구형 다결정실리콘막 및 제2도전층의 제거 공정은 전체표면상부에 감광막이나 산화막을 도포하고 상기 제2절연감이 노출시키는 화학기계연마 ( CMP ) 공정을 실시한 다음, 남은 감광막이나 산화막을 제거하는 것임을 특징으로 하는 반도체 소자의 캐패시터 제조방법.Removing the hemispherical polysilicon film and the second conductive layer on the upper side of the second insulating film is performed by applying a photosensitive film or an oxide film on the entire surface and performing a chemical mechanical polishing (CMP) process to expose the second insulating film, and then the remaining photosensitive film. Or a method for manufacturing a capacitor of a semiconductor device, characterized in that the oxide film is removed.
KR1019960079989A 1996-12-31 1996-12-31 Capacitor Manufacturing Method for Semiconductor Devices KR100464540B1 (en)

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JPH0846152A (en) * 1994-07-29 1996-02-16 Nec Corp Semiconductor memory and manufacture
KR960032742A (en) * 1995-02-20 1996-09-17 김광호 Capacitor Manufacturing Method of Semiconductor Device
KR960043191A (en) * 1995-05-30 1996-12-23 김광호 Capacitor for semiconductor device having metal plug in storage node and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0846152A (en) * 1994-07-29 1996-02-16 Nec Corp Semiconductor memory and manufacture
KR960006040A (en) * 1994-07-29 1996-02-23 가네꼬 히사시 Semiconductor Memory and Manufacturing Method Thereof
KR960032742A (en) * 1995-02-20 1996-09-17 김광호 Capacitor Manufacturing Method of Semiconductor Device
KR960043191A (en) * 1995-05-30 1996-12-23 김광호 Capacitor for semiconductor device having metal plug in storage node and manufacturing method thereof

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