KR19980060627A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents
Capacitor Manufacturing Method of Semiconductor Device Download PDFInfo
- Publication number
- KR19980060627A KR19980060627A KR1019960079989A KR19960079989A KR19980060627A KR 19980060627 A KR19980060627 A KR 19980060627A KR 1019960079989 A KR1019960079989 A KR 1019960079989A KR 19960079989 A KR19960079989 A KR 19960079989A KR 19980060627 A KR19980060627 A KR 19980060627A
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- Prior art keywords
- polycrystalline silicon
- conductive layer
- silicon film
- film
- capacitor
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- 239000003990 capacitor Substances 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 239000010408 film Substances 0.000 description 34
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 반도체 기판 상부에 제1절연막을 형성하고 제1콘택홀을 형성하여 제1도전층으로 매립한 다음, 그 상부에 제2절연막을 형성하고 제2콘택홀을 형성하여 전표면에 제2도전층과 반구형 다결정 실리콘막을 형성한 후, 반구형 다결정 실리콘막과 제2도전층 및 제2절연막을 식각하여 제1절연막이 노출되는 캐패시터를 형성함으로써 고집적화된 반도체 소자를 형성하여도 캐패시터의 정전용량을 증대시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, wherein a first insulating layer is formed on a semiconductor substrate, a first contact hole is formed and embedded in a first conductive layer, and a second insulating layer is formed thereon and a second A semiconductor is highly integrated by forming a contact hole to form a second conductive layer and a semispherical polycrystalline silicon film on the entire surface, and then etching the hemispherical polycrystalline silicon film, the second conductive layer and the second insulating film to form a capacitor to expose the first insulating film. The present invention relates to a technology capable of increasing the capacitance of a capacitor even when an element is formed.
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 보다 상세하게는 반도체 소자의 메모리 제조공정에서 캐패시터를 형성시 캐패시터간의 이격거리를 충분히 확보하여 고집적화되는 반도체 소자를 형성하여도 캐패시터 용량을 증대시킬 수 있는 기술에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, a capacitor capacity can be increased even when a high density integrated semiconductor device is formed by sufficiently securing a separation distance between capacitors when a capacitor is formed in a memory manufacturing process of a semiconductor device. It is about technology.
일반적으로, 반도체 소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고 있다. 특히, 단위셀인 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게하면서 면적을 줄이는 것이 디램소자의 고집적화에 중요한 요인이 된다.In general, with the trend toward higher integration of semiconductor devices, the cell size is reduced, making it difficult to form capacitors with sufficient capacitance. In particular, in a DRAM device composed of a MOS transistor and a capacitor, which are unit cells, reducing the area while increasing the capacitance of a capacitor, which occupies a large area of the chip, is an important factor for high integration of the DRAM device.
그리고, 캐패시터의 정전용량을 증가시키기 위하여 유전상수가 높은 물질을 저자전극으로 사용하거나 저장전극의 두께를 얇게 하거나 또는 캐패시터의 표면적을 증가시키는 등의 방법을 사용하였다.In order to increase the capacitance of the capacitor, a method of using a material having a high dielectric constant as the low electrode, reducing the thickness of the storage electrode, or increasing the surface area of the capacitor is used.
그러나, 이러한 방법들은 각각의 문제점을 가지고 있다. 즉, 높은 유전상수를 갖는 유전물질, 예를 들어 Ta2O5, TiO2또는 SrTiO3등은 신뢰도 및 박막 특성이 확실하게 확인되지 않아 실제 소자에 적용하기에는 어렵다.However, these methods have their respective problems. That is, a dielectric material having a high dielectric constant, such as Ta 2 O 5 , TiO 2 or SrTiO 3 , is difficult to be applied to an actual device because reliability and thin film characteristics are not surely confirmed.
도 1a 내지 도 1c는 종래 술에 따른 반도체 소자의 캐패시터 제조공정도이다.1A to 1C are diagrams illustrating a capacitor manufacturing process of a semiconductor device according to the related art.
먼저, 반도체 기판(10) 상부에 산화막으로 이루어진 일정 두께의 제1절연막(12)을 형성한 다음, 콘택마스크로 식각하여 제1콘택홀(14)을 형성한다.First, a first insulating layer 12 having a predetermined thickness of an oxide film is formed on the semiconductor substrate 10, and then the first contact hole 14 is formed by etching with a contact mask.
그 다음, 상기 구조의 전표면에 일정 두께의 제1도전층(16)으로 상기 제1콘택홀(14)을 매립한 다음, 일정 두께의 희생산화막(18)을 형성한다(도 1a 참조).Then, the first contact hole 14 is filled with the first conductive layer 16 having a predetermined thickness on the entire surface of the structure, and then a sacrificial oxide film 18 having a predetermined thickness is formed (see FIG. 1A).
다음, 노광마스크로 식각하여 희생산화막(18) 패턴을 형성한 후 일정 두께의 제2도전층(도시 않됨)을 형성하여 상기 희생산화막(18) 패턴의 측벽에 제2도전층 스페이서(20)를 형성한다(도 1b 참조).Next, the sacrificial oxide film 18 is formed by etching with an exposure mask, and then a second conductive layer (not shown) having a predetermined thickness is formed to form a second conductive layer spacer 20 on the sidewall of the sacrificial oxide film 18. Form (see FIG. 1B).
그 다음, 상기 희생산화막(18) 패턴을 제거한 다음 전표면에 일정 두께의 다결정 실리콘막(22)을 형성, 식각하여 식각선택비 차에 의한 반구형 다결정 실리콘막을 형성하여 저장전극을 형성한 다음, 후속공정으로 유전체막(도시 않됨)과 플레이트전극(도시 않됨)을 형성하여 캐패시터 공정을 완료한다(도 1c 참조).Next, after removing the sacrificial oxide film 18 pattern, a polycrystalline silicon film 22 having a predetermined thickness is formed and etched on the entire surface to form a hemispherical polycrystalline silicon film due to an etching selectivity difference to form a storage electrode. The process forms a dielectric film (not shown) and a plate electrode (not shown) to complete the capacitor process (see FIG. 1C).
상기한 바와 같이 종래 기술에 따르면 반도체 기판에 형성되는 캐패시터와 캐패시터간의 이격거리가 좁으므로 캐패시터간의 쇼트(short)될 위험이 존재하여 후속 공정을 실시하는 데 어려움이 있으며, 고집적화되는 반도체 소자를 형성하기 어려운 문제점이 있다.As described above, according to the related art, since the separation distance between the capacitor and the capacitor formed on the semiconductor substrate is narrow, there is a risk of shorting between the capacitors, which makes it difficult to perform a subsequent process and to form a highly integrated semiconductor device. There is a difficult problem.
이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 반도체 소자의 캐패시터 형성시 캐패시터 내측에만 반구형 다결정 실리콘막으로 형성함으로써 캐패시터간의 이격거리를 충분히 확보하여 고집적화되는 반도체 소자를 형성하여도 캐패시터 용량을 증대시킬 수 있는 반도체 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above problems, and when the capacitor of the semiconductor device is formed, the hemispherical polycrystalline silicon film is formed only inside the capacitor, thereby sufficiently increasing the capacitance of the capacitor even when forming a highly integrated semiconductor device. It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 캐패시터 제조공정도,1A to 1C are diagrams illustrating a capacitor manufacturing process of a semiconductor device according to the prior art;
도 2a 내지 도 2e는 본 발명의 일실시예에 따른 반도체 소자의 캐패시터 제조공정도.2a to 2e is a capacitor manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10,30:반도체 기판12,32:제1절연막10, 30: semiconductor substrate 12, 32: first insulating film
14,34:제1콘택홀16,36:제1도전층14, 34: first contact hole 16, 36: first conductive layer
18:희생산화막20:도전층스페이서18: dilution film 20: conductive layer spacer
22,44:다결정 실리콘막38:제2절연막22,44 polycrystalline silicon film 38: second insulating film
40:제2콘택홀42:제2도전층40: second contact hole 42: second conductive layer
상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 캐패시터 제조방법은;Capacitor manufacturing method of a semiconductor device according to the present invention to achieve the above object;
반도체 기판 상부에 제1절연막을 형성하는 공정과;Forming a first insulating film over the semiconductor substrate;
상기 제1절연막을 식각하여 제1콘택홀을 형성하는 공정과;Etching the first insulating layer to form a first contact hole;
상기 구조의 전표면에 제1도전층으로 형성하는 공정과;Forming a first conductive layer on the entire surface of the structure;
상기 제1도전층을 전면식각하되 상기 제1콘택홀을 매립하고 상기 제1절연막이 노출되도록 식각하는 공정과;Etching the entire surface of the first conductive layer while filling the first contact hole and exposing the first insulating layer;
상기 구조의 전표면에 제2절연막을 형성하는 공정과;Forming a second insulating film on the entire surface of the structure;
상기 제2절연막을 식각하여 상기 제1콘택홀 부위에 제2콘택홀을 형성하는 공정과;Etching the second insulating layer to form a second contact hole in the first contact hole;
상기 구조의 전표면에 제2도전층을 형성하는 공정과;Forming a second conductive layer on the entire surface of the structure;
상기 제2도전층 상부에 다결정 실리콘막을 형성하는 공정과;Forming a polycrystalline silicon film on the second conductive layer;
상기 다결정 실리콘막을 식각하여 반구형 다결정 실리콘막을 형성하는 공정과;Etching the polycrystalline silicon film to form a hemispherical polycrystalline silicon film;
상기 제2절연막 상부의 상기 반구형 다결정 실리콘막과 제2도전층 및 제2절연막을 식각하여 상기 제1절연막이 노출되도록 형성하는 공정과;Etching the hemispherical polycrystalline silicon film, the second conductive layer, and the second insulating film on the second insulating film to expose the first insulating film;
상기 반구형 다결정 실리콘막과 제2도전층 및 제2절연막을 제거하는 공정을 포함하는 것을 특징으로 한다.And removing the hemispherical polycrystalline silicon film, the second conductive layer, and the second insulating film.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 캐패시터 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 일실시예에 따른 반도체 소자의 캐패시터 제조공정도이다.2A to 2E are diagrams illustrating a capacitor manufacturing process of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체 기판(30) 상부에 산화막으로 이루어진 제1절연막(32)를 형성한 다음, 콘택마스크로 식각하여 콘택 부분으로 예정되는 제1콘택홀(34)을 형성한다(도 2a 참조).First, a first insulating layer 32 formed of an oxide film is formed on the semiconductor substrate 30, and then etched with a contact mask to form a first contact hole 34 intended as a contact portion (see FIG. 2A).
다음, 상기 구조의 전표면에 다결정 실리콘으로 이루어진 제1도전층(36)을 형성하여 전면식각하되 상기 제1콘택홀(34)을 매립하고 상기 제1절연막(32)의 표면이 노출되도록 식각한다(도 2b 참조).Next, a first conductive layer 36 made of polycrystalline silicon is formed on the entire surface of the structure to etch the entire surface, and the first contact hole 34 is embedded, and the surface of the first insulating layer 32 is exposed. (See FIG. 2B).
그 다음, 상기 구조의 전표면에 다결정 실리콘으로 이루어진 제2절연막(38)을 형성하고 식각하여 상기 제1콘택홀(34) 부위에 제2콘택홀(40)을 형성한다.Next, a second insulating layer 38 made of polycrystalline silicon is formed on the entire surface of the structure and etched to form a second contact hole 40 in the portion of the first contact hole 34.
다음, 상기 구조의 전표면에 다결정 실리콘막으로 이루어진 제2도전층(42)을 형성하고 그 상부에 다결정 실리콘막(44)을 형성한 다음 식각선택비차에 의한 식각 공정으로 반구형 다결정 실리콘막(44)을 형성한다(도 2c 참조).Next, a second conductive layer 42 made of a polycrystalline silicon film is formed on the entire surface of the structure, and a polycrystalline silicon film 44 is formed thereon, and then the hemispherical polycrystalline silicon film 44 is etched by an etching selectivity difference. ) (See FIG. 2C).
그 다음, 상기 반구형 다결정 실리콘막(44) 상부에 감광막(도시되지 않음) 또는 산화막(도시되지 않음)을 도포한 후, 노광마스크로 식각하여 상기 제2절연막(38) 상부의 표면이 노출되도록 상기 반구형 다결정 실리콘막(44)과 제2도전층(42)을 순차적으로 식각한 다음 화학적·기계적연마방법으로 상기 반구형 다결정 실리콘막(44)과 제2도전층(42)을 제거한다(도 2d 참조).Next, a photoresist film (not shown) or an oxide film (not shown) is coated on the hemispherical polycrystalline silicon film 44 and then etched with an exposure mask to expose the surface of the upper portion of the second insulating film 38. The hemispherical polycrystalline silicon film 44 and the second conductive layer 42 are sequentially etched, and then the hemispherical polycrystalline silicon film 44 and the second conductive layer 42 are removed by chemical and mechanical polishing methods (see FIG. 2D). ).
다음, 상기 제2절연막(38)을 식각하여 제1절연막(32)의 상부표면이 노출되도록 형성한 다음, 상기 제2절연막(38)을 제거하여 저장전극을 형성한 다음, 후속공정으로 유전체막(도시되지 않음)과 플레이트전극(도시되지 않음)을 형성함으로써 캐패시터간의 충분한 이격거리를 확보하는 본 발명에 따른 캐패시터 공정을 완료한다(도 2e 참조).Next, the second insulating layer 38 is etched to form an upper surface of the first insulating layer 32, and then the second insulating layer 38 is removed to form a storage electrode. By forming the electrode (not shown) and the plate electrode (not shown), the capacitor process according to the present invention to secure a sufficient separation distance between the capacitors is completed (see FIG. 2E).
상기한 바와 같이 본 발명에 따른 반도체 소자의 캐패시터 제조방법은 캐패시터간의 표면적을 충분히 확보하여 캐패시터 용량을 증대시키며, 후속 공정을 용이하게 실시할 수 있으므로 생산성과 수율을 향상시키며, 반도체 소자를 고집적화하는 효과가 있다.As described above, the method of manufacturing a capacitor of a semiconductor device according to the present invention increases the capacity of a capacitor by sufficiently securing the surface area between capacitors, and it is possible to easily carry out subsequent processes, thereby improving productivity and yield and increasing the integration of semiconductor devices. There is.
Claims (5)
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| KR1019960079989A KR100464540B1 (en) | 1996-12-31 | 1996-12-31 | Capacitor Manufacturing Method for Semiconductor Devices |
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| KR1019960079989A KR100464540B1 (en) | 1996-12-31 | 1996-12-31 | Capacitor Manufacturing Method for Semiconductor Devices |
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| KR100527549B1 (en) * | 1998-12-30 | 2006-04-21 | 주식회사 하이닉스반도체 | Method for forming storage electrode of semiconductor device |
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| JP2956482B2 (en) * | 1994-07-29 | 1999-10-04 | 日本電気株式会社 | Semiconductor memory device and method of manufacturing the same |
| KR100319875B1 (en) * | 1995-02-20 | 2002-08-13 | 삼성전자 주식회사 | Capacitor Manufacturing Method for Semiconductor Devices |
| KR100224653B1 (en) * | 1995-05-30 | 1999-10-15 | 윤종용 | Capacitor with storage node having metal plug in semiconductor device and manufacturing method thereof |
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