TW379416B - Method of manufacturing dual damascence - Google Patents

Method of manufacturing dual damascence Download PDF

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Publication number
TW379416B
TW379416B TW87106840A TW87106840A TW379416B TW 379416 B TW379416 B TW 379416B TW 87106840 A TW87106840 A TW 87106840A TW 87106840 A TW87106840 A TW 87106840A TW 379416 B TW379416 B TW 379416B
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TW
Taiwan
Prior art keywords
layer
opening
manufacturing
oxide layer
scope
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Application number
TW87106840A
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Chinese (zh)
Inventor
Meng-Jin Tsai
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United Microelectronics Corp
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Priority to TW87106840A priority Critical patent/TW379416B/en
Priority to DE1998136379 priority patent/DE19836379A1/en
Priority to JP10228796A priority patent/JP2969109B1/en
Priority to FR9810540A priority patent/FR2778268A1/en
Application granted granted Critical
Publication of TW379416B publication Critical patent/TW379416B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing dual damascence, including the forming of a protruding oxide layer that covers the conductive layer on the substrate, and this protrusion is in correspondence to the conductive layer. The formed isolation layer covers the oxide layer. Chemical mechanical polishing is used to remove the protrusion for the forming of an opening that is corresponding to the conductive layer, and thus saved one or more photoresist and micrifilm processes.

Description

經濟部中央榡準局貝Η消费合作社印掣 2866twf. doc/ 005 八7 __B7__ 五、發明説明（I ) 本發明是有關於一種半導體之製程，且特別是有關於 一種雙重金屬鑲嵌（Dual Damascence)之製造方法。 當積體電路的積集度增加，其所需的金屬內連線 (Interconnect)數目也跟著增加，因此兩層以上的金屬層設 計，便逐漸成爲許多積體電路所必須採用的方法。當積體 電路的積集度持續增加，對於製造良率佳，以及可靠度好 的金屬內連線的困難度也會增加；金屬鑲嵌法係一種在介 電層中先蝕刻出金屬內連線的溝渠，再塡入金屬當作內連 線的方法，此法可以滿足製程中對高可靠度及高良率內連 線的要求，所以此法將成爲在深次微米(Sub-Quarter Micron) 中內連線製造方法的最佳選擇。 第1A至1C圖係繪示習知雙重金屬鑲嵌的製造流程剖 面圖。請參照第1A圖，提供一基底10，此基底1〇上已形 成有導體層14。此導體層14係用來耦接至基底1〇上其他 欲導通之結構(未顯示）。並且導體層14與更包括形成有內 金屬介電層12,用以避免導體層Η其他欲導通之結構之 間’在非預設爲導通的位置上產生不當的導通。 接著，例如使用低壓化學氣相沉積法，形成一層氧化 層16覆蓋導體層14。並且，例如使用低壓化學氣相沉積 法’形成一層隔離層18覆蓋氧化層16，其中隔離層18之 材質例如爲氮化矽(Silicon Nitride)。然後，同樣例如使用 低壓化學氣相沉積法，形成一層氧化層20覆蓋隔離層18。 接著，上一光阻層21定義氧化層20，暴露出部份的氧化 層20,其中此氧化層20上暴露出的部份對應於導體層14。 3 本紙張尺度適用中國囤家標準（CNS ) A<4規格（2〗〇x297公釐） I 裝 I I ,¾ 口 絲 (請先閲讀背面之注意事項再填寫本頁) 經漓部中央榡準局貝工消費合作社印聚 2 8 6 6twf, doc/ 005 八7 ____B7_____ 五、發明説明（>) 請參照第1B圖，使用傳統的微影蝕刻技術，蝕刻暴 露出的氧化層20，並且往下蝕刻穿過隔離層18，以形成 一開口 22暴露出氧化層16。然後移除光阻層21，移除的 方法例如爲使用氧電漿法。接著，上另一光阻層24進一 步定義氧化層20，暴露出開口 22與部份的氧化層20，其 中更包括暴露出開口 22兩側之部份氧化層20。 請參照第1C圖，使用傳統的微影蝕刻技術，繼續蝕 刻開口 22中所暴露出氧化層16，藉以使得開口 22進一步 暴露出隔離層18，以及蝕刻光阻層24所暴露出的氧化層 20與開口 22兩側之部份氧化層20，以分別形成一開口 26 與28，分別暴露出隔離層18。其中，開口 28更包括暴露 出開口 22。 接著，例如使用氧電漿法，移除光阻層24。然後，例 如使用濺鍍法或化學氣相沉積法，形成一導體層30塡入 於開口 22與28中，接觸至導體層14，並且塡入開口 26 中。 然後，進行後續的步驟以完成雙重金屬鑲嵌之製造。 然而，此後續製程爲熟習此技藝者所能輕易完成，故此處 不再贅述。 然而，此後續製程，因爲需要進行兩次上光阻及微影 步驟，所以製程上較複雜，而且容易產生對焦不準的現象。 因此本發明的主要目的就是在提供一種雙重金屬鑲嵌 之製造方法，僅需使用一次上光阻及微影步驟，因此製程 簡單且不會產生對焦不準的現象。 4 本紙張尺度適用中ί國家標準（CNS ) A4規格（2丨〇X297公釐)~ ----：------餐------、訂------0 (請先閲讀背面之注意事項再填寫本頁) 2866twf.doc/005 A7 B7 經滴部中央標準局貝工消费合作社印裝 五、發明説明（彡） 根據本發明的目的，提出一種雙重金屬鑲嵌之製造方 法，包括形成一具有突起部份之氧化層覆蓋基底上的導體 層，並且此突起部份對應於導體層。接著，形成一隔離層， 覆蓋氧化層。然後，例如使用化學機械硏磨法去除此突起 部份，以形成一開口，其中此開口對應於導體層。以及， 進行其他後續步驟。 因此，本發明之方法可以比習知技藝省一次上光阻及 微影步驟，並且製程較簡單。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1A至1C圖係繪示習知雙重金屬鑲嵌的製造流程剖 面圖；以及 第2A至2C圖係繪示依照本發明一較佳實施例的一種 雙重金屬鑲嵌的製造流程剖面圖。 圖示標記說明： 10、50 :基底 12、52 :內金屬介電層 14 ' 30、53、54、68 :導體層 16、20、56、60 :氧化層 18、58 :隔離層 21、24、62 :光阻層 22 ' 26、28、59、64 :開口 5 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公着)" ----.------^裝------訂------絲 (請先閱讀背面之注意事項再填寫本頁) 2866twf.doc/〇〇5 A7 B7 五、發明説明（《/·) 57、61 :突起部份 實施例, 第2A至2C圖係繪示依照本發明一較佳實施例的一種 雙重金屬鑲嵌的製造流程剖面圖。請參照第2A圖，提供 一基底50，此基底50上已形成有導體層54與53。此導體 層54係用來耦接至基底50上其他欲導通之結構(未顯示）。 並且導體層54與更包括形成有內金屬介電層52,用以避 免導體層54其他欲導通之結構之間，在非預設爲導通的 位置上產生不當的導通。其中導體層54的寬度較寬，而 導體層53的寬度較窄。 接著，例如使用高密度電漿(High Density Plasma ; HDP) 化學氣相沉積法，形成一層氧化層56覆蓋導體層53與54。 因爲高密度電漿化學氣相沉積法，在沉積過程中具有獨特 的削角現象，因此會產生較佳的突起部份57與61。其中， 此突起部份58的位置對應於導體層54，而突起部份57的 位置對應於導體層53。並且，因爲導體層54的寬度大於 導體層53，所以突起部份61的突起高度大於突起部份57 的突起高度。 然後，例如使用低壓化學氣相沉積法，形成一層隔離 層58覆蓋氧化層56，其中隔離層58之材質例如爲氮化矽 或氮氧化矽。其中，此隔離層58會隨著氧化層56的表面 而起伏，並且隔離層58上高起之處對應於突起部份57與 6卜 接著，例如使用化學機械硏磨（Chemical Mechanical 6 本紙張尺度適用中國國家標準（CNS )六4说格（210Χ297公釐） ----------^------，1T------Μ (請先閲讀背面之注意事項再填寫本頁) 教满部中央標率局貝工消费合作社印^ 2866twf.doc/005 A7 B7 經濟部中央標率局貝工消費合作社印聚 五、發明説明（f)Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, Beida Consumer Cooperative 2866twf. Doc / 005 8 7 __B7__ V. Description of the Invention (I) The present invention relates to a semiconductor process, and in particular to a dual metal inlay (Dual Damascence) Of manufacturing method. As the integration degree of integrated circuits increases, the number of metal interconnects required by them also increases. Therefore, the design of two or more metal layers has gradually become a method that many integrated circuits must adopt. When the integration degree of integrated circuits continues to increase, the difficulty of manufacturing metal interconnects with good yield and reliability will also increase; the metal damascene method is a method of first etching out metal interconnects in a dielectric layer Trench, and then pour metal into the method of interconnection. This method can meet the requirements of high reliability and high yield interconnection in the process. Therefore, this method will become a sub-quarter micron. The best choice for interconnect manufacturing methods. Figures 1A to 1C are cross-sectional views showing the manufacturing process of a conventional double metal inlay. Referring to FIG. 1A, a substrate 10 is provided, and a conductive layer 14 has been formed on the substrate 10. The conductor layer 14 is used for coupling to other structures (not shown) on the substrate 10 to be conducted. In addition, the conductive layer 14 and the inner metal dielectric layer 12 are formed to prevent the conductive layer Η other structures to be conducted from conducting conduction 'at an unpredicted position. Next, for example, a low-pressure chemical vapor deposition method is used to form an oxide layer 16 to cover the conductor layer 14. And, for example, a low pressure chemical vapor deposition method is used to form an isolation layer 18 to cover the oxide layer 16, wherein the material of the isolation layer 18 is, for example, silicon nitride (Silicon Nitride). Then, for example, a low-pressure chemical vapor deposition method is used to form an oxide layer 20 to cover the isolation layer 18. Next, the last photoresist layer 21 defines the oxide layer 20, and a part of the oxide layer 20 is exposed. The exposed part of the oxide layer 20 corresponds to the conductor layer 14. 3 This paper size applies to China Standards (CNS) A < 4 size (2〗 〇297mm) I installed II, ¾ mouth silk (Please read the precautions on the back before filling this page) Local Shellfish Consumer Cooperative Co., Ltd. Print 2 8 6 6twf, doc / 005 8 7 ____B7_____ 5. Description of the Invention (>) Please refer to Figure 1B, using the traditional lithography etching technology, to etch the exposed oxide layer 20, and Under-etching passes through the isolation layer 18 to form an opening 22 to expose the oxide layer 16. The photoresist layer 21 is then removed by a method such as an oxygen plasma method. Next, another photoresist layer 24 is further defined as the oxide layer 20, and the opening 22 and a part of the oxide layer 20 are exposed, which further includes a part of the oxide layer 20 on both sides of the opening 22 being exposed. Referring to FIG. 1C, the conventional lithographic etching technique is used to continue etching the oxide layer 16 exposed in the opening 22, so that the opening 22 further exposes the isolation layer 18 and the oxide layer 20 exposed by the photoresist layer 24 is etched A part of the oxide layer 20 on both sides of the opening 22 is formed to form an opening 26 and 28 respectively, and the isolation layer 18 is exposed respectively. The opening 28 further includes an opening 22 exposed. Next, the photoresist layer 24 is removed using, for example, an oxygen plasma method. Then, for example, using a sputtering method or a chemical vapor deposition method, a conductor layer 30 is formed and is inserted into the openings 22 and 28, contacts the conductor layer 14, and is inserted into the opening 26. Then, the subsequent steps are performed to complete the manufacture of the dual metal damascene. However, this subsequent process can be easily completed by those skilled in the art, so it will not be repeated here. However, in this subsequent process, the photoresist and lithography steps are required twice, so the process is more complicated, and the phenomenon of in-focus is easy to occur. Therefore, the main purpose of the present invention is to provide a method for manufacturing a dual metal damascene, which only requires the photoresist and lithography steps to be used once, so the manufacturing process is simple and the phenomenon of inaccurate focusing does not occur. 4 This paper size applies to the national standard (CNS) A4 specification (2 丨 〇297297 mm) ~ ----: ------ meal ------, order ------ 0 (Please read the precautions on the back before filling out this page) 2866twf.doc / 005 A7 B7 Printed by the Central Bureau of Standardization, Shellfish Consumer Cooperative, V. Description of the invention (彡) According to the purpose of the present invention, a double metal inlay is proposed The manufacturing method includes forming an oxide layer with a protruding portion covering the conductive layer on the substrate, and the protruding portion corresponds to the conductive layer. Next, an isolation layer is formed to cover the oxide layer. Then, the protruding portion is removed, for example, using a chemical mechanical honing method to form an opening, where the opening corresponds to the conductor layer. And, perform other subsequent steps. Therefore, the method of the present invention can save the photoresist and lithography steps once compared to the conventional technique, and the manufacturing process is simpler. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIGS. 1A to 1C FIG. 2 is a cross-sectional view showing a manufacturing process of a conventional double metal inlay; and FIGS. 2A to 2C are cross-sectional views showing a manufacturing process of a double metal inlay according to a preferred embodiment of the present invention. Description of icons: 10, 50: substrate 12, 52: inner metal dielectric layer 14 '30, 53, 54, 68: conductor layer 16, 20, 56, 60: oxide layer 18, 58: isolation layer 21, 24 , 62: Photoresist layer 22 '26, 28, 59, 64: Opening 5 This paper size is applicable to China National Standard (CNS) A4 specification (2 丨 0X297) " ----.------ ^ Equipment ------ Order ------ Silk (Please read the precautions on the back before filling in this page) 2866twf.doc / 〇〇5 A7 B7 V. Description of the invention ("/ ·" 57, 61 : Examples of protrusions, and FIGS. 2A to 2C are cross-sectional views showing a manufacturing process of a dual metal inlay according to a preferred embodiment of the present invention. Referring to FIG. 2A, a substrate 50 is provided. The substrate 50 has conductor layers 54 and 53 formed thereon. The conductive layer 54 is used for coupling to other structures (not shown) on the substrate 50 to be conducted. In addition, the conductive layer 54 and the inner metal dielectric layer 52 are formed to prevent other conductive structures of the conductive layer 54 from being conducted, and improper conduction is generated at a position that is not preset to be conductive. Among them, the width of the conductor layer 54 is wide, and the width of the conductor layer 53 is narrow. Next, for example, a high density plasma (High Density Plasma; HDP) chemical vapor deposition method is used to form an oxide layer 56 to cover the conductor layers 53 and 54. Because the high-density plasma chemical vapor deposition method has a unique chamfering phenomenon during the deposition process, better protruding portions 57 and 61 will be generated. Among them, the position of the protruding portion 58 corresponds to the conductive layer 54, and the position of the protruding portion 57 corresponds to the conductive layer 53. Also, since the width of the conductor layer 54 is larger than the conductor layer 53, the protrusion height of the protrusion portion 61 is greater than the protrusion height of the protrusion portion 57. Then, for example, a low-pressure chemical vapor deposition method is used to form an isolation layer 58 covering the oxide layer 56, wherein the material of the isolation layer 58 is, for example, silicon nitride or silicon oxynitride. Wherein, the isolation layer 58 will fluctuate with the surface of the oxide layer 56, and the raised portion of the isolation layer 58 corresponds to the protruding portions 57 and 6. Then, for example, chemical mechanical honing (Chemical Mechanical 6 paper size) Applicable to the Chinese National Standard (CNS) six 4 grids (210 × 297 mm) ---------- ^ ------, 1T ------ M (Please read the precautions on the back first (Fill in this page again.) Printed by the Central Standards Bureau of the Ministry of Education, Printed by the Shellfish Consumer Cooperatives ^ 2866twf.doc / 005 A7 B7 Printed by the Central Standards Bureau of the Ministry of Economy, Printed by the Shellfish Consumer Cooperatives.

Polishing ; CMP)法，去除對應於突起部份61之隔離層58， 以形成開口 59暴露出氧化層56。因爲，突起部份57的高 度不高，所以此硏磨步驟並不會去除對應於突起部份57 之隔離層58。並且，使得殘留的隔離層58與暴露出的氧 化層56，大約位於同一高度。然後，例如使用低壓化學氣 相沉積法，形成一層氧化層60覆蓋隔離層58與暴露出的 氧化層56。 本發明之特徵即是使用化學機械硏磨法，去除對應於 突起部份59之隔離層58，以形成開口 59，因此可以比習 知技藝省一次上光阻及微影步驟。並且，當導體層54與 導體層54之間，同時具有較高的突起部份與較低的突起 部份時。此硏磨步驟只會使得較高的突起部份形成開口’ 而不會在較少的突起部份上形成開口。故，在後續步驟中 沉積另一導體層時，即可以避免此導體層與下方的導體層 產生不適當的導通。 上一光阻層62定義氧化層60，此光阻層62暴露出對 應於開口 59之氧化層60。並且此光阻層62所暴露出之區 域約大於開口 59,因此也會暴露出開口 59兩側之隔離層 58。然後，使用傳統的微影蝕刻技術，蝕刻氧化層60，用 以形成開口 64,其中更包括進一步往下鈾刻開口 59暴露 出之氧化層56，使得開口 59進一步暴露出導體層54。 然後，例如使用濺鍍法或化學氣相沉積法’形成一導 體層68塡入開口 59中接觸導體層54，並覆蓋開口 64所 暴露出的隔離層58。其中，導體層68之材質例如爲鎢’ 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） —.—<------裝— (請先閱讀背面之注意事項再填寫本頁) 訂 绍 2866twf.d〇c/005 A7 B7 ------ - 五、發明説明（A ) 或其他導電材料。 接著，進行後續步驟以完成雙重金屬鐵嵌之製造。然 而此後續製程非關於本發明之特徵，故此處不再贅述。 因此，本發明的特徵包括使用高密度電漿化學氣相沉 積法與電漿增益化學氣相沉積法形成氧化層56，然後形成 隔離層58，藉以產生突起部份57。接著，以化學機械硏 磨法，去除隔離層58較大突起之部份，用以形成開口 59。 因此可以比習知技藝省一次上光阻及微影步驟，所以製程 比習知技藝更簡單。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 I.--^------^------.1T------if (請先閱讀背面之注意事項再填寫本頁) 經满部中决標率局貝工消費合作社印掣 8 本紙張尺度適用中國國家標準（CNS ) A4規格（2!〇X297公釐）Polishing; CMP) method, removing the isolation layer 58 corresponding to the protruding portion 61 to form an opening 59 to expose the oxide layer 56. Since the height of the protruding portion 57 is not high, the honing step does not remove the isolation layer 58 corresponding to the protruding portion 57. In addition, the remaining isolation layer 58 and the exposed oxidation layer 56 are positioned at approximately the same height. Then, for example, using a low-pressure chemical vapor deposition method, an oxide layer 60 is formed to cover the isolation layer 58 and the exposed oxide layer 56. A feature of the present invention is to use a chemical mechanical honing method to remove the isolation layer 58 corresponding to the protruding portion 59 to form the opening 59, so that the photoresist and lithography steps can be saved in one step compared with the conventional technique. Also, when the conductor layer 54 and the conductor layer 54 have both a high protrusion portion and a lower protrusion portion at the same time. This honing step will only allow openings to be formed on the higher protrusions and will not form openings on the fewer protrusions. Therefore, when another conductor layer is deposited in a subsequent step, it is possible to avoid an inappropriate conduction between this conductor layer and the underlying conductor layer. The last photoresist layer 62 defines an oxide layer 60. This photoresist layer 62 exposes the oxide layer 60 corresponding to the opening 59. And the area exposed by the photoresist layer 62 is larger than the opening 59, so the isolation layers 58 on both sides of the opening 59 are also exposed. Then, the conventional lithographic etching technique is used to etch the oxide layer 60 to form an opening 64, which further includes an oxide layer 56 exposed further down the uranium etched opening 59, so that the opening 59 further exposes the conductor layer 54. Then, for example, a sputtering method or a chemical vapor deposition method is used to form a conductive layer 68 which is inserted into the opening 59 to contact the conductive layer 54 and covers the isolation layer 58 exposed by the opening 64. Among them, the material of the conductor layer 68 is, for example, tungsten. 7 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) —.— < ------ install— (Please read the precautions on the back first Fill out this page again) Order 2866twf.d〇c / 005 A7 B7 -------V. Description of Invention (A) or other conductive materials. Then, the subsequent steps are performed to complete the manufacturing of the double metal iron insert. However, this subsequent process is not related to the features of the present invention, so it will not be repeated here. Therefore, the features of the present invention include forming an oxide layer 56 using a high-density plasma chemical vapor deposition method and a plasma gain chemical vapor deposition method, and then forming an isolation layer 58 to generate the protruding portion 57. Next, the large protruding portion of the isolation layer 58 is removed by a chemical mechanical honing method to form an opening 59. Therefore, the photoresist and lithography steps can be saved once compared to the conventional technique, so the process is simpler than the conventional technique. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. I .-- ^ ------ ^ ------. 1T ------ if (Please read the precautions on the back before filling in this page) Consumption Cooperative Press 8 This paper size applies to China National Standard (CNS) A4 (2! 〇X297mm)

Claims (1)

2866twf.doc/〇〇5 C8 ___ D8 穴、申请專利範圍 1.—種雙重金屬鑲嵌之製造方法，包括： fe供一基底，該基底上形成有複數個第一導體層； 形成一第一氧化層覆蓋該些第〜導體層與該基底，該 第一氧化層具有一較高突起部份與一較低突起部份分別對 應於該些第一導體層； ' 形成一隔離層覆蓋該第一热化層，藉以使得該隔離層 之形狀分別對應於該較高突起部份與一較低突起部份； 去除對應於該較高突起部份之該隔離層，以形成一第 一開口暴露出該第一氧化層，該第一開口對應於該些第一 導體層之一； 形成一第二氧化層覆蓋形成有該第一開口之該隔離 層； 定義該第二氧化層與第一氧化層，用以形成一第二開 口暴露出該第一開口，和該些第一導體層中的該第一導體 層；以及 形成一第二導體層於該第一開口與第二開口中接觸暴 露出之該第一導體層。 經濟部中央標率局貝工消費合作社印装 tn 1^1 H· -^ϋ · ί nn ml ml ^ Jr • 0¾ 、言 (請先閲讀背面之注意事項再填寫本頁) 2. 如申請專利範圍第1項所述之雙重金屬鑲嵌之製造 方法，其中形成該第一氧化層的方法，包括高密度電發化1 學氣相沉積法。 3. 如申請專利範圍第1項所述之雙重金屬鑲哮之製^ 方法，其中該隔離層之材質包括氮化矽。 4. 如申請專利範圍第1項所述之雙重金屬鑲嵌之製造 方法，其中去除對應於該較高突起部份之該隔離層的方 9 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 2 8 6 61 w f :/005 Λ8 B8 C8 D8 六、申請專利範圍 法’包括化學機械硏磨法。 5. 如申請專利範圍第1項所述之雙重金屬鑲嵌之製造 方法’其中定義該第二氧化層與第一氧化層的方法，包括 —一--------- -- (請先閲讀背面之注意事項再填寫本頁) 微影蝕刻法。 6. 如申請專利範圍第1項所述之雙重金屬鑲嵌之製造 方法’其中去除對應於該較高突起部份之該隔離層的步驟 中’更包括保留對應於該較低突起部份之該隔離層。 7. —種雙重金屬鑲嵌之製造方法，包括： 提供一基底，該基底上形成有複數個第一導體層； 依序形成具有一較高突起部份與較低突起部份之一第 一氧化層與隔離層覆蓋該些第一導體層，該些較高與較低 突起部份分別對應於該些第一導體層； 去除該隔離層之該較高突起部份，以形成一第一開口 暴露出該第一氧化層，該第一開口對應於該些第一導體層 之一； 形成一第二氧化層覆蓋該形成有該開口之隔離層； 經濟部中央標準局貝工消費合作社印装 定義該第二氧化層與第一氧化層，用以形成一第二開 口暴露出該第一開口，和該些第一導體層之該第一導體 層；以及 形成一第二導體層於該第一開口與第二開口中接觸暴 露出之該第一導體層。 8. 如申請專利範圍第7項所述之雙重金屬鑲嵌之製造 方法’其中形成該第一氧化層的方法，包括高密度電漿化 學氣相沉積法。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐〉 經濟部中央標準局員工消費合作社印製 Λ8 2866twf.doc/005 B8 C8 D8 六、申請專利範圍 9. 如申請專利範圍第7項所述之雙重金屬鑲嵌之製造 方法'，其中形成該第一氧化層的方法，包括電漿增益化學 氣相沉積法。 10. 如申請專利範圍第7項所述之雙重金屬鑲嵌之製造 方法，其中該隔離層之材質包括氮化矽。 11. 如申請專利範圍第7項所述之雙重金屬鑲嵌之製造 方法，其中去除該隔離層之該較高突起部份的方法，包括 化學機械硏磨法。 12. 如申請專利範圍第7項所述之雙重金屬鑲嵌之製造 方法，其中定義該第二氧化層與第一氧化層的方法，包括 微影蝕刻法。 13. 如申請專利範圍第7項所述之雙重金屬鑲嵌之製造 方法，其中去除該隔離層之該較高突起部份的步驟中，更 包括保留該隔離層之該較低突起部份。 14. 如申請專利範圍第7項所述之雙重金屬鑲嵌之製造 方法，其中該第二導體層係選自於鎢、銅與鋁等金屬所組 成之族群。 15. 如申請專利範圍第7項所述之雙重金屬鑲嵌之製造 方法，其中形成該第二導體層的方法包括化學氣相沉積 法。 n #n —^1 I * nn n^i m ^^1 T« (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）2866twf.doc / 〇〇5 C8 ___ D8 cavity, patent application scope 1. A method for manufacturing a double metal inlay, including: a substrate for a substrate, a plurality of first conductor layers formed on the substrate; forming a first oxide The first oxide layer has a higher protrusion portion and a lower protrusion portion corresponding to the first conductor layers, respectively, to form the isolation layer covering the first conductive layer and the substrate. The heating layer, so that the shape of the isolation layer corresponds to the higher protruding portion and a lower protruding portion, respectively; the isolation layer corresponding to the higher protruding portion is removed to form a first opening exposed The first oxide layer, the first opening corresponding to one of the first conductor layers; forming a second oxide layer covering the isolation layer formed with the first opening; defining the second oxide layer and the first oxide layer For forming a second opening to expose the first opening and the first conductor layer in the first conductor layers; and forming a second conductor layer to be exposed in contact with the first opening and the second opening The first conductor Floor. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, tn 1 ^ 1 H ·-^ ϋ · ί nn ml ml ^ Jr • 0¾, words (please read the precautions on the back before filling this page) 2. If you apply for a patent The method for manufacturing a dual metal damascene according to item 1 of the scope, wherein the method for forming the first oxide layer includes a high-density electrochemical method and a vapor deposition method. 3. The method for manufacturing a dual metal insert as described in item 1 of the scope of the patent application, wherein the material of the isolation layer includes silicon nitride. 4. The manufacturing method of the double metal inlay as described in item 1 of the scope of the patent application, wherein the square corresponding to the higher protruding part of the isolation layer is removed. Mm) 2 8 6 61 wf: / 005 Λ8 B8 C8 D8 6. The scope of patent application method includes chemical mechanical honing method. 5. The manufacturing method of the dual metal inlay as described in item 1 of the scope of the patent application, wherein the method of defining the second oxide layer and the first oxide layer includes------------(please (Read the precautions on the back before filling out this page) Lithography. 6. The manufacturing method of the dual metal inlay as described in item 1 of the scope of the patent application, wherein the step of removing the isolation layer corresponding to the higher protruding portion includes further retaining the Isolation layer. 7. A method for manufacturing a dual metal inlay, comprising: providing a substrate on which a plurality of first conductor layers are formed; and sequentially forming a first oxide having a higher protrusion portion and a lower protrusion portion Layers and isolation layers cover the first conductor layers, and the higher and lower protrusions correspond to the first conductor layers, respectively; the higher protrusions of the isolation layer are removed to form a first opening The first oxide layer is exposed, and the first opening corresponds to one of the first conductor layers; a second oxide layer is formed to cover the isolation layer in which the opening is formed; printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The second oxide layer and the first oxide layer are defined for forming a second opening to expose the first opening, and the first conductor layers of the first conductor layers; and forming a second conductor layer on the first conductor layer. An opening is in contact with the first conductor layer exposed in the second opening. 8. The method for manufacturing a dual metal damascene according to item 7 of the scope of the patent application, wherein the method for forming the first oxide layer includes a high-density plasma chemical vapor deposition method. This paper size applies to Chinese National Standard (CNS) Α4 specifications (210 × 297 mm) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs Λ8 2866twf.doc / 005 B8 C8 D8 6. Scope of patent application 9. If item 7 of the scope of patent application The method of manufacturing a dual metal damascene, wherein the method of forming the first oxide layer includes a plasma gain chemical vapor deposition method. 10. The manufacturing method of the dual metal damascene described in item 7 of the scope of patent application, The material of the isolation layer includes silicon nitride. 11. The manufacturing method of the dual metal inlay as described in item 7 of the patent application scope, wherein the method of removing the higher protruding portion of the isolation layer includes chemical mechanical honing 12. The method for manufacturing a dual metal damascene as described in item 7 of the scope of patent application, wherein the method of defining the second oxide layer and the first oxide layer includes lithography etching method. 13. As the scope of patent application scope 7 The method of manufacturing a dual metal inlay as described in the item, wherein the step of removing the higher protruding portion of the isolation layer further includes retaining the lower portion of the isolation layer. 14. The manufacturing method of the dual metal inlay as described in item 7 of the scope of patent application, wherein the second conductor layer is selected from the group consisting of metals such as tungsten, copper and aluminum. 15. If applying for a patent The method for manufacturing a dual metal damascene according to item 7 of the scope, wherein the method for forming the second conductor layer includes a chemical vapor deposition method. N #n — ^ 1 I * nn n ^ im ^^ 1 T «(please first Read the notes on the reverse side and fill out this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm)
TW87106840A 1998-05-04 1998-05-04 Method of manufacturing dual damascence TW379416B (en)

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Application Number Priority Date Filing Date Title
TW87106840A TW379416B (en) 1998-05-04 1998-05-04 Method of manufacturing dual damascence
DE1998136379 DE19836379A1 (en) 1998-05-04 1998-08-11 Manufacturing process using the double damascene process
JP10228796A JP2969109B1 (en) 1998-05-04 1998-08-13 Method of manufacturing semiconductor device using double wave pattern process
FR9810540A FR2778268A1 (en) 1998-05-04 1998-08-19 Double inlay process for forming interconnections especially in multi-level ICs

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