CN211350636U - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN211350636U CN211350636U CN202020247738.9U CN202020247738U CN211350636U CN 211350636 U CN211350636 U CN 211350636U CN 202020247738 U CN202020247738 U CN 202020247738U CN 211350636 U CN211350636 U CN 211350636U
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Abstract
The utility model provides a semiconductor device, including substrate, second interlaminar dielectric layer, electrically conductive interconnection line and the hard mask layer that is formed with first interlaminar dielectric layer, wherein, it has at least one electrically conductive plug to inlay in the first interlaminar dielectric layer, second interlaminar dielectric layer cover in on the first interlaminar dielectric layer, just be formed with a plurality of runs through in the second interlaminar dielectric layer the second slot of second interlaminar dielectric layer, and at least part second slot expose correspondingly the top of electrically conductive plug, electrically conductive interconnection line is filled in the second slot and with corresponding the top of electrically conductive plug contacts, the hard mask layer covers the second slot is peripheral on the second interlaminar dielectric layer to it is adjacent to separate between the top of electrically conductive interconnection line. The scheme can effectively control the gap width between the formed conductive interconnection lines through the hard mask layer accurately and effectively, and the problem of bridging of the conductive interconnection lines is avoided.
Description
Technical Field
The utility model relates to an integrated circuit makes technical field, in particular to semiconductor device.
Background
In Back End of Line (BEOL) of a semiconductor device, several layers of metal interconnection lines and contact plugs connecting the metal interconnection lines of different layers need to be formed above a semiconductor device layer to lead out electrodes of the semiconductor device. With the continuous development of semiconductor technology, the Critical Dimension (CD) of semiconductor devices is continuously shrinking, metal interconnection lines are becoming thinner and thinner, and gaps between the metal interconnection lines are becoming smaller and smaller. When a photoresist used for defining a metal interconnection line is exposed, if a photoresist line is relatively thin and an area of a light-transmitting area around the photoresist line is relatively large, due to limitation of a lithography limit of a lithography machine, the actually exposed photoresist line may be distorted (e.g., line shrinkage (shrink) occurs to become thin and thin, and bridging (bridge) occurs at the top of a photoresist opening), and a metal interconnection line formed based on the exposed photoresist pattern may have bridging (bridge) and other problems.
Specifically, the process of forming a layer of metal interconnection line in the existing back-end process is as follows:
first, referring to fig. 1A, an etching stop layer 102, a second interlayer dielectric layer 103, and a hard mask layer 104 are sequentially formed on a first interlayer dielectric layer 100 having a lower conductive plug 101, and a patterned photoresist layer 105 is formed on the surface of the hard mask layer 104 through photoresist layer coating, exposure, development, and other photolithography processes, wherein the patterned photoresist layer 105 has an opening 105b for defining a position and a line width of a metal interconnection line to be formed and a photoresist line 105a for defining a position and a line width of a gap between the metal interconnection lines to be formed, and the opening 105b is aligned with the lower conductive plug 101. When the line width of the opening 105b required after exposure is greater than the line width of the required photoresist line 105a, the lithography limit of the lithography machine may cause some actually exposed photoresist lines 105a to shrink (shrink, that is, the line width and height of the actually obtained photoresist line 105a are respectively smaller than the line width and height after ideal exposure), and at this time, the opening 105b around the shrunk photoresist line 105a may have a bridging (i.e., top connection) phenomenon.
Next, referring to fig. 1B, the hard mask layer 104 is etched by using the patterned photoresist layer 105 as a mask to transfer the pattern in the photoresist layer 105 to the hard mask layer 104, and then the photoresist layer 105 may be removed, at this time, the problem of the pattern in the photoresist layer 105 is transferred to the hard mask layer 104, which causes the problems of shrinkage of the corresponding line 104a in the hard mask layer 104 and bridging of the corresponding opening, and the problems in the hard mask layer 104 are even more serious than those in the photoresist layer 105 due to the existence of process errors.
Then, referring to fig. 1C, the hard mask layer 104 is used as a mask to continue etching downward by self-aligned (self-aligned) etching until the surface of the contact plug 101 in the first interlayer dielectric layer 100 is exposed, so as to form a corresponding trench 103 b. At this time, since the pattern in the hard mask layer 104 has the problems of line shrinkage and opening bridging, when the pattern in the hard mask layer 104 is transferred into the second interlayer dielectric layer 103, it is likely that the second interlayer dielectric layer 103 is unnecessarily damaged, and the problem of line 103a shrinkage is generated, thereby bridging the formed trench 103 b.
Referring to fig. 1D and 1E, the metal 106 is filled into the trench 103b through electroplating, deposition, and other processes until the metal 106 fills the trench 103b, and Chemical Mechanical Polishing (CMP) is performed on the filled metal 106 to planarize the top surface thereof, so that the hard mask layer 104 is removed together until the top of the interlayer dielectric layer 103 is exposed, thereby forming a metal interconnection line 106a isolated by the interlayer dielectric layer 103. At this time, since the heights of the tops of the sidewalls of some of the trenches 103b in the second interlayer dielectric layer 103 are reduced, the line widths and heights of the interlayer dielectric layers 103 between the metal interconnection lines 106a are too small, so that bridging problems 106b (as shown in fig. 1E and 1F) may occur between the metal interconnection lines 106a, which may have a fatal influence on the product performance.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a semiconductor device to solve the problem of bridging between the electrically conductive interconnect line.
In order to solve the above technical problem, the utility model provides a semiconductor device, include:
the device comprises a substrate, a first interlayer dielectric layer and a second interlayer dielectric layer, wherein at least one conductive plug is embedded in the first interlayer dielectric layer;
the second interlayer dielectric layer covers the first interlayer dielectric layer, a plurality of second grooves penetrating through the second interlayer dielectric layer are formed in the second interlayer dielectric layer, and at least part of the second grooves are exposed out of the tops of the corresponding conductive plugs;
conductive interconnection lines filled in the second trenches and contacting tops of the respective conductive plugs;
and the hard mask layer covers the second interlayer dielectric layer on the periphery of the second groove and separates the tops of the adjacent conductive interconnection lines.
Optionally, a top of the hard mask layer is flush with a top of the conductive interconnect line.
Optionally, a diffusion barrier layer is further disposed between the second trench and the conductive interconnection line.
Optionally, an etching stop layer is further disposed between the second interlayer dielectric layer and the first interlayer dielectric layer.
Optionally, the compactness of the etching stop layer is higher than that of the first interlayer dielectric layer and that of the second interlayer dielectric layer.
Optionally, the material of the etch stop layer includes at least one of silicon carbide, and silicon nitride doped with nitrogen.
Optionally, the materials of the first interlayer dielectric layer and the second interlayer dielectric layer respectively include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-K dielectric with a dielectric constant K lower than 3.9.
Optionally, the material of the conductive interconnection line includes at least one of tungsten, aluminum, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, copper, polysilicon, and metal silicide.
Optionally, the material of the hard mask layer includes at least one of tantalum, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten nitride, silicon nitride, and silicon oxynitride.
Compared with the prior art, the technical scheme of the utility model following beneficial effect has:
1. the utility model discloses a semiconductor device, including substrate, second interlaminar dielectric layer, electrically conductive interconnect and the hard mask layer that is formed with first interlaminar dielectric layer, wherein, it has at least one electrically conductive plug to inlay in the first interlaminar dielectric layer, second interlaminar dielectric layer cover in on the first interlaminar dielectric layer, just be formed with a plurality of running through in the second interlaminar dielectric layer the second slot of second interlaminar dielectric layer, and at least part second slot expose correspondingly the top of electrically conductive plug, electrically conductive interconnect fills in the second slot and with corresponding the top of electrically conductive plug contacts, the hard mask layer covers the second slot is peripheral on the second interlaminar dielectric layer to will be adjacent separate between the top of electrically conductive interconnect. The scheme can effectively control the gap width between the formed conductive interconnection lines through the hard mask layer accurately and effectively, and the problem of bridging of the conductive interconnection lines is avoided.
2. The technical scheme of the utility model simple, easy to carry out, and can improve the performance and the yield of product.
Drawings
Fig. 1A to fig. 1E are schematic cross-sectional views of a device structure during a process of forming a metal interconnection line in a conventional back-end process.
FIG. 1F is a scanning electron micrograph of the metal interconnect bridging corresponding to FIG. 1E.
Fig. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Fig. 3A to 3G are schematic cross-sectional views of device structures in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
The technical solution provided by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention. The meaning of "and/or" herein is either or both.
Referring to fig. 2, an embodiment of the present invention provides a semiconductor device, including: a substrate (not shown), a first interlevel dielectric layer 300, a second interlevel dielectric layer 303, conductive interconnect lines 307a, and a hard mask layer 305 a.
The substrate may be a front-end-of-line (FEOL) finished substrate, which may be at least one of the following mentioned materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. An isolation structure may be formed in the substrate, the isolation structure being a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. Electronic components (not shown), such as transistors (NMOS and/or PMOS), resistors, capacitors, diodes, transistors, and the like, may also be formed in the substrate.
The first interlayer dielectric layer 300 is formed on a substrate, and at least one conductive plug 301 is embedded in the first interlayer dielectric layer 300. The conductive plugs 301 may be formed by a contact hole etching and filling process, and each conductive plug 301 may be in electrical contact with an electrode of a corresponding electronic component in the substrate. The material of the first interlayer dielectric layer 300 may include, but is not limited to, silicon oxide (SiO)2) Silicon nitride (SiN), silicon oxynitride (SiON), low-K dielectric with a dielectric constant K lower than 3.9, Fluorinated Silicate Glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and the like, and the top surface of the first interlayer dielectric layer 300 is flat. The material of the conductive plug 301 is preferably tungsten metal, and may be aluminum metal, copper metal, or the like. And the top surface of the first interlayer dielectric layer 300 is flat, and the conductive plug301 is flush with the top surface of the first interlevel dielectric layer 300.
A second interlayer dielectric layer 303 covers the first interlayer dielectric layer 300, and a plurality of second trenches (306 in fig. 3E) are formed in the second interlayer dielectric layer 303, and at least a portion of the second trenches expose tops of the corresponding conductive plugs 301 in the first interlayer dielectric layer 300. The material of the second interlayer dielectric layer 303 may include, but is not limited to, silicon oxide (SiO)2) Silicon nitride (SiN), silicon oxynitride (SiON), low-K dielectrics, Fluorinated Silicate Glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and the like. The thickness of the second interlayer dielectric layer 303 may be made according to the thickness of the conductive interconnection line 307a, for example, 500nm to 2000 nm.
A hard mask layer 305a covers the second interlayer dielectric layer 303 at the periphery of the second trench and separates the tops of the adjacent conductive interconnection lines 307 a. And the top of the hard mask layer 305a is flush with the top of the conductive interconnect line 307 a. The material of the hard mask layer 305a may include, but is not limited to, at least one of tantalum, tantalum nitride, titanium nitride, zirconium titanium nitride, tungsten nitride, silicon oxynitride, and the like.
Optionally, an etching stop layer 302 is further interposed between the first interlayer dielectric layer 300 and the second interlayer dielectric layer 303, and compactness of the etching stop layer 302 is higher than that of the first interlayer dielectric layer 300 and the second interlayer dielectric layer 303. Further optionally, the material of the etch stop layer 302 includes at least one of silicon oxycarbide, silicon nitride, and silicon oxynitride.
Optionally, a diffusion barrier layer is further disposed between the second trench and the conductive interconnection line 307a, and a material of the diffusion barrier layer may be a material of a metal or a metal compound layer, such as tantalum, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten nitride, an alloy thereof, or a composition thereof. In addition, the diffusion barrier layer may also include multiple layers.
Referring to fig. 3A to 3G, the present embodiment further provides a method for manufacturing the semiconductor device, including the following steps:
s1, providing a substrate, wherein a first interlayer dielectric layer is formed on the substrate, at least one conductive plug is embedded in the first interlayer dielectric layer, and a second interlayer dielectric layer covers the first interlayer dielectric layer;
s2, forming a patterned photoresist layer on the second interlayer dielectric layer, wherein the patterned photoresist layer has a plurality of photoresist lines and photoresist openings between adjacent photoresist lines;
s3, etching and removing the second interlayer dielectric layer with partial thickness by taking the patterned photoresist layer as a mask so as to form a first groove in the second interlayer dielectric layer;
s4, removing the patterned photoresist layer and forming a hard mask layer filling the first trench;
s5, with the hard mask layer as a mask, etching the second interlayer dielectric layer until the top of the conductive plug in the first interlayer dielectric layer is exposed to form a second groove; and the number of the first and second groups,
and S6, filling a conductive material in the second trench and performing top planarization on the conductive material to form a conductive interconnection line in contact with the top of the corresponding conductive plug.
Referring to fig. 3A, in step S1, a substrate (not shown) is first provided, wherein the substrate may be a front-end-of-line (FEOL) substrate, which may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. An isolation structure may be formed in the substrate, the isolation structure being a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. The substrate may also have electronic elements formed thereinDevices (not shown), such as transistors (NMOS and/or PMOS), resistors, capacitors, diodes, transistors, and the like. The substrate is also provided with a first interlayer dielectric layer 300, the first interlayer dielectric layer 300 is provided with at least one conductive plug 301, the conductive plug 301 can be formed through a contact hole etching and filling process, and each conductive plug 301 can be electrically contacted with an electrode of a corresponding electronic element in the substrate. In other embodiments of the present invention, there may be a lower conductive interconnection line (not shown) formed by the method for manufacturing a conductive interconnection line of the present invention and a conductive plug located above the lower conductive interconnection line in the first interlayer dielectric layer 300, and the conductive plug may be formed by a damascene process. The material of the first interlayer dielectric layer 300 may include, but is not limited to, silicon oxide (SiO)2) Silicon nitride (SiN), silicon oxynitride (SiON), low-K dielectric with a dielectric constant K lower than 3.9, Fluorinated Silicate Glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and the like, and the top surface of the first interlayer dielectric layer 300 is flat. The material of the conductive plug 301 is preferably tungsten metal, and may be aluminum metal, copper metal, or the like. And the top surface of the conductive plug 301 is flush with the top surface of the first interlayer dielectric layer 300.
With continued reference to fig. 3A, in step S1, an etching stop layer 302 may be covered on the first interlayer dielectric layer 300 and the conductive plug 301 by using a chemical vapor deposition process or an atomic layer deposition process, the material of the etching stop layer 302 may include, but is not limited to, at least one of silicon carbide (SiCN), silicon carbide (SiC), and silicon nitride (SiN), preferably, the compactness of the etching stop layer 302 is higher than that of the first interlayer dielectric layer 300 and the second interlayer dielectric layer 303, the etching stop layer 302 may serve as an etching stop point for subsequently etching the second interlayer dielectric layer 303 to form the second trench, and protects the underlying first interlayer dielectric layer 300 and the conductive plug 301 from being damaged by etching during the etching process, and on the other hand, after the subsequent formation of the conductive interconnection line, the material in the conductive interconnection line, such as a metal interconnection line, can be prevented from diffusing into the underlying first interlayer dielectric layer 300.
Please refer to fig. 3A, whereinIn step S1, a second interlayer dielectric layer 303 may then be covered on the etch stop layer 302 by using a chemical vapor deposition process or a spin coating process, wherein the material of the second interlayer dielectric layer 303 may include, but is not limited to, silicon oxide (SiO)2) Silicon nitride (SiN), silicon oxynitride (SiON), low-K dielectrics, Fluorinated Silicate Glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and the like. The thickness of the second interlayer dielectric layer 303 may be made according to the thickness of the conductive interconnection line to be formed, for example, 500nm to 2000 nm. When the conductive interconnection lines with the same thickness are formed, the thickness of the second interlayer dielectric layer 303 is thicker than that of the second interlayer dielectric layer 103 in fig. 1A, for example, the thickness of the second interlayer dielectric layer 303 may be equal to the sum of the thicknesses of the hard mask layer 104 and the second interlayer dielectric layer 103 in fig. 1A.
With continued reference to fig. 3A, in step S2, a patterned photoresist layer 304 is formed on the surface of the second interlayer dielectric layer 303, wherein the pattern of the patterned photoresist layer 304 is complementary to the pattern of the patterned photoresist layer 105 in fig. 1A. The patterned photoresist layer 304 has a plurality of photoresist lines 304a and photoresist openings 304b located between adjacent photoresist lines 304a, where the photoresist lines 304a are used to define the position and size of a conductive interconnection line to be formed, and at least a portion of the photoresist lines 304a are aligned with corresponding conductive plugs 301, the photoresist openings 304b are used to define the position and size of a gap between adjacent conductive interconnection lines, and the line width of the photoresist lines 304a is greater than the line width of the photoresist openings 304b, for example, the line width of the photoresist lines 304a is 1.5-5 times the line width of the photoresist openings 304 b. The thickness of the photoresist layer 304 is determined by the process requirements for forming the first trench by subsequently etching the second interlayer dielectric layer 303, for example, 500nm to 5000 nm. In this embodiment, the step of forming the patterned photoresist layer 304 on the second interlayer dielectric layer 303 includes: the method for forming the patterned photoresist layer 304 includes the steps of coating a negative photoresist material on the second interlayer dielectric layer 303 by using a spin coating process, and exposing and developing the negative photoresist material by using a first photomask to form the patterned photoresist layer 304, wherein areas of the photoresist layer 304 and areas of the photoresist layer 105 which are removed by development are just exchanged, and although an exposed area and a shielding area are the same as those of the patterned photoresist layer 105, the photoresist layer 304 is made of the negative photoresist material, so that the problem that a developed photoresist line is not shrunk to become thinner and thinner, that is, the problem of top bridging of the photoresist opening 304b is not caused. In another embodiment, the step of forming the patterned photoresist layer 304 on the second interlayer dielectric layer 303 comprises: coating a positive photoresist material on the second interlayer dielectric layer 303, and exposing and developing the positive photoresist material by using a second photomask complementary to the first photomask to form the patterned photoresist layer 304, wherein the areas of the photoresist layer 304 and the photoresist layer 105 exposed and shielded by the photomask are just exchanged, and the area of the exposed area is relatively large and the area of the shielded area is relatively small, so that the problem of thinning and thinning of the actually exposed photoresist lines, namely the problem of top bridging of the photoresist opening 304b, is solved. In order to enhance the exposure of the photoresist layer 304, a film structure such as a bottom anti-reflection layer (not shown) may be formed on the second interlayer dielectric layer 303 before the photoresist material corresponding to the photoresist layer 304 is coated on the second interlayer dielectric layer 303.
Referring to fig. 3A and 3B, in step S3, the patterned photoresist layer 304 is used as a mask, and a corresponding dry etching process is used to etch a portion of the thickness of the second interlayer dielectric layer 303, so as to form a first trench 303B in the second interlayer dielectric layer 303, where the depth of the first trench 303B depends on the thickness of a hard mask layer to be formed subsequently. Since the shapes and line widths of the photoresist lines 304a and the photoresist openings 304b in the patterned photoresist layer 304 can be ensured in step S2, in this step, the patterned photoresist layer 304 is used as a mask, and only a part of the thickness of the second interlayer dielectric layer 303 is etched, so that the lateral etching of the second interlayer dielectric layer 303 can be reduced, and further the vertical or approximately vertical etching is realized, thereby enabling the sidewalls of the formed first trenches 303b to be vertical or approximately vertical (for example, the included angle between the sidewalls and the bottom surface is between 80 degrees and 100 degrees). At this time, the second interlayer dielectric layer 303 sandwiched between the adjacent first trenches 303b protrudes from the bottom surfaces of the first trenches 303b to form lines 303 a.
Referring to fig. 3B, 3C and 3D, in step S4, first, the patterned photoresist layer 304 may be removed by a dry stripping and/or a wet stripping process. Then, a hard mask material 305 is coated on the surfaces of the second interlayer dielectric layer 303 and each of the first trenches 303b by any suitable process, such as electroplating, electroless plating or vapor deposition, and the hard mask material 305 at least fills each of the first trenches 303 b. Next, a Chemical Mechanical Polishing (CMP) process may be used to perform a chemical mechanical polishing (i.e., chemical mechanical planarization) on the top of the hard mask material 305 until the top of the second interlayer dielectric layer 303 is exposed, or even to continue to thin the second interlayer dielectric layer 303 to a certain extent, so as to form the hard mask layer 305a in the first trench 303 b. At this time, since the morphology, the line width, and the like of the first trench 303B meet requirements, the required hard mask layer 305a can be effectively retained after the material filling and the CMP process, that is, the morphology and the line width of the formed hard mask layer 305a meet requirements, and the problem in the hard mask layer 104 shown in fig. 1B does not occur. The hard mask material 305 may include, but is not limited to, at least one of tantalum, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten nitride, silicon oxynitride, and the like.
Referring to fig. 3E, in step S5, the hard mask layer 305a is used as a mask, and the second interlayer dielectric layer 303 is etched by using a corresponding dry etching process (e.g., plasma etching, deep reactive ion etching, etc.) until the top surface of the corresponding conductive plug 301 is exposed, so as to form a second trench 306. Because the shape, line width, thickness and the like of the hard mask layer 305a meet requirements, in the process of etching the second interlayer dielectric layer 303 to form the second trench 306 by using the hard mask layer 305a as a mask, the lateral etching of the second interlayer dielectric layer 303 can be reduced, the shrinkage of the second interlayer dielectric layer 303 below the hard mask layer 305a is avoided, and the bridging problem between the adjacent second trenches 306 is further avoided. At this time, each of the second trenches 306 sequentially penetrates through the second interlayer dielectric layer 303 and the etch stop layer 302.
Referring to fig. 3E to fig. 3G, in step S6, a thin diffusion barrier layer (not shown) may be formed in the second trench 306 and filled with the conductive material 307 by any suitable process such as electroplating, electroless plating or vapor deposition, wherein the material of the diffusion barrier layer may be a metal or a metal compound layer, such as tantalum, tantalum nitride, titanium nitride, zirconium titanium nitride, tungsten nitride, an alloy thereof or a composition thereof. In addition, the diffusion barrier layer may also include a plurality of layers, the conductive material layer 307 fills the second trench 306, and the conductive material layer 307 may include, but is not limited to, one or more of tungsten, aluminum, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, copper, polysilicon, metal silicide, and the like. Then, a Chemical Mechanical Polishing (CMP) process may be used to planarize the top of the conductive material 307 until the top of the hard mask layer 305a is exposed, as shown in fig. 3G, to form a conductive interconnect line 307a filled in the second trench 306 and having a top level with the top of the hard mask layer 305a, at which time the top of the conductive interconnect line 307a is level with the top of the hard mask layer 305 a.
The method for manufacturing a semiconductor device according to this embodiment can form an embedded hard mask layer in the second interlayer dielectric layer, and the hard mask layer can precisely and effectively define a gap between adjacent conductive interconnection lines, so that the second interlayer dielectric layer between adjacent first trenches can be removed under the masking effect of the hard mask layer to form a second trench, and a conductive material is filled in the second trench and the top of the second trench is planarized to obtain a corresponding conductive interconnection line meeting requirements. And the process method is simple and convenient to implement.
To sum up, the technical scheme of the utility model can be effectively through keeping the hard mask layer, accurate and control the gap width between the electrically conductive interconnect line effectively to avoided the problem of electrically conductive interconnection lines bridging, simple process, easy to carry out, and can improve the performance and the yield of product.
The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.
Claims (9)
1. A semiconductor device, comprising:
the device comprises a substrate, a first interlayer dielectric layer and a second interlayer dielectric layer, wherein at least one conductive plug is embedded in the first interlayer dielectric layer;
the second interlayer dielectric layer covers the first interlayer dielectric layer, a plurality of second grooves penetrating through the second interlayer dielectric layer are formed in the second interlayer dielectric layer, and at least part of the second grooves are exposed out of the tops of the corresponding conductive plugs;
conductive interconnection lines filled in the second trenches and contacting tops of the respective conductive plugs;
and the hard mask layer covers the second interlayer dielectric layer on the periphery of the second groove and separates the tops of the adjacent conductive interconnection lines.
2. The semiconductor device of claim 1, wherein a top of the hardmask layer is flush with a top of the conductive interconnect line.
3. The semiconductor device of claim 1, wherein a diffusion barrier layer is further disposed between the second trench and the conductive interconnect line.
4. The semiconductor device according to claim 1, wherein an etch stop layer is further provided between the second interlayer dielectric layer and the first interlayer dielectric layer.
5. The semiconductor device of claim 4, wherein the etch stop layer is more dense than the first interlayer dielectric layer and the second interlayer dielectric layer.
6. The semiconductor device according to claim 4, wherein a material of the etch stop layer comprises at least one of nitrogen-doped silicon carbide, and silicon nitride.
7. The semiconductor device according to claim 1, wherein materials of the first interlayer dielectric layer and the second interlayer dielectric layer respectively include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-K dielectric having a dielectric constant K of less than 3.9.
8. The semiconductor device of claim 1, wherein a material of the conductive interconnect line comprises at least one of tungsten, aluminum, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, copper, polysilicon, metal silicide.
9. The semiconductor device of claim 1, wherein a material of the hard mask layer comprises at least one of tantalum, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten nitride, silicon nitride, and silicon oxynitride.
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| CN113192892A (en) * | 2021-04-23 | 2021-07-30 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113192892A (en) * | 2021-04-23 | 2021-07-30 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN113192892B (en) * | 2021-04-23 | 2022-03-08 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
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