CN108447796A - A kind of semiconductor chip structure parameters analysis method - Google Patents
A kind of semiconductor chip structure parameters analysis method Download PDFInfo
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- CN108447796A CN108447796A CN201810209068.9A CN201810209068A CN108447796A CN 108447796 A CN108447796 A CN 108447796A CN 201810209068 A CN201810209068 A CN 201810209068A CN 108447796 A CN108447796 A CN 108447796A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Abstract
The invention discloses a kind of semiconductor chip structure parameters analysis methods, including：It determines mounting material used in semiconductor chip, using acquisition modes corresponding with the mounting material, the consistent semiconductor chip of at least two layout informations is obtained from device；Lateral de-layer is carried out to the first semiconductor chip at least two semiconductor chips that get, and identifies each layer structural information, obtains the transversary information of the first semiconductor chip；Longitudinal profile making is carried out to the second semiconductor chip at least two semiconductor chips that get, and identifies and obtains the vertical structure information of the second semiconductor chip；According to transversary information and vertical structure information, the structural parameters of semiconductor chip are determined.The structural parameters that the domain structure and chip longitudinal direction of every layer of chip can be obtained through the invention provide Technical Reference for chip failure analysis, structural analysis and chip design.
Description
Technical field
The invention belongs to component reliability technical field more particularly to a kind of semiconductor chip structure Parameter analysis sides
Method.
Background technology
Semiconductor chip structure parameter acquiring is to realize super large-scale integration reliability evaluation, failure analysis and collection
The basis identified at circuit layout.
The failure analysis that integrated circuit can be greatly improved based on semiconductor chip structure parameter is horizontal, since super large is advised
Single transistor size is minimum inside vlsi die, and often chip interior metallization is multilayered structure, current failure point
Analysis means basically can not be accurately positioned the specific invalid position of such device, by obtaining semiconductor chip structure ginseng
Number, the micro-structure of device inside can accurately be shown, foundation is provided for failure analysis defect location.
Raising that can be strong based on semiconductor chip structure parameter is horizontal to the reliability evaluation of integrated circuit.Partly leading
Carry out analysis on the basis of body chip structure parameter, device critical structure and key parameter, such as single transistor can be obtained
The information such as gate oxide thickness, transistor feature size, inter-level dielectric quality, tungsten thru-hole quality, enrich structural analysis
Means and Essential Elements Of Analysis can provide basis for IC reliability appraisal, while can be set for semiconductor circuit chip
Meter provides reference and data supporting.
Invention content
The technology of the present invention solves the problems, such as：Overcome the deficiencies of the prior art and provide a kind of semiconductor chip structure parameter point
Analysis method can obtain the structural parameters of the domain structure and chip longitudinal direction of every layer of chip, for chip failure analysis, structural analysis
It is designed with chip and Technical Reference is provided.
In order to solve the above-mentioned technical problem, the invention discloses a kind of semiconductor chip structure parameters analysis methods, including：
Determine mounting material used in semiconductor chip, using acquisition modes corresponding with the mounting material, from
The consistent semiconductor chip of at least two layout informations is obtained in device；
Lateral de-layer is carried out to the first semiconductor chip at least two semiconductor chips that get, and identifies each layer
Structural information obtains the transversary information of the first semiconductor chip；
Longitudinal profile making is carried out to the second semiconductor chip at least two semiconductor chips that get, and is identified
Obtain the vertical structure information of the second semiconductor chip；
According to transversary information and vertical structure information, the structural parameters of semiconductor chip are determined.
In above-mentioned semiconductor chip structure parameters analysis method, material is installed used in the determining semiconductor chip
Material obtains that at least two layout informations are consistent partly to lead using acquisition modes corresponding with the mounting material from device
Body chip, including：
When it is to have definite melting point material to determine mounting material used in semiconductor chip, using physical heating method from device
The consistent semiconductor chip of at least two layout informations is obtained in part；
When it is corrodible material to determine mounting material used in semiconductor chip, using fuming nitric aicd etch or nothing
Water ethylenediamine etch obtains the consistent semiconductor chip of at least two layout informations from device.
In above-mentioned semiconductor chip structure parameters analysis method, in described pair of at least two semiconductor chips got
The first semiconductor chip carry out lateral de-layer, and identify each layer structural information, obtain the transversary of the first semiconductor chip
Information, including：
Step 11, the passivation layer of first semiconductor chip is removed using physical etchings method, exposure obtains current gold
Categoryization layer, and identify current metal layer structural parameters；
Step 12, the current metal layer is removed using chemical corrosion method, exposure obtains next layer；
Step 13, if next layer is polycrystal layer, identification obtains the structural parameters of polycrystal layer；
Step 14, if next layer is metal layer, identification obtains next layer of structural parameters, and return to step 12.
In above-mentioned semiconductor chip structure parameters analysis method, in described pair of at least two semiconductor chips got
The second semiconductor chip carry out longitudinal profile making, and identify obtain the vertical structure information of the second semiconductor chip, including：
Cross-wise direction along the second semiconductor chip is ground and polishes to second semiconductor chip；
Section is carried out to the second semiconductor chip after grinding and polishing treatment and eats acid and section dyeing processing, and is identified
To the vertical structure information of the second semiconductor chip.
In above-mentioned semiconductor chip structure parameters analysis method, the structural parameters of the semiconductor chip, including：
Transistor classification, size and position, metal-oxide-semiconductor classification, size and position, resistance size and position, capacitor size and
Position, inductor size and position, multiple-layer metallization interconnection architecture, PN junction doping depth, passivation layer thickness, gate oxide thickness,
Metallization thickness, polycrystalline layer thickness.
The present invention has the following advantages：
The invention discloses a kind of semiconductor chip structure parameters analysis methods, and half is obtained based on physics, chemical method
Conductor chip domain and structural parameters, this method can obtain the structural parameters of the domain structure and chip longitudinal direction of every layer of chip,
Technical Reference is provided for chip failure analysis, structural analysis and chip design.
Description of the drawings
Fig. 1 is a kind of step flow chart of semiconductor chip structure parameters analysis method in the embodiment of the present invention.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to disclosed by the invention
Embodiment is described in further detail.
Referring to Fig.1, a kind of step flow of semiconductor chip structure parameters analysis method in the embodiment of the present invention is shown
Figure.In the present embodiment, the semiconductor chip structure parameters analysis method, including：
Step 101, mounting material used in semiconductor chip is determined, using acquisition corresponding with the mounting material
Mode obtains the consistent semiconductor chip of at least two layout informations from device.
In the present embodiment, chip (semiconductor chip) is obtained from device refers to：Chip is taken out from packaging body
Method can choose following several methods and obtain chip according to the different mounting means of semiconductor chip：
(1) when it is to have definite melting point material to determine mounting material used in semiconductor chip, using physical heating method
The consistent semiconductor chip of at least two layout informations is obtained from device.
Preferably, physical heating method refers to directly heating to make its fusing to semiconductor chip mounting material, to make partly to lead
Body chip is detached with fixing body, and is removed chip using Mechanical Method.This method is suitable for having the installation material for being relatively fixed fusing point
Material, such as PbSn solders should avoid causing mechanical damage to chip when taking out chip using Mechanical Method.
(2) when it is corrodible material to determine mounting material used in semiconductor chip, using fuming nitric aicd etch
Or anhydrous ethylenediamine etch, the consistent semiconductor chip of at least two layout informations is obtained from device.
Preferably, fuming nitric aicd etch refers to using fuming nitric aicd directly etching semiconductor chip mounting material, to
The method for making semiconductor chip be detached with fixing body.This method is suitable for the chip that all can be corroded by fuming nitric aicd and installs material
Material, such as silver conductive adhesive.When corroding using fuming nitric aicd, fuming nitric aicd should be heated to 160 DEG C, and fuming nitric aicd is avoided to wave
Hair keeps fuming nitric aicd concentration.This method reaction speed is fast, efficient, but the metal that this method can be exposed to semiconductor chip
Before change causes to corrode, therefore use this method takes out semiconductor chip, semiconductor chip most surface layer information should be first obtained.
Preferably, anhydrous ethylenediamine etch refers to being corroded to chip mounting material using anhydrous ethylenediamine, makes half
The method that conductor chip is detached with fixing body.The chip mounting material that this method is suitable for by anhydrous ethylenediamine to be corroded, such as silver
Organic matter, part organic gel in conducting resinl etc., this method reflect that speed is slow, and efficiency is low, but not is caused to semiconductor chip
Damage.
Step 102, lateral de-layer is carried out to the first semiconductor chip at least two semiconductor chips that get, and
It identifies each layer structural information, obtains the transversary information of the first semiconductor chip.
In the present embodiment, it can be obtained by the following steps the transversary information of the first semiconductor chip：Step 11, it adopts
The passivation layer of first semiconductor chip is removed with physical etchings method, exposure obtains current metal layer, and identifies proper
The structural parameters of preceding metal layer；Step 12, the current metal layer is removed using chemical corrosion method, exposure obtains next
Layer；Step 13, if next layer is polycrystal layer, identification obtains the structural parameters of polycrystal layer；Step 14, if next layer is metallization
Layer, then identification obtain next layer of structural parameters, and return to step 12.
Preferably：
(1) depassivation layer
Using either physically or chemically removal semiconductor chip surface passivation layer.It is blunt for glass such as silica, silicon nitrides
Change layer, plasma etching method should be taken to remove, for organic matters such as polyimides, anhydrous ethylenediamine corrosion can be used and (or wait
Ion etching).
(2) semiconductor chip metallization structure parameter acquiring
After removing passivation layer, what is exposed is the domain structure on chip upper layer, at this point, using metallographic microscope and scanning
Electronic Speculum is checked and is analyzed to chip layout, and is taken a picture to domain structure, and the complete fabric chip of the layer, and base are obtained
In structure chart, analysis chip electrical structure and interconnecting relation obtain this layer of metallization structure parameter.
(3) metallization removal layer
The caustic solution coordinated using NaOH and phosphoric acid exposes understructure to removing chip metallization.NaOH solution
It is rapid with reactive aluminum, it is efficient, but NaOH can corrode polycrystalline, be suitable for chip upper metallization, phosphoric acid and reactive aluminum speed compared with
Slowly, efficiency is low, but phosphoric acid does not corrode chip polycrystal layer, will not destroy chip fabric.Therefore, except directly being connect with chip polycrystalline
Outside tactile metallization, it should be corroded using 17%NaOH solution, control solution temperature is room temperature, the gold being in direct contact with chip
Categoryization layer should use phosphoric acid corrosion, to ensure that chip bottom polycrystalline is injury-free.Wherein the chip metallization number of plies can pass through core
Piece vertical structure acquisition of information.
(4) chip polycrystal layer structural parameters obtain
After removing all coating metals and oxide layer, you can chip underlying polysilicon structure is obtained, it is aobvious using metallographic
Chip layout is identified and analyzed in micro mirror and scanning electron microscope, to determine the type and type of each transistor.
(5) chip netlist structural information obtains
It is obtained in structural parameters and position distribution relationship and multi-layer metallized structure information based on chip polycrystal layer
Electrical interconnection structure determines the connection relation between different crystal pipe, forms the netlist structural information of semiconductor chip.
Step 103, longitudinal profile system is carried out to the second semiconductor chip at least two semiconductor chips that get
Make, and identifies and obtain the vertical structure information of the second semiconductor chip.
In the present embodiment, the structural parameters of semiconductor chip can be determined as follows：Along the second semiconductor core
The cross-wise direction of piece is ground and polishes to second semiconductor chip；To the second semiconductor after grinding and polishing treatment
Chip carries out section and eats acid and section dyeing processing, and identifies and obtain the vertical structure information of the second semiconductor chip.
Preferably：
(1) semiconductor core slice lapping
Special chip fixture can be used semiconductor chip is fixed, semiconductor chip is indulged using 6 μm of mills
To grinding, speed of grinding plate is 60 revs/min, without applying pressure to semiconductor chip in process of lapping, to avoid semiconductor
Chip cracks, and dynamics maintains semiconductor chip vertical with mill, and semiconductor chip is milled to target location nearby i.e.
It can.
(2) semiconductor chip polishes
0.5 μm of polishing cloth is selected to be polished semiconductor chip, polishing is 0.03 μm of diamond polishing liquid auxiliary of addition
Grinding and polishing, speed of grinding plate are controlled at 50 revs/min, and without applying pressure to semiconductor chip in process of lapping, dynamics maintains half
Conductor chip is vertical with mill, and semiconductor chip is milled to target location by the step.Then to sample and polishing cloth
It is cleaned, and polishing fluid is changed to 0.01 μm of diamond polishing liquid, ANALYSIS OF CROSS SECTIONS FOR SEMICONDUCTOR CHIP is finely polished, it is smooth
Chip cross-section, speed of grinding plate still keeps 50 revs/min, and time control is in 1~2min.
(3) ANALYSIS OF CROSS SECTIONS FOR SEMICONDUCTOR CHIP eats acid
Using the mixed liquor (ratio 4 of hydrofluoric acid and ammonium fluoride:1) chip cross-section is impregnated, the time is in 10-20s, corruption
It is cleaned using clear water after the completion of erosion, then is observed after being cleaned using acetone.
(4) ANALYSIS OF CROSS SECTIONS FOR SEMICONDUCTOR CHIP dyes
Using hydrofluoric acid and nitric acid mixed liquor (ratio 1:1) immersion treatment is carried out, then time 5-10s uses clear water clear
It washes, then is cleaned using acetone.
(5) ANALYSIS OF CROSS SECTIONS FOR SEMICONDUCTOR CHIP structural parameters obtain
After being dyed to ANALYSIS OF CROSS SECTIONS FOR SEMICONDUCTOR CHIP, you can the structure and morphology for obtaining chip cross-section, using scanning electron microscope pair
Chip cross-section structure is observed and is measured, and passivation layer thickness, the metal layer number of plies, thickness, gate oxide thickness PN junction are obtained
The information such as depth, to obtain the vertical structure information of semiconductor.
Step 104, according to transversary information and vertical structure information, the structural parameters of semiconductor chip are determined.
In the present embodiment, the transversary information and vertical structure information of integrating semiconductor chip, you can analysis obtains
The structural information situation of semiconductor chip entirety, includes but are not limited to：Transistor classification, size and position, metal-oxide-semiconductor classification,
Size and position, resistance size and position, capacitor size and position, inductor size and position, multiple-layer metallization interconnection architecture, PN
Tie doping depth, passivation layer thickness, gate oxide thickness, metallization thickness, polycrystalline layer thickness.
On the basis of the above embodiments, it is illustrated with reference to a specific example.
It chooses certain type integrated circuit and carries out the horizontal and vertical structural information acquisition of semiconductor chip progress, to obtain semiconductor
The structural parameters situation of chip entirety：
(1) piece is taken
160 DEG C of boilings are carried out to device using concentrated nitric acid, die bonding material silver paste is corroded, individual semiconductor core is obtained
Piece.
(2) depassivation layer
The glass passivation layer that chip surface silica and silicon nitride meet is removed using plasma etching method.
(3) chip metallization layer structural parameters obtain
Chip surface entirety pattern is analyzed using metallographic microscope, obtains the metallized traces situation on chip surface layer
And interconnection information, and take a picture to chip pattern.
(4) metallization removal
Using the removal chip surface metallization of 17%NaOH solution, exposure chip lower layer oxide layer.
(5) oxide layer removes
Using the oxide layer of plasma etching method removal chip exposure.
(6) chip metallic intermediate layer structural parameters obtain
Chip metallic intermediate layer pattern is analyzed using metallographic microscope, obtains metallized traces situation and interconnection
Information, and take a picture to this layer of chip pattern.
(7) metallization removal
Chip underlying metal, exposure chip polysilicon layer are removed using phosphoric acid solution.
(8) chip polycrystal layer structural parameters obtain
Obtained chip polysilicon layer is observed and analyzed using metallographic microscope, determines the type of each transistor
And structure size, obtain the structural parameters information of this layer.
(9) chip longitudinal direction grinding and polishing
Chip is fixed using special chip fixture, chip is ground using 6 μm of mills, 60 revs/min of rotating speed is ground
It is milled at wherein one near metal-oxide-semiconductor, then uses 0.5 μm of polishing cloth to add 0.03 μm of diamond polishing liquid and be processed by shot blasting,
After chip exposes complete metal-oxide-semiconductor vertical structure, sample is cleaned, replaces 0.01 μm of diamond polishing liquid, polishing
2min。
(10) chip cross-section eats acid and dyeing
Using the mixed liquor (ratio 4 of hydrofluoric acid and ammonium fluoride:1) 15s is impregnated to chip cross-section, then uses clear water and third
Ketone cleans.
Using hydrofluoric acid and nitric acid mixed liquor (ratio 1:1) 10s is impregnated to chip cross-section, then uses clear water and acetone clear
It washes.
(11) chip cross-section structural information obtains
Observation analysis is carried out to chip cross-section using scanning electron microscope, and Each part is measured, obtains chip
Vertical structure information.
(12) chip overall structure information
The transversary information and vertical structure information of integrating semiconductor chip, you can obtain chip Global Information situation.
Each embodiment in this explanation is described in a progressive manner, the highlights of each of the examples are with its
The difference of his embodiment, the same or similar parts between the embodiments can be referred to each other.
The above, best specific implementation mode only of the invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.
The content that description in the present invention is not described in detail belongs to the known technology of professional and technical personnel in the field.
Claims (5)
1. a kind of semiconductor chip structure parameters analysis method, which is characterized in that including：
Mounting material used in semiconductor chip is determined, using acquisition modes corresponding with the mounting material, from device
It is middle to obtain the consistent semiconductor chip of at least two layout informations；
Lateral de-layer is carried out to the first semiconductor chip at least two semiconductor chips that get, and identifies each layer structure
Information obtains the transversary information of the first semiconductor chip；
Longitudinal profile making is carried out to the second semiconductor chip at least two semiconductor chips that get, and identifies and obtains
The vertical structure information of second semiconductor chip；
According to transversary information and vertical structure information, the structural parameters of semiconductor chip are determined.
2. semiconductor chip structure parameters analysis method according to claim 1, which is characterized in that the determining semiconductor
Mounting material used in chip obtains at least two using acquisition modes corresponding with the mounting material from device
The consistent semiconductor chip of layout information, including：
When it is to have definite melting point material to determine mounting material used in semiconductor chip, using physical heating method from device
Obtain the consistent semiconductor chip of at least two layout informations；
When it is corrodible material to determine mounting material used in semiconductor chip, using fuming nitric aicd etch or anhydrous second
Diamines etch obtains the consistent semiconductor chip of at least two layout informations from device.
3. semiconductor chip structure parameters analysis method according to claim 1, which is characterized in that described pair gets
The first semiconductor chip at least two semiconductor chips carries out lateral de-layer, and identifies each layer structural information, obtains first
The transversary information of semiconductor chip, including：
Step 11, the passivation layer of first semiconductor chip is removed using physical etchings method, exposure is currently metallized
Layer, and identify current metal layer structural parameters；
Step 12, the current metal layer is removed using chemical corrosion method, exposure obtains next layer；
Step 13, if next layer is polycrystal layer, identification obtains the structural parameters of polycrystal layer；
Step 14, if next layer is metal layer, identification obtains next layer of structural parameters, and return to step 12.
4. semiconductor chip structure parameters analysis method according to claim 1, which is characterized in that described pair gets
The second semiconductor chip at least two semiconductor chips carries out longitudinal profile making, and identifies and obtain the second semiconductor chip
Vertical structure information, including：
Cross-wise direction along the second semiconductor chip is ground and polishes to second semiconductor chip；
Section is carried out to the second semiconductor chip after grinding and polishing treatment and eats acid and section dyeing processing, and identifies and obtains the
The vertical structure information of two semiconductor chips.
5. semiconductor chip structure parameters analysis method according to claim 1, which is characterized in that the semiconductor chip
Structural parameters, including：
Transistor classification, size and position, metal-oxide-semiconductor classification, size and position, resistance size and position, capacitor size and position,
Inductor size and position, multiple-layer metallization interconnection architecture, PN junction doping depth, passivation layer thickness, gate oxide thickness, metallization
Thickness, polycrystalline layer thickness.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109444193A (en) * | 2018-09-13 | 2019-03-08 | 胜科纳米（苏州）有限公司 | The failure analysis method of semiconductor chip |
| CN111261533A (en) * | 2020-01-21 | 2020-06-09 | 宜特(上海)检测技术有限公司 | Method for taking chip by driving IC |
| CN111312609A (en) * | 2020-03-03 | 2020-06-19 | 胜科纳米（苏州）有限公司 | Method for measuring thickness of silicon epitaxial layer on silicon substrate |
| CN111653498A (en) * | 2020-06-12 | 2020-09-11 | 长江存储科技有限责任公司 | Semiconductor structure and grinding method thereof |
| CN113607511A (en) * | 2021-06-23 | 2021-11-05 | 北京芯可鉴科技有限公司 | Method for preparing power chip sample to be analyzed and power chip sample to be analyzed |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102072967A (en) * | 2010-12-14 | 2011-05-25 | 东南大学 | Gold-gold bonding process-based thermal type wind speed and direction sensor and preparation method thereof |
| CN102253325A (en) * | 2010-05-21 | 2011-11-23 | 中芯国际集成电路制造(上海)有限公司 | Method for analyzing chip failure |
| CN105047557A (en) * | 2015-09-10 | 2015-11-11 | 宜特(上海)检测技术有限公司 | High-order chip failure physical de-layering analysis method |
| CN105699149A (en) * | 2016-04-05 | 2016-06-22 | 工业和信息化部电子第五研究所 | Layer stripping method in chip failure analysis process |
| CN105699875A (en) * | 2016-01-15 | 2016-06-22 | 工业和信息化部电子第五研究所 | Method for detecting multilayer copper interconnected layout structure |
-
2018
- 2018-03-14 CN CN201810209068.9A patent/CN108447796A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102253325A (en) * | 2010-05-21 | 2011-11-23 | 中芯国际集成电路制造(上海)有限公司 | Method for analyzing chip failure |
| CN102072967A (en) * | 2010-12-14 | 2011-05-25 | 东南大学 | Gold-gold bonding process-based thermal type wind speed and direction sensor and preparation method thereof |
| CN105047557A (en) * | 2015-09-10 | 2015-11-11 | 宜特(上海)检测技术有限公司 | High-order chip failure physical de-layering analysis method |
| CN105699875A (en) * | 2016-01-15 | 2016-06-22 | 工业和信息化部电子第五研究所 | Method for detecting multilayer copper interconnected layout structure |
| CN105699149A (en) * | 2016-04-05 | 2016-06-22 | 工业和信息化部电子第五研究所 | Layer stripping method in chip failure analysis process |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109444193A (en) * | 2018-09-13 | 2019-03-08 | 胜科纳米（苏州）有限公司 | The failure analysis method of semiconductor chip |
| CN111261533A (en) * | 2020-01-21 | 2020-06-09 | 宜特(上海)检测技术有限公司 | Method for taking chip by driving IC |
| CN111261533B (en) * | 2020-01-21 | 2021-11-23 | 苏试宜特(上海)检测技术有限公司 | Method for taking chip by driving IC |
| CN111312609A (en) * | 2020-03-03 | 2020-06-19 | 胜科纳米（苏州）有限公司 | Method for measuring thickness of silicon epitaxial layer on silicon substrate |
| CN111653498A (en) * | 2020-06-12 | 2020-09-11 | 长江存储科技有限责任公司 | Semiconductor structure and grinding method thereof |
| CN113607511A (en) * | 2021-06-23 | 2021-11-05 | 北京芯可鉴科技有限公司 | Method for preparing power chip sample to be analyzed and power chip sample to be analyzed |
| CN113607511B (en) * | 2021-06-23 | 2023-12-08 | 北京芯可鉴科技有限公司 | Method for preparing power chip sample to be analyzed and power chip sample to be analyzed |
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Application publication date: 20180824 |