CN110836905A - Failure analysis method for automatically identifying physical defects of chip - Google Patents
Failure analysis method for automatically identifying physical defects of chip Download PDFInfo
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- CN110836905A CN110836905A CN201911107608.3A CN201911107608A CN110836905A CN 110836905 A CN110836905 A CN 110836905A CN 201911107608 A CN201911107608 A CN 201911107608A CN 110836905 A CN110836905 A CN 110836905A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/22—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material
- G01N23/225—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material using electron or ion
- G01N23/2251—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material using electron or ion using incident electron beams, e.g. scanning electron microscopy [SEM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N2223/00—Investigating materials by wave or particle radiation
- G01N2223/40—Imaging
- G01N2223/401—Imaging image processing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N2223/00—Investigating materials by wave or particle radiation
- G01N2223/40—Imaging
- G01N2223/402—Imaging mapping distribution of elements
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N2223/00—Investigating materials by wave or particle radiation
- G01N2223/40—Imaging
- G01N2223/426—Imaging image comparing, unknown with known substance
Abstract
The invention relates to a failure analysis method for automatically identifying physical defects of a chip, which relates to the failure analysis technology of a semiconductor integrated circuit.
Description
Technical Field
The invention relates to a semiconductor integrated circuit failure analysis technology, in particular to a failure analysis method for automatically identifying physical defects of a chip.
Background
With the development of semiconductor technology, the yield of chips is required to be higher and higher. The physical failure analysis of the integrated circuit chip is one of the methods for improving the yield of the semiconductor device.
At present, the general process of physical failure analysis of an integrated circuit chip comprises the steps of grinding and removing layers, observing and confirming a physical failure position by a scanning electron microscope layer by layer, and further analyzing a cross-section scanning electron microscope or a transmission electron microscope at the failure position. The physical failure position is confirmed by scanning electron microscope observation layer by layer, which is a key step in the method and determines the success or failure of the whole failure analysis. The traditional method is to manually and visually observe a scanning electron microscope image to find out the position of a physical defect. This method is inefficient because it takes a long time to observe the area with the naked human eye, and also depends strongly on the level of the engineer's observation ability and experience. With the shrinking feature size of integrated circuit chips, the critical defects are smaller and smaller, the defects are easy to be missed, the efficiency of traditional manual observation is gradually reduced, and the requirement on the capability of engineers is higher and higher.
Disclosure of Invention
The invention aims to provide a failure analysis method for automatically identifying the physical defects of a chip, which does not need manual visual observation, so that the efficiency is high and the accuracy is high.
The failure analysis method for automatically identifying the physical defects of the chip, provided by the invention, comprises the following steps of: s1: carrying out layer removal processing on the chip to a target layer and position; s2: controlling a scanning electron microscope to capture one or more photos at different positions in a target area at a target level; s3: extracting the outline picture from the picture captured by the scanning electron microscope in the step S2 through software and outputting the outline picture in a standard layout format to form a proposed layout; s4: finding out a corresponding part of the extracted layout in the step S3 in the complete chip original layout through graph comparison, and performing lamination processing to form a laminated layout; and S5: and automatically comparing and identifying the physical defect position of the laminated layout data, wherein the automatic comparison and identification comprises the following steps: rough identification: carrying out XOR operation on the laminated layout to generate a difference hot spot, simultaneously setting a threshold line width to eliminate noise, indicating that a physical defect exists at the position by the difference hot spot after the noise is eliminated, and feeding back the area with the physical defect to a scanning electron microscope picture for final confirmation; and accurately identifying: dividing the laminated layout into a plurality of regions, wherein each region is provided with only one equipotential line, respectively analyzing the number of the equipotential lines of the extracted layout and the original layout in each region, and judging that no physical defect exists if the extracted layout and the original layout are the same; and if the number of the equipotential lines is different, judging that the physical defects exist, and feeding back the areas with the physical defects to a scanning electron microscope picture for final confirmation.
Further, in step S1, the sem is controlled by software at the target level.
Further, the layout in the actual chip extracted in step S3 is only a small part of the layout of the actual chip.
Further, in step S5, the threshold line width is set according to the design rule of each layer of the chip.
Furthermore, the equipotential lines are lines which are at the same potential in the extracted layout and the original layout or the extracted layout and the original layout after power-on if the overlapped part of the lines in the extracted layout and the lines in the original layout in the laminated layout is electrically communicated.
Further, only one line in the original layout is included in one region divided by the overlay layout in step S5.
Further, only one line in the extracted layout is included in one region divided by the overlay layout in step S5.
Furthermore, in step S5, a region divided by the overlay layout only includes one line in the original layout and one line in the extracted layout, and the one line in the original layout and the one line in the extracted layout at least partially overlap.
Further, in step S5, the one region divided by the overlay layout includes only one line in the original layout and the first line and the second line in the extracted layout, and the one line in the original layout and the first line and the second line in the extracted layout are at least partially overlapped, respectively.
Further, in step S5, the one region divided by the overlay layout only includes the first line and the second line in the original layout and the line in the extracted layout, and the first line and the second line in the original layout and the line in the extracted layout respectively at least partially overlap.
Further, if there are two lines in the extracted layout and one line in the original layout in step S5, there is an open defect.
Further, in step S5, if there are two lines in the original layout and one line in the extracted layout, it indicates that there is a bridging defect.
Further, in step S5, if there is one line in the original layout and there are 0 equipotential lines in the extracted layout, it indicates that there is a missing pattern defect.
Further, in step S5, if there are 0 lines in the original layout and one line in the extracted layout, it indicates that there is a redundant defect.
Furthermore, the operations from step S1 to step S5 are repeated at different process levels to complete the layer-by-layer analysis of the entire chip.
According to the failure analysis method for automatically identifying the physical defects of the chip, provided by the invention, the image of the scanning electron microscope is captured, the captured image is subjected to layout extraction to form an extracted layout, the layout is searched, the extracted layout is found out in the complete original chip layout, the corresponding part is subjected to lamination processing to form a laminated layout, then the laminated layout is roughly identified, the laminated layout is accurately identified to finish the automatic identification of the physical defects, manual visual observation is not needed, and therefore, the efficiency is high and the accuracy is high.
Drawings
FIG. 1 is a schematic view of a scanning electron micrograph of a chip from delamination processing to target layer grabbing.
Fig. 2 is a schematic diagram of a layout photograph extracted from the scanning electron micrograph in fig. 1.
Fig. 3 is a schematic diagram of the extracted layout photos after the extracted layout photos find the corresponding positions in the original chip layout and are subjected to stacking processing.
Fig. 4a is a schematic diagram of hot spots generated by the direct XOR operation of fig. 3.
Fig. 4b is a schematic diagram of hot spots after noise elimination.
FIGS. 5a-5e are different embodiments of equipotential lines.
FIG. 6 is a diagram illustrating a result of automatically identifying physical defects of a chip according to an embodiment of the invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In an embodiment of the present invention, a failure analysis method for automatically identifying physical defects of a chip is provided, and specifically, the failure analysis method for automatically identifying physical defects of a chip includes:
s1: carrying out layer removal processing on the chip to a target layer and position;
s2: controlling a scanning electron microscope to capture one or more photos at different positions in a target area at a target level;
specifically, in an embodiment of the present invention, the scanning electron microscope is controlled at the target level by software. Specifically, referring to fig. 1, fig. 1 is a schematic view of a scanning electron micrograph of a chip from a layer removal process to a target layer capture, which is an example of a scanning electron micrograph including four metal lines.
S3: extracting the outline picture from the picture captured by the scanning electron microscope in the step S2 through software and outputting the outline picture in a standard layout format to form a proposed layout;
specifically, referring to fig. 2, fig. 2 is a schematic diagram of a layout photograph extracted from the sem photograph in fig. 1.
S4: finding out a corresponding part of the extracted layout in the step S3 in the complete chip original layout through graph comparison, and performing lamination processing to form a laminated layout;
specifically, in an embodiment of the present invention, the layout in the actual chip extracted in step S3 is only a small part of the actual chip layout, and it is necessary to find a corresponding position in the complete original chip layout and perform stacking processing.
Specifically, referring to fig. 3, fig. 3 is a schematic diagram of the extracted layout photo, which is obtained by finding a corresponding position in the original chip layout and performing lamination processing, where the area of the block 310 is the extracted layout and the area of the block 320 is the original chip layout.
S5: and automatically comparing and identifying the physical defect position of the laminated layout data, wherein the automatic comparison and identification comprises the following steps:
rough identification: carrying out XOR (exclusive OR) operation on the laminated layout to generate a difference hot spot, simultaneously setting a threshold line width to eliminate noise, indicating that a physical defect exists at the position by the difference hot spot after the noise is eliminated, and feeding back the area with the physical defect to a scanning electron microscope photo to carry out final confirmation;
specifically, referring to fig. 4a, fig. 4a is a schematic diagram of a hot spot generated by the direct XOR operation of fig. 3, such as a plurality of difference hot spots 410 generated in fig. 4a, fig. 4b is a schematic diagram of a hot spot after noise elimination, such as a schematic diagram of a hot spot after noise elimination, as shown in fig. 4b, there is no hot spot after noise processing, and a reasonable difference between an actual chip size and an original layout is caused in a manufacturing process of a chip due to a manufacturing process or a process, and the reasonable difference should not be considered as a defect, so a threshold line width needs to be set to eliminate noise, the reasonable difference is excluded as a risk of the defect, if there is a difference hot spot after noise elimination, the difference hot spot is a point with a physical defect, an area with the physical defect is fed back to a scanning electron microscope photograph for final confirmation, and the following accurate identification step is continued, and if there is no difference hot spot after noise, the precise identification step is also continued as described below.
Specifically, in an embodiment of the present invention, the threshold line width is set according to a design rule of each layer of the chip. Because the design rule of each layer is different, the threshold line width is different, and the threshold line width needs to be set correspondingly according to the design rule of each layer.
And (3) accurate identification: dividing the laminated layout into a plurality of regions, wherein each region is provided with only one equipotential line, respectively analyzing the number of the equipotential lines of the extracted layout and the original layout in each region, and judging that no physical defect exists if the extracted layout and the original layout are the same; and if the number of the equipotential lines is different, judging that the physical defects exist, and feeding back the areas with the physical defects to a scanning electron microscope picture for final confirmation.
In an embodiment of the invention, the equipotential lines are lines which are at the same potential in the extracted layout and the original layout after power-on if the part of the extracted layout in the laminated layout, which is overlapped with the lines in the original layout, is electrically communicated. In an embodiment of the present invention, referring to fig. 5a to 5e, fig. 5a to 5e are different embodiments of equipotential lines, and as shown in fig. 5a, one area divided by the overlay layout only includes one line 510 in the original layout, and if power is applied to the line 510, the potentials of the lines 510 are the same to form an equipotential line. As shown in fig. 5b, one region divided by the stacked layout includes only one line 520 in the extracted layout, and when electricity is applied to the line 520, the potentials of the respective parts of the line 520 are the same, thereby forming an equipotential line. As shown in fig. 5c, one region divided by the stacked layout only includes one line 510 in the original layout and one line 520 in the extracted layout, the line 510 and the line 520 are at least partially overlapped, and if power is applied to the line 510 and the line 520, the overlapped portions of the line 510 and the line 520 are electrically connected, so that the lines 510 and 520 have the same potential, and the lines 510 and 520 form an equipotential line. As shown in fig. 5d, one region divided by the overlay layout only includes one line 510 in the original layout and lines 521 and 522 in the extracted layout, the line 510 and the lines 521 and 522 are at least partially overlapped, respectively, and if power is supplied to the line 510 and the lines 521 and 522, the electric potentials of the line 510 and the lines 521 and 522 are the same, so that the line 510 and the lines 521 and 522 form an equipotential line. As shown in fig. 5e, one region divided by the overlay layout only includes lines 511 and 512 in the original layout and line 520 in the extracted layout, lines 511 and 512 at least partially overlap line 520, respectively, and if power is applied to lines 511 and 512 and line 520, the potentials of lines 511 and 512 and line 520 are the same, so that lines 511 and 512 and line 520 form an equipotential line.
Further, in an embodiment of the present invention, if there are two lines in the extracted layout and one line in the original layout, there is an open defect. As shown in fig. 5d, there is an open defect in lines 511 and 512.
Further, in an embodiment of the present invention, if there are two lines in the original layout and one line in the extracted layout, it indicates that there is a bridging defect. As shown in fig. 5e, there is a bridging defect between the lines 521 and 522.
Furthermore, in an embodiment of the present invention, if there is one line in the original layout and there are 0 equipotential lines in the extracted layout, it indicates that there is a missing pattern defect. As shown in fig. 5a, a pattern-missing defect exists.
Further, in an embodiment of the present invention, if there are 0 lines in the original layout and one line in the extracted layout, it indicates that there is a redundant pattern defect. As shown in fig. 5b, a redundant pattern defect exists.
Furthermore, in an embodiment of the present invention, if the original layout and the pick-up layout are the same line, it is determined that there is no physical defect. As shown in fig. 5 c.
Through the failure analysis method for automatically identifying the physical defects of the chip, the open defects 610 of the chip can be automatically identified according to the result schematic diagram of automatically identifying the physical defects of the chip shown in fig. 6.
Furthermore, in an embodiment of the present invention, the above operations are repeated at different process levels to complete layer-by-layer analysis of the whole chip.
In conclusion, the captured images are captured through the scanning electron microscope image, the captured images are subjected to layout extraction to form an extracted layout, the layout is searched, the extracted layout is subjected to corresponding part in the complete chip original layout and is subjected to lamination processing to form a laminated layout, then the laminated layout is roughly identified, the laminated layout is accurately identified, the physical defects are automatically identified, manual visual observation is not needed, and therefore efficiency is high and accuracy is high.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (15)
1. A failure analysis method for automatically identifying physical defects of a chip is characterized by comprising the following steps:
s1: carrying out layer removal processing on the chip to a target layer and position;
s2: controlling a scanning electron microscope to capture one or more photos at different positions in a target area at a target level;
s3: extracting the outline picture from the picture captured by the scanning electron microscope in the step S2 through software and outputting the outline picture in a standard layout format to form a proposed layout;
s4: finding out a corresponding part of the extracted layout in the step S3 in the complete chip original layout through graph comparison, and performing lamination processing to form a laminated layout; and
s5: and automatically comparing and identifying the physical defect position of the laminated layout data, wherein the automatic comparison and identification comprises the following steps:
rough identification: carrying out XOR operation on the laminated layout to generate a difference hot spot, simultaneously setting a threshold line width to eliminate noise, indicating that a physical defect exists at the position by the difference hot spot after the noise is eliminated, and feeding back the area with the physical defect to a scanning electron microscope picture for final confirmation; and
and (3) accurate identification: dividing the laminated layout into a plurality of regions, wherein each region is provided with only one equipotential line, respectively analyzing the number of the equipotential lines of the extracted layout and the original layout in each region, and judging that no physical defect exists if the extracted layout and the original layout are the same; and if the number of the equipotential lines is different, judging that the physical defects exist, and feeding back the areas with the physical defects to a scanning electron microscope picture for final confirmation.
2. The failure analysis method for automatically identifying the physical defects of the chip according to claim 1, wherein the scanning electron microscope is controlled at a target level by software in step S1.
3. The failure analysis method for automatically identifying physical defects of chips as claimed in claim 1, wherein the layout of the actual chip extracted in step S3 is only a small part of the layout of the actual chip.
4. The failure analysis method for automatically identifying physical defects of a chip as claimed in claim 1, wherein the threshold line width is set according to the design rule of each layer of the chip in step S5.
5. The failure analysis method for automatically identifying the physical defects of the chip according to claim 1, wherein the equipotential lines are lines which are at the same potential in the extracted layout and the original layout or the extracted layout and the original layout after power-on if the overlapped part of the lines in the extracted layout and the lines in the original layout in the laminated layout is electrically communicated.
6. The failure analysis method for automatically identifying the physical defects of the chip as claimed in claim 1, wherein the region divided by the overlay layout in step S5 includes only one line in the original layout.
7. The failure analysis method for automatically identifying the physical defects of the chip as claimed in claim 1, wherein the step S5 includes extracting only one line in the layout in a divided region of the overlay layout.
8. The failure analysis method for automatically identifying the physical defects of the chip as claimed in claim 1, wherein the region divided by the overlay layout in step S5 includes only one line in the original layout and one line in the extracted layout, and the one line in the original layout and the one line in the extracted layout at least partially overlap.
9. The failure analysis method for automatically identifying the physical defects of the chip as claimed in claim 1, wherein the region divided by the overlay layout in step S5 includes only one line in the original layout and the first line and the second line in the extracted layout, and the one line in the original layout and the first line and the second line in the extracted layout are at least partially overlapped.
10. The failure analysis method for automatically identifying the physical defects of the chip as claimed in claim 1, wherein the region divided by the overlay layout in step S5 only includes the first line and the second line in the original layout and the line in the extracted layout, and the first line and the second line in the original layout and the line in the extracted layout respectively at least partially overlap.
11. The failure analysis method for automatically identifying physical defects of chips as claimed in claim 1, wherein if there are two lines in the extracted layout and one line in the original layout, there is an open defect in step S5.
12. The failure analysis method for automatically identifying physical defects of chips as claimed in claim 1, wherein in step S5, if there are two lines in the original layout and one line in the extracted layout, it indicates that there is a bridging defect.
13. The failure analysis method for automatically identifying the physical defects of the chip as claimed in claim 1, wherein in step S5, if there is one line in the original layout and there are 0 equipotential lines in the extracted layout, it indicates that the missing pattern defect exists.
14. The failure analysis method for automatically identifying physical defects of chips as claimed in claim 1, wherein in step S5, if there are 0 lines in the original layout and one line in the extracted layout, it indicates that there is a redundant pattern defect.
15. The failure analysis method for automatically identifying physical defects of chips as claimed in claim 1, wherein the operations of steps S1 to S5 are repeated at different process levels to complete the layer-by-layer analysis of the whole chip.
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Application publication date: 20200225 |