CN109946586A - The detection method of chip electrical connection defect - Google Patents
The detection method of chip electrical connection defect Download PDFInfo
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- CN109946586A CN109946586A CN201910111599.9A CN201910111599A CN109946586A CN 109946586 A CN109946586 A CN 109946586A CN 201910111599 A CN201910111599 A CN 201910111599A CN 109946586 A CN109946586 A CN 109946586A
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- interconnection line
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Abstract
This application discloses a kind of detection methods of chip electrical connection defect.The described method includes: removal substrate, the end of the conductive channel for the lowest part level being connected with the active area on the exposure substrate；Using the first mode of electronic scanner microscope, since the conductive channel of lowest part level, the feature image of the conductive channel of the multiple level is obtained；Using the second mode of electronic scanner microscope, since the interconnection line of lowest part level, the feature image of the interconnection line of the multiple level is obtained；In the feature image of the conductive channel of the multiple level, according to the contrast of the end of different conductive channels, the defect location information of the interconnection line of subsequent level is obtained；And in the feature image of the interconnection line in the multiple level, according to the defect location INFORMATION DISCOVERY defective locations, wherein the operating voltage of the first mode is lower than the operating voltage of the second mode.The quick positioning of defective locations may be implemented in the detection method.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly, to the detection method of chip electrical connection defect.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With pattern characteristics
Critical dimension (critical dimension, be abbreviated as CD) is smaller and smaller, and the storage density of memory device is higher and higher.It is three-dimensional
Memory device includes the multiple storage units stacked along vertical direction, and collection can be doubled up on the chip of unit area
Cheng Du, and cost can be reduced.
In the inside of three-dimensional storage part, there is a large amount of electric connection structures, for providing the position of three-dimensional storage part
The conductive path of line, wordline, selection line and source electrode line etc., such as the conductive channel longitudinally extended and the interconnection line being laterally extended.
The failure of three-dimensional storage part may be caused due to the defect of active area, it is also possible to since the defect of electric connection structure causes.Cause
This, the importance of the failure analysis of three-dimensional storage part first is that chip electrical connection defect detection.
In the detection of chip electrical connection defect, can using low-light microtechnic (Emission Microscope) and
Photoinduction resistance variations technology (OBIRCH), determines defective locations by the variation of chip interior electric current under given voltage
Position.The detection method depends on complete current path.If the electric connection structure of chip interior disconnects, it is difficult to position defect
Position.Further improved method uses nano-probe platform, and with the both ends of 2 probe contact interconnection lines, pressurize the other end for one end
Whether there is or not disconnections to judge the interconnection line for ground connection.Alternatively, being directly directed through under high voltages by scanning electron microscope (SEM)
Whether surface layer viewing metal wire has disconnection.
However, above-mentioned detection method is difficult to meet the need of the failure analysis of the complicated electric connection structure of three-dimensional storage part
It asks, expects the detection method for being further improved chip electrical connection defect to improve detection efficiency and accuracy.
Summary of the invention
In view of the above problems, the purpose of the present invention is to provide a kind of detection methods of chip electrical connection defect, wherein adopts
Conductive channel layer and interconnection line layer are imaged respectively with the different mode of scanning electron microscope, to realize the quick of defective locations
Positioning.
According to an embodiment of the invention, providing a kind of detection method of chip electrical connection defect, the chip includes substrate
With the electric connection structure on substrate, the electric connection structure includes the conductive channel and many levels for many levels being connected to each other
Interconnection line, comprising: remove the substrate, the conduction for the lowest part level being connected with the active area on the exposure substrate is logical
The end in road；Using the first mode of electronic scanner microscope, since the conductive channel of lowest part level, obtain the multiple
The feature image of the conductive channel of level；Using the second mode of electronic scanner microscope, opened from the interconnection line of lowest part level
Begin, obtains the feature image of the interconnection line of the multiple level；In the feature image of the conductive channel of the multiple level, root
According to the contrast of the end of different conductive channels, the defect location information of the interconnection line of subsequent level is obtained；And the multiple
In the feature image of the interconnection line of level, according to the defect location INFORMATION DISCOVERY defective locations.
Preferably, the conductive channel of the multiple level and the interconnection line of the multiple level are alternately stacked, the multiple
The interconnection line of level is laterally extended, and the conductive channel of the multiple level longitudinally extends, the conductive channel of the multiple level and
The interconnection line of the multiple level is connected to each other, to form the conductive path of the active area.
Preferably, when obtaining the feature image of conductive channel of the multiple level, leading for corresponding level is removed in advance
Electric channel close to the substrate coating, with the end of the exposure conductive channel.
Preferably, when obtaining the feature image of interconnection line of the multiple level, the interconnection of corresponding level is removed in advance
Line close to the substrate coating, with the surface of the exposure interconnection line.
Preferably, the operating voltage of the first mode is 500V~5KV, and the operating voltage of the second mode is 5KV
~15KV.
Preferably, the operating voltage of the first mode is selected according to the contrast, so that in defect and normal conduction
The contrast of the end of conductive channel in path is greater than predetermined value.
Preferably, the operating voltage of the second mode is selected according to the spatial resolution of the pattern, so that in pattern
The shape characteristic of the interconnection line can be differentiated in image.
Preferably, the operating voltage of the first mode is lower than the operating voltage of the second mode.
Preferably, the spatial resolution for the feature image that the first mode obtains is lower than the shape that the second mode obtains
The spatial resolution of looks image
Electrical connection defect inspection method according to an embodiment of the present invention, after removal substrate and corresponding active area, from
The conductive channel of lower layer starts successively to obtain feature image.Low-work voltage mode using scanning electron microscope is to leading
Electric channel layer imaging, to obtain the contrast between defect and normal conductive channel, to provide the defect location letter of subsequent level
Breath.Interconnection line layer is imaged using the high working voltage mode of scanning electron microscope, to obtain the high resolution graphics of interconnection line
Picture further looks at accurate defective locations.When being applied to the three-dimensional storage part with labyrinth and large area, the core
The electrical connection defect inspection method of piece can quickly find defective locations, to improve detection efficiency, and can reduce difference
The superposition phenomenon of the metal line image of level, to improve detection accuracy.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows the schematic cross-section of exemplary chip internal structure.
Fig. 2 shows the schematic illustrations of electrical connection defect inspection method according to an embodiment of the present invention.
Fig. 3 a to 3f shows the schematic cross-section in electrical connection defect inspection method each stage according to an embodiment of the present invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
It is only capable of obtaining the testing result of contact position the inventors discovered that detecting electrical connection defect using nano-probe platform,
The spatial resolution of detection is limited by probe size, then needs multiple spot to detect the chip of large area, so as to cause inspection
Survey overlong time.Therefore, nano-probe platform is difficult to meet the large area detection demand of three-dimensional storage part.It is aobvious using scanning electron
The detection of micro mirror can obtain the pattern of area of visual field, and the feature image for successively observing chip can be found that defective locations.Scanning
The spatial resolution of electron microscope is related to operating voltage.Spatial resolution can be improved using high voltage, but due to electronics
Penetration depth is deeper, and the image superposition of the electric connection structure of different level causes to be difficult to differentiate defect characteristic.Therefore, using scanning
The feature image of electron microscope is difficult to meet the detection demand of the labyrinth of three-dimensional storage part.
Fig. 1 shows the schematic cross-section of exemplary chip internal structure.The chip structure will be used to illustrate according to this
The electrical connection defect inspection method of inventive embodiments.Actual chip structure is related to specific chip type, for example, three-dimensional is deposited
The chip of memory device has more complicated structure.However, the electric connection structure of different types of chip can apply basis
The electrical connection defect inspection method of the embodiment of the present invention.
As shown, chip 100 includes 101, two transistor T1 and T2 of semiconductor substrate and the binding that is electrically connected accordingly
Structure.
In chip 100, transistor T1 includes the source region 111 formed in semiconductor substrate 101, drain region 112, is partly being led
The lamination knot of the gate-dielectric 113 and grid conductor 114 between source region 111 and drain region 112 formed in body substrate 101
Structure, and the side wall 115 positioned at laminated construction two sides.Transistor T2 include the source region 121 formed in semiconductor substrate 101,
Drain region 122, the gate-dielectric 123 and grid between source region 121 and drain region 122 formed in semiconductor substrate 101
The rhythmic structure of the fence of conductor 124, and the side wall 125 positioned at laminated construction two sides.Interlayer insulating film 102 is covered on semiconductor lining
Above bottom 101 and rhythmic structure of the fence.
Further, the electric connection structure in chip 100 is respectively used to be connected to the source electrode 111 of transistor T1 and transistor
The conductive channel and interconnection line of the source electrode 121 of T2.Conductive channel and multiple layer of the electric connection structure for example including many levels
The interconnection line in face.Interconnection line is located on the interlayer insulating film 102-104 of different level, for being laterally extended for conductive path, leads
Electric channel passes through corresponding interlayer insulating film 102-104, and the longitudinal direction for conductive path extends, to connect the mutual of adjacent level
Line.Interlayer insulating film 105 is covered on the interconnection line of top.Although being not shown, can also be formed in interlayer insulating film 105
Additional pad, for providing being electrically connected between the electric connection structure of chip interior and external circuit.
As shown, the first conductive path that the source electrode 111 of transistor T1 is connected successively includes conductive channel 211, interconnection
Line 212, conductive channel 213, interconnection line 214, conductive channel 215 and interconnection line 216, the source electrode 121 of transistor T2 be connected the
Two conductive paths successively include conductive channel 221, interconnection line 222, conductive channel 223, interconnection line 224, conductive channel 225 and mutually
Line 226.The electrical connection defect of chip 100 is likely to be present in the conductive channel and interconnection line of any level.
Fig. 2 shows the schematic illustrations of electrical connection defect inspection method according to an embodiment of the present invention.For the sake of clarity,
The electric connection structure of chip 100 is only shown in figure, and corresponding interlayer insulating film is not shown.In this example it is assumed that first
The interconnection line 212 of conductive path disconnects.
The detection method includes the pretreatment to chip.Pretreatment removal substrate and corresponding active area, to expose
The conductive channel of lower layer.The detection method is since the conductive channel of lower layer, and level detects upper layer one by one
Interconnection line and conductive channel.In the detection method, using the different mode of scanning electron microscope respectively to conductive channel layer
It is imaged with interconnection line layer, to realize the quick positioning of defective locations.
For conductive channel layer, scanning electron microscope is shone using the operating voltage of 500V~5KV (such as 1KV)
It penetrates.Since operating voltage is lower, the spatial resolution of the feature image of conductive channel layer is accordingly lower.In the conductive path of disconnection
The positive charge of middle aggregation is more than the positive charge assembled in normal conductive path.Therefore, conductive channel is irradiated in electron beam 106
Exposed end when, in the conductive path of disconnection, conductive channel captures greater number of electronics, to generate lesser amount of
Secondary electron.The quantity of the secondary electron received in detection probe 107 is less, therefore, the exposed end of the conductive channel
Brightness of image is lower.In the feature image of low resolution, the contrast of more obvious conductive channel can be obtained, can be passed through
Bright at observation conductive channel secretly judges whether corresponding conductive path disconnects.As shown, leading in first conductive path
Brightness of the brightness of the exposed end of electric channel 211 lower than the exposed end of the conductive channel 221 in second conductive path.The step
Suddenly the defect location information of subsequent level, i.e., lacking there is disconnection in the interconnection line being connected with conductive channel 211 are provided
Fall into position.
For interconnection line layer, scanning electron microscope is irradiated using the operating voltage of 5KV~15K (such as 10KV).
Since the surface area of interconnection line is larger, also it is difficult to obtain the contrast of defect and normal interconnection line using low-work voltage.
It is used in this step compared with high working voltage, to obtain the feature image of high-resolution interconnection line layer.According in conductive channel
The location information obtained in the feature image of layer is further looked in the feature image of corresponding interconnection line layer and is accurately lacked
Fall into position.For example, it can be found that defective locations 311 in interconnection line 212 in first conductive path.
The detection method is successively obtained since the conductive channel of lower layer after removal substrate and corresponding active area
Obtain feature image.Using scanning electron microscope low-work voltage mode to conductive channel layer be imaged, with obtain defect with just
Contrast between normal conductive channel, to provide the defect location information of subsequent level.Using the senior engineer of scanning electron microscope
Make voltage mode interconnection line layer is imaged, to obtain the high-definition picture of interconnection line, further looks at accurate defective locations.
When being applied to the three-dimensional storage part with labyrinth and large area, the electrical connection defect inspection method of the chip can be fast
Speed discovery defective locations, to improve detection efficiency, and can reduce the superposition phenomenon of the metal line image of different level, from
And improve detection accuracy.
Fig. 3 a to 3f shows the schematic cross-section in electrical connection defect inspection method each stage according to an embodiment of the present invention.
In this example it is assumed that there are the defective locations disconnected in the interconnection line 212,214 and 246 of first conductive path.
The detection method starts from chip 100 shown in FIG. 1.
In step S01, chip 100 is pre-processed, is had using grinding removal substrate 101 and transistor T1 and T2
Source region.
Referring to Fig. 1, the first conductive path that the source electrode 111 of transistor T1 is connected successively includes conductive channel 211, interconnection line
212, conductive channel 213, interconnection line 214, conductive channel 215 and interconnection line 216, the source electrode 121 of transistor T2 be connected second
Conductive path successively includes conductive channel 221, interconnection line 222, conductive channel 223, interconnection line 224, conductive channel 225 and interconnection
Line 226.
After the active area of removal semiconductor substrate 101 and transistor T1 and T2, the conduction for exposing lower layer is logical
The end in road 211 and 221.
In step S02, scanning electron microscope obtains the conductive channel of lower layer using the operating voltage of such as 1KV
Feature image, as shown in Figure 3a.
The operating voltage is lower, and therefore, the spatial resolution of the feature image of conductive channel layer is accordingly lower.Conductive channel
211 and 221 are located in disconnection and normal conductive path, and the positive charge assembled in the conductive path of disconnection is than normal
The positive charge assembled in conductive path is more.When electron beam 106 irradiates the exposed end of conductive channel 211 and 221, conduction is logical
Greater number of electronics is captured than conductive channel 221 in road 211, thus generates lesser amount of secondary electron.In feature image,
The brightness of the brightness ratio conductive channel 221 of conductive channel 211 is smaller, according to contrast between the two, so that it may obtain subsequent layer
The defect location information in face, i.e., there is the defective locations of disconnection in the interconnection line being connected with conductive channel 211.
In step S03, interlayer insulating film 102 is removed using grinding, rhythmic structure of the fence and conductive channel therein are also together
Removal.
In step S04, scanning electron microscope obtains the interconnection of lower layer using the operating voltage of such as 5~10KV
The feature image of line, as shown in Figure 3b.
The operating voltage is higher, and therefore, the spatial resolution of the feature image of interconnection line layer is accordingly higher.Due to interconnection line
Surface area it is larger, therefore, even with low-work voltage also be difficult obtain defect and normal interconnection line contrast.According to
The location information obtained in the feature image of conductive channel layer further looks in the feature image of corresponding interconnection line layer
Accurate defective locations.For example, it can be found that defective locations 311 in interconnection line 212 in first conductive path.
Further, as shown in Fig. 3 c to 3f, step S01 to S04 is repeated, since the conductive channel of subsequent level successively
Obtain feature image.Using scanning electron microscope low-work voltage mode to conductive channel layer be imaged, with obtain defect with
Contrast between normal conductive channel, to provide the defect location information of subsequent level.Using the height of scanning electron microscope
Interconnection line layer is imaged in operating voltage mode, to obtain the high-definition picture of interconnection line, further looks at accurate defective bit
It sets.Therefore, it is possible to complete the detection of the conductive channel and interconnection line of structure at all levels.
In the above description, the technical details such as patterning, the etching of each layer are not described in detail.But
It is it will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition,
In order to form same structure, those skilled in the art be can be devised by and process as described above not fully identical side
Method.In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot have
It is used in combination sharply.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (9)
1. a kind of detection method of chip electrical connection defect, the chip includes the electric connection structure on substrate and substrate, described
Electric connection structure includes the conductive channel for many levels being connected to each other and the interconnection line of many levels, comprising:
The substrate is removed, the end of the conductive channel for the lowest part level being connected with the active area on the exposure substrate；
Using the first mode of electronic scanner microscope, since the conductive channel of lowest part level, the multiple level is obtained
Conductive channel feature image；
Using the second mode of electronic scanner microscope, since the interconnection line of lowest part level, the multiple level is obtained
The feature image of interconnection line；
In the feature image of the conductive channel of the multiple level, according to the contrast of the end of different conductive channels, obtain with
The defect location information of the interconnection line of level afterwards；And
In the feature image of the interconnection line of the multiple level, according to the defect location INFORMATION DISCOVERY defective locations.
2. detection method according to claim 1, wherein the conductive channel of the multiple level and the multiple level
Interconnection line is alternately stacked, and the interconnection line of the multiple level is laterally extended, and the conductive channel of the multiple level longitudinally extends, institute
The interconnection line of the conductive channel and the multiple level of stating many levels is connected to each other, to form the conductive path of the active area
Diameter.
3. detection method according to claim 2, when obtaining the feature image of conductive channel of the multiple level, in advance
Coating of the conductive channel close to the substrate of corresponding level is removed, first with the end of the exposure conductive channel.
4. detection method according to claim 2, when obtaining the feature image of interconnection line of the multiple level, in advance
Coating of the interconnection line close to the substrate of corresponding level is removed, with the surface of the exposure interconnection line.
5. detection method according to claim 1, wherein the operating voltage of the first mode is 500V~5KV, described
The operating voltage of second mode is 5KV~15KV.
6. detection method according to claim 1, wherein select the work electricity of the first mode according to the contrast
Pressure, so that the contrast of the end of the conductive channel in defect and normal conductive path is greater than predetermined value.
7. detection method according to claim 1, wherein select second mould according to the spatial resolution of the pattern
The operating voltage of formula, so that the shape characteristic of the interconnection line can be differentiated in feature image.
8. detection method according to claim 6 or 7, wherein the operating voltage of the first mode is than second mould
The operating voltage of formula is low.
9. detection method according to claim 8, wherein the spatial resolution for the feature image that the first mode obtains
Lower than the spatial resolution for the feature image that the second mode obtains.
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| CN116152252A (en) * | 2023-04-20 | 2023-05-23 | 长鑫存储技术有限公司 | Method and device for processing electron microscope image and computer readable storage medium |
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