CN110867391B - Defect detection method in chip manufacturing process - Google Patents
Defect detection method in chip manufacturing process Download PDFInfo
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- CN110867391B CN110867391B CN201911106653.7A CN201911106653A CN110867391B CN 110867391 B CN110867391 B CN 110867391B CN 201911106653 A CN201911106653 A CN 201911106653A CN 110867391 B CN110867391 B CN 110867391B
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Abstract
The invention relates to a defect detection method in the chip manufacturing process, which relates to a defect detection technology.A target detection image is obtained, a layout is searched, a corresponding part of the target detection image is found in a complete chip original layout and is subjected to lamination processing to form a laminated layout, then the laminated layout is divided into a plurality of regions, each region is provided with one or more equipotential lines, the target detection image and the original layout in each region are respectively subjected to equipotential line number analysis to carry out defect detection, the difficulty of defect detection is reduced, the efficiency is high, and the accuracy is high.
Description
Technical Field
The invention relates to a defect detection technology, in particular to a defect detection method in a chip manufacturing process.
Background
With the development of semiconductor technology, the yield of chips is required to be higher and higher. However, the integrated circuit chip manufacturing process is complex, and many defects are often generated in the manufacturing process, so the defect detection is a necessary process in the integrated circuit manufacturing process.
In the whole chip manufacturing process, the most central step is pattern transfer, namely, a design pattern on an original layout is transferred to a silicon wafer to form a target pattern, namely a final pattern. During the pattern transfer process, many interlayer patterns such as mask patterns, ADI (post exposure inspection) patterns, AEI (post etch inspection) patterns, etc. are generated to assist in forming the final pattern. Because the process manufacturing process is complex and the defects are inevitable, all the intermediate layer graphs and the final graph need to be subjected to defect detection, and the logic errors such as open circuits, short circuits, graph deletion, redundant graphs and the like are avoided when the intermediate layer graphs and the final graph are compared with the designed graph on the original layout.
The conventional online defect detection is generally realized by scanning light beams to generate gray scale images for comparison of adjacent chips, but with the reduction of the line width of an integrated circuit, smaller defects are difficult to detect, and the improvement of the sensitivity introduces a large amount of noise, so that the difficulty of defect detection is more and more high. In addition, in failure analysis, the judgment of the chip defects is realized through naked eye discrimination, the efficiency is low, and omission is easy to generate.
Disclosure of Invention
The invention aims to provide a defect detection method in the chip manufacturing process, which aims to reduce the difficulty of defect detection and has high efficiency and high accuracy.
The invention provides a defect detection method in the chip manufacturing process, which comprises the following steps: s1: acquiring a target detection image, and performing lamination processing on the target detection image and an original layout to form a laminated layout; and S2: dividing the laminated layout into a plurality of regions, wherein each region is provided with only one equipotential line, respectively analyzing the number of the equipotential lines of the target detection image and the original layout in each region, and judging that no physical defect exists if the target detection image and the original layout are the same; and if the number of the equipotential lines is different, determining that the physical defect exists.
Furthermore, the target detection image is a final image transferred to a silicon wafer according to a design image on an original layout or an intermediate layer image generated for forming the final image.
Further, the intermediate layer pattern is used to assist in forming the final pattern.
Furthermore, the target detection image obtained in step S1 is only a part of the actual chip original layout, and the target detection image is found at a corresponding position in the complete chip original layout and is subjected to stacking processing.
Further, in step S1, an object detection image is captured by scanning electron microscope imaging.
Furthermore, the equipotential lines are lines which are at the same potential in the target detection image, the original layout or both the target detection image and the original layout after electrification under the assumption that the lines in the target detection image in the laminated layout are electrically communicated with the overlapped part of the lines in the original layout.
Further, only one line in the original layout is included in one region divided by the overlay layout in step S2.
Further, only one line in the target detection image is included in one region divided by the overlay layout in step S2.
Further, in step S2, the one region divided by the overlay layout includes only one line in the original layout and one line in the target detection image, and the one line in the original layout and the one line in the target detection image at least partially overlap.
Further, only one line in the original layout and the first line and the second line in the target detection image are included in one region divided by the overlay layout in step S2, and the one line in the original layout and the first line and the second line in the target detection image are at least partially overlapped, respectively.
Further, in step S2, the one region divided by the overlay layout only includes the first line and the second line in the original layout and the line in the target detection image, and the first line and the second line in the original layout and the line in the target detection image respectively at least partially overlap.
Further, if there are two lines in the target inspection image and one line in the original layout, there is an open defect in step S2.
Further, in step S2, if there are two lines in the original layout and one line in the target inspection image, it indicates that there is a bridging defect.
Further, in step S2, if there is one line in the original layout and there are 0 equipotential lines in the target inspection image, it indicates that the missing-pattern defect exists.
Further, in step S2, if there are 0 lines in the original layout and one line in the target inspection image, it indicates that there is a redundant defect.
The defect detection method in the chip manufacturing process provided by the invention comprises the steps of obtaining a target detection image, searching a domain, finding a corresponding part of the target detection image in a complete chip original domain, performing lamination processing to form a laminated domain, dividing the laminated domain into a plurality of areas, and performing equipotential line number analysis on the target detection image and the original domain in each area respectively to perform defect detection, thereby reducing the difficulty of defect detection, and having high efficiency and high accuracy.
Drawings
Fig. 1 is a schematic diagram of a layout in which an acquired target detection image finds a corresponding position in an original layout of a chip and is subjected to stacking processing.
FIGS. 2 (a) - (e) are different examples of equipotential lines.
The reference numerals of the main elements in the figures are explained as follows:
510. 520, 521, 522, 511, 512, lines.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art based on the embodiments of the present invention without any creative effort, fall within the protection scope of the present invention.
In an embodiment of the present invention, a method for detecting defects in a chip manufacturing process is provided, and specifically, the method for detecting defects in a chip manufacturing process includes:
s1: acquiring a target detection image, and performing overlapping (overlay) processing on the target detection image and an original layout to form an overlapping layout;
specifically, in an embodiment of the present invention, the target detection image is a final pattern transferred to a silicon wafer according to a design pattern on an original layout or an intermediate layer pattern generated to form the final pattern. The intermediate layer pattern is, for example, a mask pattern, an ADI (post exposure inspection) pattern, an AEI (post etch inspection) pattern, or the like, and is used to assist in forming the final pattern. The final pattern and the intermediate layer pattern are not particularly limited in the present invention as long as the patterns are generated in the chip manufacturing process. Taking forming a gate structure of a semiconductor device as an example, in the manufacturing process of the gate structure of the semiconductor device, a photomask pattern is required to be used for a photolithography exposure process, an ADI (inspection after exposure) pattern is formed after the photolithography exposure process, then an etching process is performed, an AEI (inspection after etching) pattern is formed after the etching process, and then other processes are matched to finally form the gate structure of the semiconductor device, namely a final pattern, on a chip. In order to ensure that the final pattern formed has no defects, the final pattern and the gate structure in the original layout are compared and analyzed for defect detection, and interlayer patterns such as a photomask pattern, an ADI (post exposure inspection) pattern, an AEI (post etch inspection) pattern and the like generated in the process of forming the gate structure of the semiconductor device are compared and analyzed with the gate structure in the original layout for defect detection, so as to ensure that the final pattern formed has no defects.
The target detection image obtained in step S1 is only a part of the actual chip original layout, and the target detection image is found at a corresponding position in the complete chip original layout and subjected to stacking processing. Specifically, referring to fig. 1, fig. 1 is a layout diagram of an acquired target detection image after finding a corresponding position in an original chip layout and performing stack processing, where a region of a block 310 is the acquired target detection image, and a region of a block 320 is the original chip layout.
Specifically, in an embodiment of the present invention, the target inspection image is obtained by defect scanning or Scanning Electron Microscope (SEM) photographing. However, the present invention is not particularly limited thereto.
S2: dividing the laminated layout into a plurality of regions, wherein each region is provided with only one equipotential line, respectively analyzing the number of the equipotential lines of the target detection image and the original layout in each region, and judging that no physical defect exists if the target detection image and the original layout are the same; if the number of the equipotential lines is different, the physical defect is judged to exist.
In an embodiment of the present invention, the equipotential lines are lines that have the same potential in the target detection image, the original layout, or both the target detection image and the original layout after power is turned on if the overlapped portion of the lines in the target detection image in the stacked layout is electrically connected to the overlapped portion of the lines in the original layout. In an embodiment of the present invention, referring to (a) - (e) in fig. 2, fig. 2 (a) - (e) illustrate different embodiments of equipotential lines, and as shown in (a) in fig. 2, one region divided by the overlay layout includes only one line 510 in the original layout, and if power is applied to the line 510, the potentials of the lines 510 are the same to form an equipotential line. As shown in fig. 2 (b), only one line 520 in the target detection image is included in one region divided by the stacked layout, and when electricity is applied to the line 520, the potential of each part of the line 520 is the same, thereby forming an equipotential line. As shown in (c) of fig. 2, one region divided by the overlay layout only includes one line 510 in the original layout and one line 520 in the target detection image, the line 510 and the line 520 are at least partially overlapped, and if the overlapped portion of the line 510 and the line 520 is electrically connected, if power is applied to the line 510 and the line 520, the potentials of the line 510 and the line 520 are the same, so that the line 510 and the line 520 form an equipotential line. As shown in (d) in fig. 2, one region divided by the overlay layout only includes one line 510 in the original layout and lines 521 and 522 in the target detection image, the line 510 at least partially overlaps the lines 521 and 522, respectively, and if electricity is applied to the line 510 and the lines 521 and 522, the lines 510 and 521 and 522 are at the same potential, so that the line 510 and 521 and 522 form an equipotential line. As shown in (e) in fig. 2, one region divided by the overlay layout only includes lines 511 and 512 in the original layout and line 520 in the target detection image, lines 511 and 512 at least partially overlap line 520, respectively, and if the portions of lines 511 and 512 overlapping line 520 are electrically connected, lines 511 and 512 and line 520 have the same potential so that lines 511 and 512 and line 520 form an equipotential line.
Further, in an embodiment of the present invention, if there are two lines in the target inspection image and there is one line in the original layout, there is an open defect. As shown in fig. 2 (d), there is an open defect in the lines 511 and 512.
Further, in an embodiment of the present invention, if there are two lines in the original layout and one line in the target inspection image, it indicates that there is a defect of bridging or short circuit. As shown in fig. 2 (e), the lines 521 and 522 have a bridging defect.
Further, in an embodiment of the present invention, if there is one line in the original layout and there are 0 equipotential lines in the target detection image, it indicates that there is a missing pattern defect. As shown in fig. 2 (a), a pattern-missing defect exists.
Further, in an embodiment of the present invention, if there are 0 lines in the original layout and one line in the target inspection image, it indicates that there is a redundant pattern defect. As shown in fig. 2 (b), a redundant pattern defect exists.
Furthermore, in an embodiment of the present invention, if the original layout and the pick-up layout are the same line, it is determined that there is no physical defect. As shown in fig. 2 (c).
In summary, the target detection image is obtained, the layout is searched, the target detection image is found out of the corresponding part in the complete chip original layout, the lamination processing is carried out to form the lamination layout, then the lamination layout is divided into a plurality of areas, each area is provided with one or only one equipotential line, the number of the equipotential lines is respectively carried out on the target detection image and the original layout in each area to carry out defect detection, the difficulty of defect detection is reduced, the efficiency is high, and the accuracy is high.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the spirit of the corresponding technical solutions of the embodiments of the present invention.
Claims (14)
1. A method for detecting defects in a chip manufacturing process is characterized by comprising the following steps:
s1: acquiring a target detection image, and performing lamination processing on the target detection image and an original layout to form a laminated layout; and
s2: dividing the laminated layout into a plurality of regions, wherein each region is provided with only one equipotential line, performing line number analysis which satisfies the requirement of only one equipotential line on the target detection image and the original layout in each region, and judging that no physical defect exists if the number of the lines in the target detection image and the number of the lines in the original layout are one and the lines are at least partially overlapped; if the number of lines in the target detection image is inconsistent with that of the original layout, judging that the physical defect exists;
and the equipotential lines are lines which are at the same potential in the target detection image, the original layout or both the target detection image and the original layout after electrification under the assumption that the overlapped part of the lines in the target detection image in the laminated layout is electrically communicated with the overlapped part of the lines in the original layout.
2. The method of claim 1, wherein the target inspection image is a final pattern transferred onto a silicon wafer according to a design pattern on an original layout or an intermediate layer pattern generated for forming the final pattern.
3. The method of claim 2, wherein the intermediate layer pattern is used to assist in forming the final pattern.
4. The method according to claim 1, wherein the target detection image obtained in step S1 is only a part of the original layout of the actual chip, and the corresponding position of the target detection image in the original layout of the entire chip is found and subjected to stacking processing.
5. The method for detecting defects in a chip manufacturing process according to claim 1, wherein the step S1 is performed by capturing an object inspection image through a scanning electron microscope.
6. The method of detecting defects in a chip manufacturing process according to claim 1, wherein only one line in the original layout is included in one region divided by the overlay layout in step S2.
7. The method of detecting defects in a chip manufacturing process according to claim 1, wherein only one line in the target inspection image is included in one region divided by the overlay layout in step S2.
8. The method according to claim 1, wherein the region divided by the overlay layout in step S2 includes only one line in the original layout and one line in the target detection image, and the one line in the original layout and the one line in the target detection image at least partially overlap.
9. The method of detecting defects in a chip manufacturing process according to claim 1, wherein only one line in the original layout and the first and second lines in the target inspection image are included in one region divided by the overlay layout in step S2, and the one line in the original layout and the first and second lines in the target inspection image at least partially overlap, respectively.
10. The method according to claim 1, wherein the region divided by the overlay layout in step S2 includes only the first and second lines in the original layout and the lines in the target detection image, and the first and second lines in the original layout and the lines in the target detection image at least partially overlap each other.
11. The method of claim 1, wherein if there are two lines in the target inspection image and one line in the original layout, there is an open defect in step S2.
12. The method of claim 1, wherein if there are two lines in the original layout and one line in the target inspection image, it indicates that there is a bridging defect in step S2.
13. The method of claim 1, wherein in step S2, if there is one line in the original layout and 0 equipotential lines in the target inspection image, it indicates that the missing-pattern defect exists.
14. The method of claim 1, wherein in step S2, if there are 0 lines in the original layout and one line in the target inspection image, it indicates that there is a redundant graphic defect.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102142355A (en) * | 2010-02-02 | 2011-08-03 | 吕一云 | Application method of object manufacture defect |
| CN102193302A (en) * | 2010-03-03 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Mask image defection detection method and detection system thereof |
| CN103915361A (en) * | 2014-04-08 | 2014-07-09 | 上海华力微电子有限公司 | Method for detecting chip defects |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102142355A (en) * | 2010-02-02 | 2011-08-03 | 吕一云 | Application method of object manufacture defect |
| CN102193302A (en) * | 2010-03-03 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Mask image defection detection method and detection system thereof |
| CN103915361A (en) * | 2014-04-08 | 2014-07-09 | 上海华力微电子有限公司 | Method for detecting chip defects |
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