TW519705B - Low temperature oxidation of conductive layers for semiconductor fabrication - Google Patents

Low temperature oxidation of conductive layers for semiconductor fabrication Download PDF

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Publication number
TW519705B
TW519705B TW089111040A TW89111040A TW519705B TW 519705 B TW519705 B TW 519705B TW 089111040 A TW089111040 A TW 089111040A TW 89111040 A TW89111040 A TW 89111040A TW 519705 B TW519705 B TW 519705B
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Taiwan
Prior art keywords
valve metal
wafer
metal material
metal oxide
solution
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TW089111040A
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Chinese (zh)
Inventor
Oliver Genz
Alexander Michaelis
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Infineon Technologies Corp
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02258—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by anodic treatment, e.g. anodic oxidation
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/022—Anodisation on selected surface areas
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Abstract

A method for forming a valve metal oxide for semiconductor fabrication in accordance with the present invention is disclosed and claimed. The method includes the steps of providing a semiconductor wafer (100), depositing a valve metal (110) on the wafer, placing the wafer in an electrochemical cell (200) such that a solution (114) including electrolytes interacts with the valve metal to form a metal oxide (111) when a potential difference is provided between the valve metal (110) and the solution (114) and processing the wafer using the metal oxide layer.

Description

519705 A7 B7 五、發明說明（，） [背景】 [技術領域] 本揭示係有關於半導體製造，且特別地是有關於以低溫 金屬氧化所形成的蝕刻硬式遮罩。 [相關技藝之說明】 半導體製造中的溝渠製造通常爲用於形成半導體晶圓之 溝渠或其他組件的遮罩容量所限。爲更詳細說明此，一作 爲舉例的深溝渠蝕刻實例將予以說明。所使用的深溝渠包 含用於一深溝渠電容器的一儲存節點。爲增加深溝渠電容 器的電容量，增加儲存節點的表面積爲有利的。達成其的 一種方法爲增加深溝渠深度，因爲包含深溝渠的基板可提 供深，而對基板佈局無衝擊，該深溝渠（DT)蝕刻深度通常 爲如下所說明的遮罩侵蝕所限。 參考第1圖，一記憶體裝置10包含具有一襯墊堆疊11 形成於其上的一基板12，基板12偏，好爲單晶矽基板，襯 墊堆疊11包含一個氧化物層14與一個氮化物層16。硬式 遮單層18沈積於襯墊堆疊11上。硬式遮罩18係使用熟 習本技藝之人士熟知的光學微影技術而蝕刻，而形成孔洞 15(DT17將形成於此）。溝渠17的形成偏好使用諸如反應 性離子蝕刻（RIE)等非等向性鈾刻形成。 溝渠17蝕刻入基板12中。然而，在該製程期間，侵蝕 硬式遮罩18，其可能對鄰接溝渠17位置的區域造成間接 的傷害。蝕刻越久，則硬式遮罩1 8侵触的風險越高。 爲增加蝕刻時間，可使用較厚的硬式18遮罩。然而， 此將增加製程時間，且不會提供較深的溝渠。 -3- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 一 一°4· B1B1 -1 I I I MmKmm I an an ϋ ϋ ·ϋ ϋ I ^1 ^1 ϋ ϋ ϋ ·ϋ ^1 ^1 ϋ · 經濟部智慧財產局員工消費合作社印製 519705 A7 B7 五、發明說明（y) 因此，具有增加選擇性之更經濟的蝕刻用硬式遮罩爲需 要的，以便在硬式遮罩未明顯侵蝕下增加蝕刻時間。 [發明槪述】 根據本發明之一種用於形成半導體製造的閥金屬氧化物 的方法包含的步驟有提供一半導體晶圓，沈積一閥金屬材 料於該晶圓上，將該晶圓安置於電化學電池中，以使得含 電解質的一溶液與該閥金屬材料交互作用，而在一電位差 提供於該閥金屬材料與溶液之間時形成一個金屬氧化物， 以及使用該金屬氧化物層將晶圓加工。 根據本發明之一種用於蝕刻溝渠於半導體基板中的方法 包含的步驟有提供一半導體晶圓，形成一基板的襯墊堆疊 ，沈積一閥金屬材料於該襯墊堆疊上，將該基板安置於電 化學電池中，以使得含電解質的一溶液與該閥金屬材料交 互作用，而在一電位差提供於該閥金屬材料與溶液之間時 形成一個金屬氧化物，以及使用該金屬氧化物作爲用於將 溝渠蝕入基板中的一鈾刻遮罩。 根據本發明之另一種用於形成半導體製造的閥金屬氧化 物的方法包含的步驟有提供一包含至少有一層形成於其上 之基板的半導體晶圓，沈積一介電層於該至少一層上，沈 積一閥金屬材料於該介電層上，藉由將該晶圓安置於電化 學電池中，以使得含電解質的一溶液與該閥金屬材料交互 作用，而在一電位差被提供於該閥金屬材料與溶液之間時 形成一個金屬氧化物’而將該閥金屬材料氧化，該介電層 用於在氧化步驟期間提供對於該至少一層的保護，以及使 -4- 本&張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） " " — (請先閱讀背面之注意事項再填寫本頁) it an — ϋ ϋ ϋ 1 I ϋ I I I 1 n 1 I 1 I I i^i an n ϋ n 1 519705 A7 _ B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（々） 用該金屬氧化物層將晶圓加工。 在另一個方法中，沈積一閥金屬材料的步驟可能包含沈 積由鋁、鈮、鉅、鈦、氮化鈦、飴及鉻組成的族群中選擇 的一閥金屬材科。該方法可―包含槪歩驟赛施加一電屢於該 閥金屬材料與溶液之間而形成電位差，以使得所施加的電 壓可控制該金屬氧化物厚度。該溶液可包含乙酸鹽緩衝物 於水性溶液中。該乙酸鹽緩衝溶液較佳地具有約4至7之 間的pH値。將晶圓安置於電化學電池中的步驟包含將晶 圓安置於電化學電池中，以使得該晶圓具有暴露出的閥金 屬表面積，以及提供暴露表面積大於閥金屬之暴露表面積 的一相對電極於該溶液中。 將晶圓安置於電化學電池中的步驟可包含將除了暴露出 的閥金屬材料面積以外的區域密封，以避免該閥金屬材料 與溶液接觸，包含電解質的該溶液較佳地與閥金屬材料交 互作用，而在約室溫形成金屬氧化物。使用該金屬氧化物 層而將晶圓加工的步驟可包含使用該金屬氧化物層作爲一 蝕刻遮罩和/或蝕刻阻絕物的步驟。使用該金屬氧化物作 爲用於將溝渠蝕入基板之蝕刻遮罩的該步驟可包含將該閥 金屬材料製作圖案，而在溝渠的位置開啓孔洞的步驟。使 用該金屬氧化物作爲用於將溝渠蝕入基板之蝕刻遮罩的該 步驟可包含將該金屬氧化物製作圖案，而在溝渠的位置開 啓孔洞的步驟。將晶圓加工的步驟可包含將閥金屬材料製 作圖案而在溝渠位置開啓孔洞的步驟，以使用該金屬氧化 物作爲蝕刻遮罩。將晶圓加工的步驟可包含將金屬氧化物 -5- 本&張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐^ (請先閱讀背面之注意事項再填寫本頁) 音------ 訂i 線 _♦----------------------- 519705 Α7 Β7 五、發明說明（4 ) 製作圖案而在溝渠位置開啓孔洞的步驟，以使用該金屬氧 化物作爲蝕刻遮罩。 本發明的這些與其他目的、特徵及優點將由下列舉例實 施例的細節說明而變得更淸楚，該細節說明係配合附圖硏 讀。 [圖式之簡單說明】 本揭示將參考下列圖式而詳細地呈現於下列較佳實施例 的說明中，其中： 第1圖爲表示溝渠蝕刻期間之硬式遮罩侵蝕的傳統半導 體裝置的剖面圖； 第2圖爲表示根據本發明之一閥金屬材料層被沈積於其 上之半導體裝置的剖面圖； 第3圖爲表示在閥金屬材料層製作圖案後，根據本發明 之第2圖的閥金屬材料層氧化之半導體裝置的剖面圖； 第4圖爲一種用於電化學形成根據本發明之一閥金屬氧 化物的設備的示意圖； 第5圖爲根據本發明之電容量C (電荷儲存）對電位ϋ的 圖式； 第6圖爲根據本發明之電流I對電位U的圖式； 第7圖爲表示根據本發明之作爲蝕刻遮罩之氧化閥金屬 層的第3圖的半導體裝置的剖面圖； 第8圖爲表示根據本發明之沈積在一保護介電層上之一 閥金屬材料層的半導體裝置的剖面圖； 第9圖爲表示在該經氧化金屬層製作圖案前，根據本發 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 I I ^1 ^1 βϋ _1 ϋ ·1 ϋ ϋ ϋ ϋ ^1 1 ϋ ϋ ·ϋ ι 519705 A7 B7 五、發明說明（r) 明之第8圖的氧化閥金屬層的半導體裝置的剖面圖；以及 第1 〇圖爲表示根據本發明之作爲蝕刻遮罩之經氧化閥 金屬層的第9圖的半導體裝置的剖面圖。 [較佳實施例之詳細說明] 本發明係有關於半導體製造，且更特別地是有關於具有 經改良選擇性蝕刻能力的硬式遮罩。根據本發明的硬式遮 罩包含諸如閥金屬等金屬或諸如氮化鈦等其他導電性化合 物。爲簡化起見，閥金屬將認爲亦包含其他化合物，該閥 金屬較佳地以低溫氧化法氧化。在較佳實施例中，使用諸 如 Al2〇3，Ti02，Ta205，Nb206，Zr02，及 Hf02 等之閥 金屬氧化物。這些氧化物呈現高鈾刻選擇性，並可較習知 硬式遮罩以更經濟有效率的方法形成。一種用於在低溫形 成閥金屬氧化物硬式遮罩的製程現在將更詳細地說明。 現在特別詳細地參考圖式，其中相同的參考數字在所有 圖式中代表類似或相當的元件，以及從第2圖開始，一半 導體裝置1〇〇可包含諸如動態隨機存取記憶體（DRAM)、 同步DRAM、靜態RAM以及唯讀記憶體或其他記憶體積 體電路等記憶體裝置。裝置100亦可包含處理器晶片、邏 輯電路、特殊應用晶片或類似物。雖然裝置及下列方 法將舉例說明用於半導體記憶體中的深溝渠形成，然而本 發明係更爲廣泛且可被應用於在任何製程步驟使用閥金屬 氧化物的一蝕刻遮罩或一薄層的任何半導體裝置。 裝置100包含一基板102。基板102可包含矽材料，雖 然可使用諸如砷化鎵、矽在絕緣體上等之基板材料。一襯 -7- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱Ί " (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -0 ϋ ϋ I ϋ ϋ ϋ 1 mm— ϋ ϋ 1 I ϋ I 線如----------------------- 519705 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（^ ) 墊堆疊101形成於基板102的頂端表面104上。襯墊堆疊 101可包含一個氧化層106及一個氮化層108。其他層可 提供，或多層氧化物和/或氮化物層可使用。 根據本發明，一閥金屬層110被沈積於襯墊堆疊1〇1上。 閥金屬層110可包含鋁、鈦、鉅、鈮、銷和/或飴之一或 多種。諸如氮化鈦等相對於基板1 02可選擇性地蝕刻之形 成氧化物的其他的導電性金屬閥化合物可予以使用。閥金 屬層110可使用化學氣相沈積（CVD)製程沈積。此外，閥 金屬層110可使用物理氣相沈積（PVD)製程沈積。閥金屬 層110可沈積達約lOnm至約600nm間的厚度，較佳地爲 約100nm至約300nm間，雖然可使用其他厚度。 閥金屬110可在此時製作圖案或氧化，並按著被製作圖 案。在另一個狀況中，該氧化物或金屬係以熟習本技藝之 人士所熟習的微影製作圖案及微影技術製作圖案。爲方便 起見，閥金屬層110在氧化前製作圖案的狀況係表示於第 3圖中。在氧化前製作圖案閥金屬層110爲較佳的，因爲 層11 0可相對於微影光阻層而選擇性地蝕刻；光胆層（未 表示於圖中）對層1 00有選擇性，其足以使用反應性離子 蝕刻（RIE)而開啓厚度約60〇nm的層110，其他層厚亦可 被使用，此舉相當於一硬式遮罩開啓製程；藉由以該方法 製作層110之圖案，層100基於該金屬層對光阻的選擇性 而容易製作圖案；接著移除該光阻層。 參考第3圖，經製作圖案閥金屬層110現在以捍據本發 明的低溫氧化製程而氧化，以形成一金屬氧化物層20 (第 -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) # 519705 A7 B7 五、發明說明（7 ) 7圖）。一電極112連接至閥金屬層11〇(或基板102，若一 適當的導電性路徑存在於基板102與閥金屬110之間）， 以及裝置1〇〇暴露於一電解質溶液114。閥金屬及其化合 物可根據本發明而被陽極氧化，以形成均勻的氧化物膜。 有利地，閥金屬氧化物電化學反應允許電流僅以單一方向 流動，亦即流向氧化物形成。根據高電場模型，一固定膜 厚d係以所施加的電位U而決定如下： d = k(U-U0X) EQ.1 其中，膜形成因子k及氧化物形成電位Up係取決於實驗 條件，包含所使用的電解質、溶液的pH値和/或所使用的 閥金屬。閥金屬層110在約室溫下氧化，雖然其他的溫度 可使用以獲得不同的結果。良好的控制該氧化製程，並產 生均勻的氧化。該經控制的氧化可以第4圖所示的設備獲 得。該製程將金屬及金屬化合物（氮化鈦）轉變爲氧化物。 這些氧化物現在使用爲硬式遮罩，因爲其耐以下的反應性 離子蝕刻製程。 參考第4圖’根據本發明’所不的一'設備200係用於 施加電壓以控制電化學氧化物形成於具有一裝置1 〇 〇形成 於其上的晶圓202上。設備200爲包含一個槽204的一電 化學電池，該槽2〇4塡充以含電解質的液體206。液體206 較佳地爲水，而電解質則可包含諸如鹽、酸性化合物、鹼 性化合物等或其組合的離子化合物。在一實、施例中，該電 解質包含約4至約7之pH濃度的乙酸緩衝物。其他化合 物及濃度爲希冀的且可提供，以使得離子可在槽204中的 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -· 11-----訂·------線—▲ 經濟部智慧財產局員工消費合作社印製519705 A7 B7 V. INTRODUCTION (,) [BACKGROUND] [Technical Field] The present disclosure relates to semiconductor manufacturing, and in particular, to an etching hard mask formed by low-temperature metal oxidation. [Explanation of Related Techniques] Trench manufacturing in semiconductor manufacturing is usually limited by the mask capacity of trenches or other components used to form semiconductor wafers. To illustrate this in more detail, an example of deep trench etching will be described. The deep trench used includes a storage node for a deep trench capacitor. To increase the capacitance of a deep trench capacitor, it is advantageous to increase the surface area of the storage node. One way to achieve this is to increase the depth of deep trenches, as substrates containing deep trenches can provide depth without impacting the layout of the substrate. The depth of the deep trench (DT) etch is usually limited by mask erosion as described below. Referring to FIG. 1, a memory device 10 includes a substrate 12 having a pad stack 11 formed thereon. The substrate 12 is biased to be a single crystal silicon substrate. The pad stack 11 includes an oxide layer 14 and a nitrogen layer.物 层 16。 The material layer 16. A hard masking layer 18 is deposited on the pad stack 11. The hard mask 18 is etched using optical lithography techniques well known to those skilled in the art to form holes 15 (DT17 will be formed here). The trench 17 is preferably formed using an anisotropic uranium etch such as reactive ion etching (RIE). The trench 17 is etched into the substrate 12. However, during this process, the hard mask 18 is eroded, which may cause indirect damage to the area adjacent to the trench 17 location. The longer the etch, the higher the risk of hard mask 18 interference. To increase the etch time, a thicker hard 18 mask can be used. However, this will increase process time and will not provide deeper trenches. -3- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ° 4 · B1B1 -1 III MmKmm I an an ϋ ϋ · ϋ ϋ I ^ 1 ^ 1 ϋ ϋ ϋ · ϋ ^ 1 ^ 1 ϋ · Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 519705 A7 B7 V. Invention Description (y) Therefore A more economical hard mask for etching with increased selectivity is needed in order to increase the etch time without the hard mask significantly eroding. [Invention description] A method for forming a valve metal oxide for semiconductor manufacturing according to the present invention includes the steps of providing a semiconductor wafer, depositing a valve metal material on the wafer, and placing the wafer on an electrochemical device. In a battery, a solution containing an electrolyte interacts with the valve metal material, a metal oxide is formed when a potential difference is provided between the valve metal material and the solution, and a wafer is formed using the metal oxide layer. machining. A method for etching trenches in a semiconductor substrate according to the present invention includes the steps of providing a semiconductor wafer, forming a pad stack of a substrate, depositing a valve metal material on the pad stack, and placing the substrate on In an electrochemical cell, a solution containing an electrolyte interacts with the valve metal material, and a metal oxide is formed when a potential difference is provided between the valve metal material and the solution, and the metal oxide is used as A trench is etched into a etched mask in the substrate. Another method for forming a valve metal oxide for semiconductor manufacturing according to the present invention includes the steps of providing a semiconductor wafer including at least one substrate formed thereon, depositing a dielectric layer on the at least one layer, A valve metal material is deposited on the dielectric layer, and by placing the wafer in an electrochemical cell, a solution containing an electrolyte interacts with the valve metal material, and a potential difference is provided to the valve metal. When a metal oxide is formed between the material and the solution, the valve metal material is oxidized, the dielectric layer is used to provide protection for the at least one layer during the oxidation step, and to make the & Zhang scale applicable to China National Standard (CNS) A4 Specification (210 X 297 mm) " " — (Please read the notes on the back before filling this page) it an — ϋ ϋ ϋ 1 I ϋ III 1 n 1 I 1 II i ^ i an n ϋ n 1 519705 A7 _ B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (々) The metal oxide layer is used to process the wafer. In another method, the step of depositing a valve metal material may include depositing a valve metal material selected from the group consisting of aluminum, niobium, giant, titanium, titanium nitride, hafnium, and chromium. The method can include: applying a voltage step by step between the valve metal material and the solution to form a potential difference, so that the applied voltage can control the thickness of the metal oxide. The solution may include an acetate buffer in an aqueous solution. The acetate buffer solution preferably has a pH of between about 4 and 7. The step of placing a wafer in an electrochemical cell includes placing the wafer in an electrochemical cell such that the wafer has an exposed valve metal surface area, and providing an opposite electrode with an exposed surface area greater than the exposed surface area of the valve metal. The solution. The step of placing the wafer in the electrochemical cell may include sealing an area other than the exposed area of the valve metal material to prevent the valve metal material from contacting the solution, and the solution containing the electrolyte preferably interacts with the valve metal material. Effect while forming a metal oxide at about room temperature. The step of processing the wafer using the metal oxide layer may include the step of using the metal oxide layer as an etching mask and / or etching stopper. The step of using the metal oxide as an etching mask for etching the trench into the substrate may include a step of patterning the valve metal material and opening a hole at the position of the trench. The step of using the metal oxide as an etching mask for etching the trench into the substrate may include a step of patterning the metal oxide and opening a hole at the position of the trench. The step of processing the wafer may include a step of patterning the valve metal material to open a hole in the trench position to use the metal oxide as an etching mask. The steps of processing the wafer may include converting the metal oxides to the 5-scale & Zhang standards applicable to China National Standard (CNS) A4 specifications (210 X 297 mm ^ (Please read the precautions on the back before filling out this page). ------ Order i line _ ♦ ----------------------- 519705 Α7 Β7 V. Description of the invention (4) Make the pattern and place it in the trench The step of opening the holes uses the metal oxide as an etching mask. These and other objects, features, and advantages of the present invention will be made clearer by the detailed description of the following example embodiments, which are described in conjunction with the drawings Read. [Simplified Description of the Drawings] This disclosure will be presented in detail in the description of the following preferred embodiments with reference to the following drawings, in which: FIG. 1 is a conventional semiconductor device showing hard mask erosion during trench etching. Sectional view; FIG. 2 is a sectional view showing a semiconductor device on which a valve metal material layer is deposited according to one of the present invention; FIG. 3 is a view showing a second image according to the present invention after patterning is performed on the valve metal material layer Sectional view of a semiconductor device for oxidizing a valve metal material layer; FIG. 4 is a schematic diagram of an apparatus for electrochemically forming a valve metal oxide according to the present invention; FIG. 5 is a diagram of a capacitance C (charge storage) versus a potential ϋ according to the present invention; and FIG. 6 is Diagram of current I versus potential U according to the present invention; FIG. 7 is a cross-sectional view of a semiconductor device of FIG. 3 showing an oxide valve metal layer as an etching mask according to the present invention; FIG. 8 is a view showing a semiconductor device according to the present invention A cross-sectional view of a semiconductor device with a valve metal material layer deposited on a protective dielectric layer; FIG. 9 shows that before the patterning of the oxidized metal layer, the Chinese National Standard (CNS) was applied according to the paper dimensions A4 size (210 X 297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs II ^ 1 ^ 1 βϋ _1 ϋ · 1 ϋ ϋ ϋ ϋ1 1 ϋ ϋ · ϋ 519705 A7 B7 V. Description of the invention (r) Sectional view of the semiconductor device of the oxidized valve metal layer of FIG. 8; and FIG. 10 shows the oxidized valve metal as an etching mask according to the present invention. Semiconducting layer 9 A cross-sectional view of the device. [Detailed description of the preferred embodiment] The present invention relates to semiconductor manufacturing, and more particularly to a hard mask having improved selective etching capabilities. The hard mask according to the present invention includes A metal such as a valve metal or other conductive compound such as titanium nitride. For simplicity, the valve metal will be considered to include other compounds as well, the valve metal is preferably oxidized by a low temperature oxidation method. In a preferred embodiment, the Valve metal oxides such as Al203, Ti02, Ta205, Nb206, Zr02, and Hf02. These oxides exhibit high uranium etching selectivity and can be formed in a more economical and efficient manner than conventional hard masks. A process for forming a valve metal oxide hard mask at a low temperature will now be described in more detail. Reference is now made in particular to the drawings, in which the same reference numerals represent similar or equivalent elements in all drawings, and starting from FIG. 2, a semiconductor device 100 may include, for example, dynamic random access memory (DRAM) , Synchronous DRAM, static RAM, and memory devices such as read-only memory or other memory volume circuits. The device 100 may also include a processor chip, a logic circuit, an application-specific chip, or the like. Although the device and the following methods will exemplify the use of deep trench formation in semiconductor memory, the present invention is broader and can be applied to an etch mask or a thin layer of valve metal oxide at any process step Any semiconductor device. The device 100 includes a substrate 102. The substrate 102 may include a silicon material, although a substrate material such as gallium arsenide, silicon on an insulator, or the like may be used. Yilin-7- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 Public Love " (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs- 0 ϋ ϋ I ϋ ϋ ϋ 1 mm— ϋ ϋ 1 I ϋ I line such as ----------------------- 519705 Employees ’Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Print A7 B7 5. Description of the Invention (^) A pad stack 101 is formed on the top surface 104 of the substrate 102. The pad stack 101 may include an oxide layer 106 and a nitride layer 108. Other layers may be provided, or multiple oxides may be provided. And / or a nitride layer may be used. According to the present invention, a valve metal layer 110 is deposited on the gasket stack 101. The valve metal layer 110 may include one of aluminum, titanium, giant, niobium, pins, and / or hafnium Or more. Other conductive metal valve compounds such as titanium nitride that can be selectively etched relative to the substrate 102 can be used. The valve metal layer 110 can be deposited using a chemical vapor deposition (CVD) process. In addition, the valve metal layer 110 may be deposited using a physical vapor deposition (PVD) process. The valve metal layer 110 may be sunk. The thickness is between about 100 nm and about 600 nm, preferably between about 100 nm and about 300 nm, although other thicknesses can be used. The valve metal 110 can be patterned or oxidized at this time and patterned as desired. In another In the situation, the oxide or metal is patterned by lithography and lithography techniques familiar to those skilled in the art. For the sake of convenience, the condition of patterning the valve metal layer 110 before oxidation is shown in Section 3. In the figure, it is better to make the patterned valve metal layer 110 before oxidation, because the layer 110 can be selectively etched relative to the lithographic photoresist layer; the photobladder layer (not shown in the figure) has a layer 100. Selectivity, which is sufficient to use reactive ion etching (RIE) to open layer 110 with a thickness of about 60 nm, other layer thicknesses can also be used, which is equivalent to a hard mask opening process; by using this method to make the layer The pattern of 110, the layer 100 is easy to make a pattern based on the selectivity of the metal layer to the photoresist; then the photoresist layer is removed. Referring to FIG. Oxidation process A metal oxide layer 20 (No. -8- This paper size applies to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling this page) # 519705 A7 B7 V. Invention Explanation (7) 7). An electrode 112 is connected to the valve metal layer 11 (or the substrate 102, if an appropriate conductive path exists between the substrate 102 and the valve metal 110), and the device 100 is exposed to a Electrolyte solution 114. Valve metals and their compounds can be anodized in accordance with the present invention to form a uniform oxide film. Advantageously, the valve metal oxide electrochemical reaction allows a current to flow in only a single direction, i.e. to the oxide formation. According to the high electric field model, a fixed film thickness d is determined by the applied potential U as follows: d = k (U-U0X) EQ.1 where the film formation factor k and the oxide formation potential Up depend on experimental conditions, Contains the electrolyte used, the pH of the solution, and / or the valve metal used. The valve metal layer 110 is oxidized at about room temperature, although other temperatures can be used to obtain different results. The oxidation process is well controlled and produces uniform oxidation. This controlled oxidation can be obtained with the equipment shown in Figure 4. This process converts metals and metal compounds (titanium nitride) into oxides. These oxides are now used as hard masks because they are resistant to the following reactive ion etching processes. Referring to FIG. 4, a 'device 200 according to the present invention' is used to apply a voltage to control the formation of an electrochemical oxide on a wafer 202 having a device 100 formed thereon. The device 200 is an electrochemical cell containing a tank 204 filled with an electrolyte-containing liquid 206. The liquid 206 is preferably water, and the electrolyte may include an ionic compound such as a salt, an acidic compound, a basic compound, or the like, or a combination thereof. In one embodiment, the electrolyte comprises an acetate buffer having a pH concentration of about 4 to about 7. Other compounds and concentrations are desired and can be provided so that the ions can be in the slot 204. This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling in this Page)-· 11 ----- Order · ------ Line— ▲ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

-1_1 ϋ >1 ^ 11 ϋ ϋ ϋ ϋ ϋ ϋ H ϋ n I ^1 ^ ϋ I 519705 A7 _ B7 五、發明說明（j) 電極間傳遞。 裝置1〇〇(偏好被包含於半導體晶圓202上）固定於一絕 緣晶座2 J0上。夾頭212設置於晶圓20；Σ周圍，以固定並 密封晶圓202，而使得僅裝置100的上表面214被暴露於 槽204中的溶液206。電接觸係藉由導電線路218而被製 作於背面216的裝置100上，或直接被製作於閥金屬層 110，若絕緣層存在於基板102與閥金屬層110之間，諸 如上述的狀況。 一導電膜或箔220可被安置於一非導電性或絕緣晶座 210與晶圓202之間，以改良線路218與晶圓202間的電 接觸。一參考電極222包含於槽204中，而維持溶液206(在 第3與9圖中亦被標示爲溶液11 4)中的預定電位。參考電 極222將維持裝置1〇〇(較佳地爲晶片或晶圓）的電位。一 相對電極224亦被包含。相對電極224較佳地含至少如裝 置1〇〇之相同的暴露表面積數量。較佳地，相對於裝置100 的表面，相對電極224爲大的。亦即，相對電極224的表 面積爲閥金屬層110表面積的約1.5至約5 0.倍。相對電 極224較佳地包含一貴金屬（諸如金或鉑），以降低污染物 的顧慮，相對電極224較佳地包含已被氧化的相同金屬於 該晶圓上，亦即閥金屬層110的金屬。該電解質的最適化 條件將取決於各關金屬。 一電壓源或恆定電位器226，用於提供裝置100與參考 電極222間的電壓差。該電壓差使用於控制如上述之形成 在裝置100上的氧化物厚度。該具有裝置1〇〇的晶圓需要 -10- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) - — — ml— ^ ·11111111 I . 經濟部智慧財產局員工消費合作社印製 — — — — — — — — — — — — — — I — n I I I I I . 519705 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（？） 被潛浸於電解質溶液2 06中。該電位逐漸提高至靶電位， 其係爲希冀膜厚所需並維持在該電位一段時間。該氧化電 流及電荷可即時監測。當特定數量的總電荷已傳遞時，該 氧化完成。建立特定氧化物厚度所需的電荷數量取決於所 使用的金屬。第5至6圖舉例表示諸如Al，Ta，Nb，Hf ’ Ti與Zr等閥金屬在諸如pH爲5.9之乙酸鹽緩衝物之電 解質溶液中的電流-電壓行爲。使用類似於此的圖式，一 電荷/電流對電壓關係可獲得。一電壓因而設定，以獲得 根據本發明之希冀氧化物厚度。第6圖表示電位ϋ所造成 的電流I。第5圖表示電容量C對電位U。使用第5與6 圖以及EQ」，一閥金屬氧化物的厚度可根據指定的電位或 電流而決定，而提供特定厚度金屬氧化物所需的時間數量 可被決定。藉由監測電化學反應的特性，該金屬氧化物層 的性質可被決定，諸如氧化層厚度、金屬氧化層的橫向膨 脹等。有利地是，該訊息可消除根據本發明形成之金屬氧 化層的物理量測的需要。在將具有裝置100的晶圓由溶液 2 06取出後，殘留的電解質必須以去離子水移除。 參考第7圖，使用閥金屬氧化層120，進行基板102的 蝕刻。層120將提供高耐蝕刻性與高蝕刻選擇性於矽（基 板102)，以使得溝渠122形成。閥金屬氧化物層120較佳 地包含 Α12〇3，Ti〇2，Ta205，Nb206，Zr02，及 Hf02。 其他的氧化物亦可根據本發明而形成。該閥金屬氧化層120 的高耐蝕刻性與高蝕刻選擇性將提供RIE(或其他蝕刻製 程）較長的蝕刻時間。在舉例之包含深溝渠形成的實例中， -11- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) - 線· 519705 A7 B7 五、發明說明（π ) 較長的蝕刻時間將提供鈾刻較深溝渠的能力，而無侵蝕的 顧慮。加工可按著如本技藝所熟知的被進行。 -------------ΦΚ—— (請先閱讀背面之注意事項再填寫本頁) 參考第8圖’另一*個實施例含有包含一'基板302的裝置 300。基板302可包含矽材料，雖然可使用基板材料。一 襯墊堆疊301可包含一個氧化層306及一個氮化層308。 其他層可提供，或多層氧化物和/或氮化物層可使用。 根據本發明，一介電層311可沈積於襯墊堆疊301上。 介電層301包含相對於襯墊堆疊301頂層可被選擇性地移 除之諸如BPSG等氧化物或其他材料。介電層311可提供 以保護，而在後續步驟中的陽極氧化期間，保護襯墊堆疊 301或裝置300的其他組件。介電層311包含足以避免過 度氧化的厚度。一閥金屬層310沈積於該介電層311上。 閥金屬層310可使用如上述的CVD或PVD沈積。 線- 閥金屬層310可在此時製作圖案或氧化，並按著製作圖 案。在另一個狀況'中，該氧化物或金屬係以熟習本技藝之 人士所熟習的微影制作圖案及微影技術制作圖案。閥金屬 層3 1 0在氧化後製作圖案狀況係表示於第9圖中。 經濟部智慧財產局員工消費合作社印製 參考第9圖，層3 1J9係以如上述之低溫氧化製程而氧化 (參考第4圖）。一電極120連接至閥金屬層310或基板302。 閥金屬層310允許在部分位置與基板302接觸，因而允許 電極320被連接至基板302。層310完全氧化，而形成爲 閥金屬氧化層之層322 (第10圖）。 參考第10圖，閥金屬氧化層310已使用如上述的光阻（末 表示於圖中）而製作圖案。層322可以諸如RIE製程等對 -1 2 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) 519705 A7 B7 五、發明說明（） 於光阻有選擇性的乾式蝕刻製程而蝕刻。開口 3 1 3係穿經 閥金屬氧化層322而形成。溝渠316的鈾刻現在進行。根 據本發明，較深的溝渠316可形成，因爲閥金屬氧化物提 供對RIE的優越耐蝕刻性。加工可如本技藝所熟知地接續 進行。 有益地是，本發明提供一種用於形成硬式遮罩而無需消 耗熱預算的方法。本發明將在約室溫下形成氧化物化合物 。這些閥金屬氧化膜的熱形成通常需要在數百度°C的相當 高溫下進行。閥金屬氧化層可使用諸如濕式蝕刻製程而被 移除。 本發明係藉由在濺鍍前、後將各金屬膜陽極氧化，而提 供一均勻且緻密（無針孔）的閥金屬氧化膜於一晶圓上。一 些超過熱氧化的優點包含： 1) 低熱預算； 2) 易於以所施加的電位控制氧化物厚度； 3) 藉由量測氧化製程設備200中的電荷消耗，而即時監 測厚度； 4) 藉由量測氧化製程設備200中的電荷消耗，而易於控 制基於沿著裝置100或30 0表面之氧化所造成的金屬氧化 物橫向膨脹； 5) 藉由在室溫加工及仔細的電位控制，金屬氧化膜中的 應力降低可達成；以及 6) 較容易且較便宜的設備安裝與測試，且無污染物的顧 慮。 -1 3 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 --------^---------$1®----------------------- 519705 A7 B7 五、發明說明（丨> ) 本發明可使用於蝕刻溝渠，保護組件或多數種其他應用 。例如，一閥金屬氧化層可形成爲摻質植入用的遮罩，或 者蝕刻或拋光用的一阻絕層。 用於半導體製造之閥金屬低溫氧化的較佳實施例已被說 明（但其希冀作爲舉例而非限制），但應注意地是在上述教 導的揭示中，改良與更換將可爲熟習本技藝之人士爲之。 因此，應瞭解地是，落於斯附申請專利範圍之本發明的精 神與範疇中的改變可在所揭示之本發明的特定實施例中爲 之。 [元件符號對照表] ------------— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 10 11 12 14 15 16 17 18 100 101 102 104 106 108 記憶體裝置 襯墊堆疊 基板 氧化層 孔洞 氮化層 深溝渠 硬式遮罩層 裝置 襯墊堆疊 基板 頂端表面 氧化層 氮化層 -14- 線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 519705 Α7 Β7 經濟部智慧財產局員工消費合作社印製 --------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 發明說明（θ) 110 112 120 122 200 202 204 206 210 212 214 216 218 220 222 224 226 300 301 302 304 306 308 310 閥金屬層 電極 閥金屬氧化層 溝渠 設備 晶圓 槽 液體 晶座 夾頭 上表面 背面 導電線路 導電膜 參考電極 相對電極 電壓源 裝置 襯墊堆疊 基板 上表面 氧化層 氮化層 閥金屬層 -15- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 519705 A7 _B7 五、發明說明（A ) 311 介電層 313 開口 316 溝渠 320 電極 322 閥金屬氧化層 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -16- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）-1_1 ϋ > 1 ^ 11 ϋ ϋ ϋ ϋ ϋ ϋ H ϋ n I ^ 1 ^ ϋ I 519705 A7 _ B7 V. Description of the invention (j) Transfer between electrodes. The device 100 (preferably included on the semiconductor wafer 202) is fixed on an insulating wafer 2 J0. The chuck 212 is disposed around the wafer 20; Σ to fix and seal the wafer 202 so that only the upper surface 214 of the device 100 is exposed to the solution 206 in the groove 204. The electrical contact is made on the device 100 on the back surface 216 through the conductive line 218 or directly on the valve metal layer 110. If the insulating layer is present between the substrate 102 and the valve metal layer 110, it is as described above. A conductive film or foil 220 may be disposed between a non-conductive or insulating wafer base 210 and the wafer 202 to improve the electrical contact between the wiring 218 and the wafer 202. A reference electrode 222 is contained in the groove 204, and a predetermined potential is maintained in the solution 206 (also designated as the solution 11 4 in Figs. 3 and 9). The reference electrode 222 will maintain the potential of the device 100, preferably a wafer or wafer. A counter electrode 224 is also included. The counter electrode 224 preferably contains at least the same amount of exposed surface area as the device 100. Preferably, the opposite electrode 224 is large relative to the surface of the device 100. That is, the surface area of the counter electrode 224 is about 1.5 to about 50 times the surface area of the valve metal layer 110. The opposite electrode 224 preferably contains a precious metal (such as gold or platinum) to reduce the concern of contamination. The opposite electrode 224 preferably includes the same metal that has been oxidized on the wafer, that is, the metal of the valve metal layer 110. . The optimum conditions for this electrolyte will depend on the metals involved. A voltage source or constant potentiometer 226 is used to provide the voltage difference between the device 100 and the reference electrode 222. This voltage difference is used to control the thickness of the oxide formed on the device 100 as described above. The wafer with device 100 needs -10- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page)---ml- ^ · 11111111 I. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economy — — — — — — — — — — — — — I — n IIIII. 519705 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economy A7 B7 V. Invention Explanation (?) Was submerged in electrolyte solution 06. This potential is gradually increased to the target potential, which is required to maintain the film thickness for a period of time. The oxidation current and charge can be monitored immediately. This oxidation is complete when a certain amount of total charge has been transferred. The amount of charge required to establish a particular oxide thickness depends on the metal used. Figures 5 to 6 illustrate the current-voltage behavior of valve metals such as Al, Ta, Nb, Hf 'Ti and Zr in an electrolytic solution such as an acetate buffer at pH 5.9. Using a scheme similar to this, a charge / current versus voltage relationship is obtained. A voltage is thus set to obtain the desired oxide thickness according to the present invention. Figure 6 shows the current I caused by the potential ϋ. FIG. 5 shows the capacitance C versus the potential U. Using Figures 5 and 6 and EQ ", the thickness of a valve metal oxide can be determined according to a specified potential or current, and the amount of time required to provide a metal oxide of a specific thickness can be determined. By monitoring the characteristics of the electrochemical reaction, the properties of the metal oxide layer can be determined, such as the thickness of the oxide layer and the lateral expansion of the metal oxide layer. Advantageously, this message can eliminate the need for physical measurement of the metal oxide layer formed in accordance with the present invention. After the wafer having the device 100 is taken out from the solution 206, the residual electrolyte must be removed with deionized water. Referring to Fig. 7, the substrate 102 is etched using the valve metal oxide layer 120. The layer 120 will provide high etch resistance and high etch selectivity to silicon (substrate 102) so that trenches 122 are formed. The valve metal oxide layer 120 preferably includes A1203, Ti02, Ta205, Nb206, Zr02, and Hf02. Other oxides can also be formed according to the present invention. The high etch resistance and high etch selectivity of the valve metal oxide layer 120 will provide a longer etch time for RIE (or other etching processes). In the example that includes the formation of deep trenches, -11- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page)-Line · 519705 A7 B7 5. Description of the Invention (π) Longer etching time will provide the ability of uranium to etch deeper trenches without the concern of erosion. Processing can be performed as is well known in the art. ------------- ΦΚ—— (Please read the notes on the back before filling this page) Refer to FIG. 8 'Another * embodiment contains a device 300 including a substrate 302. The substrate 302 may include a silicon material, although a substrate material may be used. A pad stack 301 may include an oxide layer 306 and a nitride layer 308. Other layers may be provided, or multiple oxide and / or nitride layers may be used. According to the present invention, a dielectric layer 311 may be deposited on the pad stack 301. The dielectric layer 301 contains an oxide or other material such as BPSG that can be selectively removed relative to the top layer of the pad stack 301. The dielectric layer 311 may be provided for protection while protecting the pad stack 301 or other components of the device 300 during anodization in a subsequent step. The dielectric layer 311 contains a thickness sufficient to avoid excessive oxidation. A valve metal layer 310 is deposited on the dielectric layer 311. The valve metal layer 310 may be deposited using CVD or PVD as described above. The wire-valve metal layer 310 can be patterned or oxidized at this time and can be patterned accordingly. In another situation, the oxide or metal is patterned using lithography and lithography techniques familiar to those skilled in the art. The state in which the valve metal layer 3 1 0 is patterned after oxidation is shown in FIG. 9. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Refer to Figure 9, layer 3 1J9 is oxidized by the low temperature oxidation process as described above (refer to Figure 4). An electrode 120 is connected to the valve metal layer 310 or the substrate 302. The valve metal layer 310 allows contact with the substrate 302 at a partial position, thereby allowing the electrode 320 to be connected to the substrate 302. The layer 310 is completely oxidized to form a layer 322 as a valve metal oxide layer (FIG. 10). Referring to FIG. 10, the valve metal oxide layer 310 has been patterned using the photoresist (not shown in the figure) as described above. The layer 322 can be -1 such as the RIE process, etc.-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 519705 A7 B7 V. Description of the invention () Selective dry etching process for photoresist And etching. The opening 3 1 3 is formed through the valve metal oxide layer 322. Uranium carving of trench 316 is now proceeding. According to the present invention, deeper trenches 316 may be formed because the valve metal oxide provides superior etch resistance to RIE. Processing can be continued as is well known in the art. Advantageously, the present invention provides a method for forming a rigid mask without the need to consume a heat budget. The present invention will form an oxide compound at about room temperature. The thermal formation of these valve metal oxide films usually requires relatively high temperatures of several hundred degrees ° C. The valve metal oxide layer can be removed using processes such as wet etching. The present invention provides a uniform and dense (no pinhole) valve metal oxide film on a wafer by anodizing each metal film before and after sputtering. Some advantages over thermal oxidation include: 1) low thermal budget; 2) easy to control oxide thickness with applied potential; 3) real-time monitoring thickness by measuring charge consumption in oxidation process equipment 200; 4) by Measure the charge consumption in the oxidation process equipment 200 and easily control the lateral expansion based on the metal oxide caused by oxidation along the surface of the device 100 or 300; 5) By processing at room temperature and careful potential control, metal oxidation Stress reduction in the membrane can be achieved; and 6) easier and cheaper equipment installation and testing without concerns about contamination. -1 3-This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ---- ---- ^ --------- $ 1® ----------------------- 519705 A7 B7 V. Description of the invention (丨 > The invention can be used to etch trenches, protect components or most other applications. For example, a valve metal oxide layer can be formed as a mask for dopant implantation or as a barrier layer for etching or polishing. The preferred embodiment of low temperature oxidation of valve metal for semiconductor manufacturing has been described (but it is intended as an example and not a limitation), but it should be noted that in the disclosure of the above teachings, improvements and replacements will be familiar to those skilled in the art People do it. Therefore, it should be understood that changes in the spirit and scope of the invention falling within the scope of the Scottish Patent Application may be made in the specific embodiments of the invention disclosed. [Comparison Table of Component Symbols] ------------— (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 10 11 12 14 15 16 17 18 100 101 102 104 106 108 Memory device pad stack substrate oxide layer hole nitride layer deep trench hard mask layer device pad top substrate oxide layer nitride layer -14- line · This paper size applies to Chinese national standards ( CNS) A4 specification (210 X 297 mm) 519705 Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -------------------- Order ----- ---- Line (please read the precautions on the back before filling this page) Description of the invention (θ) 110 112 120 122 200 202 204 206 210 212 214 216 218 220 222 224 226 300 301 302 304 306 308 310 Valve metal layer Electrode valve metal oxide layer trench equipment wafer trough liquid crystal holder chuck upper surface back conductive circuit conductive film reference electrode opposite electrode voltage source device pad stack substrate upper surface oxide layer nitride layer valve metal layer -15- This paper size applies to China National Standard (CNS) A4 Specification (210 X 297 (%) 519705 A7 _B7 V. Description of the invention (A) 311 Dielectric layer 313 Opening 316 Ditch 320 Electrode 322 Valve metal oxide layer (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -16- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

519705 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 A'申請專利範圍 L 一種用於形成半導體製造的閥金屬氧化物的方法，包含 下列步驟： 提供一半導體晶圓； 沈積一閥金屬材料於該晶圓上； 將該晶圓安置於電化學電池中，以使得含電解質的一溶 液與該閥金屬材料交互作用，而在一電位差提供於該閥金 屬材料與溶液之間時形成一個金屬氧化物；以及 使用該金屬氧化物層將晶圓加工。 2·如申請專利範圍第1項之方法，其中沈積一閥金屬材料 的步驟包含沈積由錦、妮、钽、鈦、氮化鈦、給及鉻組 成的族群中選擇的一閥金屬材料。 3 ·如申請專利範圍第i項之方法，更包含有施加一電壓於 該閥金屬材料與溶液之間而形成電位差，以使得所施加 的電壓可控制該金屬氧化物厚度之步驟。 4 ·如申請專利範圍第1項之方法，其中該溶液包含乙酸鹽 緩衝物於水性溶液中。 5·如申請專利範圍第1項之方法，其中該乙酸鹽緩衝溶液 具有約4至7之間的pH値。 6 ·如申請專利範圍第1項之方法，其中將晶圓安置於電化 學電池中的步驟含有： 將晶圓安置於電化學電池中，以使得該晶圓具有暴露出 的閥金屬表面積；以及 提供暴露表面積大於閥金屬之暴露表面積的一相對電極 於該溶液中。 -17- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注咅P事項再填寫本頁) -0 訂---------線！ ^ ϋ — >1 ϋ n ϋ I n a— 519705 A8 B8 C8 D8 六、申請專利範圍 7 ·如申請專利範圍第6項之方法，其中將晶圓安置於電化 學電池中的步驟包含將除了暴露出的閥金屬材料面積以 外的區域密封，以避免該閥金屬材料與溶液接觸。 8·如申請專利範圍第1項之方法，其中包含電解質的該溶 液較佳地與閥金屬材料交互作用，而在約室溫形成金屬 氧化物。 9·如申請專利範圍第1項之方法，其中使用該金屬氧化物 層而將晶圓加工的步驟可包含使用該金屬氧化物層作爲 一蝕刻遮罩與蝕刻阻絕物之一的步驟。 1 〇 · —種用於蝕刻溝渠於半導體基板中的方法，包含下列 步驟： 提供一半導體晶圓； 形成一基板的襯墊堆疊； 沈積一閥金屬材料於該襯墊堆疊上，將該基板安置於電 化學電池中，以使得含電解質的一溶液與該閥金屬材料交 互作用，而在一電位差提供於該閥金屬材料與溶液之間時 形成一個金屬氧化物；以及 使用該金屬氧化物作爲用於將溝渠蝕入基板中的一蝕刻 遮罩。 11·如申請專利範圍第10項之方法，其中沈積一閥金屬材 料的步驟包含沈積由鋁、鈮、鉅、鈦、氮化鈦、耠及銷 組成的族群中選擇的一閥金屬材料。 1 2 ·如申請專利範圍第1 〇項之方法，更包含的步驟有施加 一電壓於該閥金屬材料與溶液之間而形成電位差，以使 -1 8 - ^本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） (請先閱讀背面之注意事項再填寫本頁) 0 經濟部智慧財產局員工消費合作社印制衣 1_· ϋ ϋ l^i I n immm I ·ϋ ϋ n I ϋ B^i B^i ϋ ϋ n ϋ ϋ ϋ ϋ I 519705 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 得所施加的電壓可控制該金屬氧化物厚度。 13·如申請專利範圍第10項之方法，其中該溶液包含乙酸 鹽緩衝物於水性溶液中。 14·如申請專利範圍第10項之方法，其中該乙酸鹽緩衝溶 液具有約4至7之間的pH値。 1 5 ·如申請專利範圍第1 0項之方法，其中將晶圓安置於電 化學電池中的步驟包含有： 將晶圓安置於電化學電池中，以使得該晶圓具有暴露出 的閥金屬表面積；以及 提供暴露表面積大於閥金屬之暴露表面積的一相對電極 於該溶液中。 1 6 ·如申請專利範圍第1 5項之方法，其中將晶圓安B於電 化學電池中的步驟包含將除了暴露出的閥金屬材料面積 以外的區域密封，以避免該閥金屬材料與溶液接觸。 17·如申請專利範圍第10項之方法，其中包含電解質的該 溶較佳地與閥金屬材料交互作用，而在約室溫形成金屬 氧化物。 18·如申請專利範圍第10項之方法，其中使用該金屬氧化 物作爲用於將溝渠蝕入基板之蝕刻遮罩的該步驟可包含 將該閥金屬材料製作圖案，而在溝渠的位置開啓孔洞的 步驟。 19·如申請專利範圍第10項之方法，其中使用該金屬氧化 物作爲用於將溝渠蝕入基板之蝕刻遮罩的該步驟可包含 將該金屬氧化物製作圖案，而在溝渠的位置開啓孔洞的 -19- ^紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) 0 訂------- 線！ r— — — — — — — — — — — — — — — — — — — 519705 A8 B8 C8 D8 ____ 六、申請專利範圍 步驟。 (請先閱讀背面之注意事項再填寫本頁) 20. —種用於形成半導體製造的閥金屬氧化物的方法，包 含下列步驟； 提供包含至少有一層形成於其上之基板的半導體晶圓； 沈積一介電層於該至少一層上； 沈積一閥金屬材料於該介電層上； 藉由將該晶圓安置於電化學電池中，以使得含電解質的 一溶液與該閥金屬材料交互作用，而在一電位差提供於該 閥金屬材料與溶液之間時形成一個金屬氧化物，而將該閥 金屬材料氧化’該介電層用於在氧化步驟期間提供對於該 至少一層的保護；以及 使用該金屬氧化物層將晶圓加工。 21·如申請專利範圍第20項之方法，其中沈積一閥金屬材 料的步驟包含沈積由鋁、鈮、鉅、鈦、氮化鈦、給及鍩 組成的族群中選擇的一閥金屬材料。 22.如申請專利範圍第20項之方法，更包含有施加一電壓 於該閥金屬材料與溶液之間而形成電位差，以使得所施 加的電壓可控制該金屬氧化物厚度的步驟。 經濟部智慧財產局員工消費合作社印製 23·如申請專利範圍第20項之方法，其中該溶液包含乙酸 鹽緩衝物於水性溶液中。 24·如申請專利範圍第2〇項之方法，其中該乙酸鹽緩衝溶 液具有約4至7之間的pH値。 25·如申請專利範圍第20項之方法，其中將晶圓安置於電 化學電池中的步驟包含： -20- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）^' 519705 A8 B8 C8 D8 六、申請專利範圍 將晶圓安置於電化學電池中，以使得該晶圓具有暴露出 的閥金屬表面積；以及 提供暴露表面積大於閥金屬之暴露表面積的一相對電極 於該溶液中。 26·如申請專利範圍第25項之方法，其中將晶圓安置於電 化學電池中的步驟包含將除了暴露出的閥金屬材料面積 以外的區域密封，以避免該閥金屬材料與溶液接觸。 27. 如申請專利範圍第20項之方法，其中包含電解質的該 溶液較佳地與閥金屬材料交互作用，而在約室溫形成金 屬氧化物。 28. 如申請專利範圍第20項之方法，其中使用該金屬氧化 物層而將晶圓加工的步驟可包含使用該金屬氧化物層作 爲一蝕刻遮罩與蝕刻阻絕物之一的步驟。 29. 如申請專利範圍第20項之方法，其中將晶圓加工的步 驟可包含將閥金屬材料製作圖案而在溝渠位置開啓孔洞 的步驟，以使用該金屬氧化物作爲蝕刻遮罩。 30. 如申請專利範圍第20項之方法，其中將晶圓加工的步 驟可包含將金屬氧化物製作圖案而在溝渠位置開啓孔洞 的步驟，以使用該金屬氧化物作爲蝕刻遮罩。 -21- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------0 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製519705 A8 B8 C8 D8 Printed by the Consumers 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A' Application for Patent Scope L A method for forming a valve metal oxide for semiconductor manufacturing, including the following steps: providing a semiconductor wafer; depositing a valve metal material On the wafer; placing the wafer in an electrochemical cell so that a solution containing an electrolyte interacts with the valve metal material, and a metal is formed when a potential difference is provided between the valve metal material and the solution Oxide; and processing the wafer using the metal oxide layer. 2. The method of claim 1 in which the step of depositing a valve metal material includes depositing a valve metal material selected from the group consisting of brocade, niobium, tantalum, titanium, titanium nitride, and chromium. 3. The method according to item i of the patent application, further comprising the step of applying a voltage between the valve metal material and the solution to form a potential difference so that the applied voltage can control the thickness of the metal oxide. 4. The method of claim 1 in which the solution comprises an acetate buffer in an aqueous solution. 5. The method of claim 1 in which the acetate buffer solution has a pH of between about 4 and 7. 6. The method of claim 1, wherein the step of placing the wafer in the electrochemical cell includes: placing the wafer in the electrochemical cell so that the wafer has an exposed valve metal surface area; and An opposing electrode is provided in the solution with an exposed surface area greater than that of the valve metal. -17- The size of this paper is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back before filling in this page) -0 Order --------- line !! ^ ϋ — > 1 ϋ n ϋ I na— 519705 A8 B8 C8 D8 VI. Application for Patent Scope 7 · As the method for applying for Patent Scope Item 6, the step of placing the wafer in an electrochemical cell includes removing the exposure The area outside the area of the valve metal material is sealed to prevent the valve metal material from contacting the solution. 8. The method of claim 1 in the scope of patent application, wherein the solution containing the electrolyte preferably interacts with the valve metal material to form a metal oxide at about room temperature. 9. The method of claim 1, wherein the step of processing the wafer using the metal oxide layer may include the step of using the metal oxide layer as one of an etching mask and an etching stopper. 10. A method for etching trenches in a semiconductor substrate, including the following steps: providing a semiconductor wafer; forming a substrate stack; and depositing a valve metal material on the substrate stack, and positioning the substrate In an electrochemical cell, a solution containing an electrolyte interacts with the valve metal material, and a metal oxide is formed when a potential difference is provided between the valve metal material and the solution; and the metal oxide is used as An etch mask for etching the trench into the substrate. 11. The method of claim 10, wherein the step of depositing a valve metal material comprises depositing a valve metal material selected from the group consisting of aluminum, niobium, giant, titanium, titanium nitride, hafnium, and pins. 1 2 · As for the method in the scope of patent application No. 10, the method further includes the step of applying a voltage between the valve metal material and the solution to form a potential difference, so that the paper size applies to Chinese national standards ( CNS) A4 size (210 X 297) (Please read the notes on the back before filling out this page) 0 Printed clothing by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1_ · ϋ ϋ l ^ i I n immm I · ϋ ϋ n I ϋ B ^ i B ^ i ϋ ϋ n ϋ ϋ ϋ ϋ ϋ I 519705 A8 B8 C8 D8 Printed by the Intellectual Property Bureau Employees Consumer Cooperatives of the Ministry of Economic Affairs 6. The applied voltage can control the thickness of the metal oxide. 13. The method of claim 10, wherein the solution comprises an acetate buffer in an aqueous solution. 14. The method of claim 10, wherein the acetate buffer solution has a pH of between about 4 and 7. 15 · The method of claim 10, wherein the step of placing a wafer in an electrochemical cell includes: placing the wafer in an electrochemical cell so that the wafer has an exposed valve metal Surface area; and providing an opposing electrode in the solution with an exposed surface area greater than the exposed surface area of the valve metal. 16 · The method according to item 15 of the scope of patent application, wherein the step of mounting the wafer in the electrochemical cell includes sealing the area other than the exposed area of the valve metal material to avoid the valve metal material and the solution contact. 17. The method of claim 10, wherein the solvent containing the electrolyte preferably interacts with the valve metal material to form a metal oxide at about room temperature. 18. The method of claim 10, wherein the step of using the metal oxide as an etching mask for etching a trench into a substrate may include patterning the valve metal material, and opening a hole at the location of the trench. A step of. 19. The method of claim 10, wherein the step of using the metal oxide as an etching mask for etching a trench into a substrate may include patterning the metal oxide and opening a hole at the location of the trench. -19- ^ The paper size applies the Chinese National Standard (CNS) A4 specification (21 × X 297 mm) (Please read the note on the back? Matters before filling out this page) 0 Order ------- Line! r — — — — — — — — — — — — — — — — — — 519705 A8 B8 C8 D8 ____ 6. Application for patent scope steps. (Please read the precautions on the back before filling this page) 20. —A method for forming a valve metal oxide for semiconductor manufacturing, including the following steps: Provide a semiconductor wafer including at least one substrate formed on it; Depositing a dielectric layer on the at least one layer; depositing a valve metal material on the dielectric layer; placing the wafer in an electrochemical cell so that a solution containing an electrolyte interacts with the valve metal material And a metal oxide is formed when a potential difference is provided between the valve metal material and the solution, and the valve metal material is oxidized 'the dielectric layer is used to provide protection for the at least one layer during the oxidation step; and using The metal oxide layer processes the wafer. 21. The method of claim 20, wherein the step of depositing a valve metal material comprises depositing a valve metal material selected from the group consisting of aluminum, niobium, giant, titanium, titanium nitride, and hafnium. 22. The method of claim 20, further comprising the step of applying a voltage between the valve metal material and the solution to form a potential difference so that the applied voltage can control the thickness of the metal oxide. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 23. The method of claim 20, wherein the solution contains an acetate buffer in an aqueous solution. 24. The method of claim 20, wherein the acetate buffer solution has a pH of between about 4 and 7. 25. The method according to item 20 of the patent application, wherein the steps of placing the wafer in an electrochemical cell include: -20- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^ ' 519705 A8 B8 C8 D8 VI. Application for patent Place the wafer in an electrochemical cell so that the wafer has an exposed valve metal surface area; and provide a counter electrode in the solution with an exposed surface area greater than the exposed surface area of the valve metal. in. 26. The method of claim 25, wherein the step of placing the wafer in the electrochemical cell includes sealing an area other than the exposed area of the valve metal material to prevent the valve metal material from contacting the solution. 27. The method of claim 20, wherein the electrolyte-containing solution preferably interacts with the valve metal material to form a metal oxide at about room temperature. 28. The method of claim 20, wherein the step of processing the wafer using the metal oxide layer may include the step of using the metal oxide layer as one of an etching mask and an etching stopper. 29. The method of claim 20, wherein the step of processing the wafer may include the step of patterning the valve metal material to open a hole at the trench location, so as to use the metal oxide as an etching mask. 30. The method of claim 20, wherein the step of processing the wafer may include a step of patterning a metal oxide and opening a hole at a trench location to use the metal oxide as an etching mask. -21- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------ 0 (Please read the precautions on the back before filling this page) Ministry of Economy Printed by the Intellectual Property Bureau Staff Consumer Cooperative
TW089111040A 1999-06-08 2000-06-27 Low temperature oxidation of conductive layers for semiconductor fabrication TW519705B (en)

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