A7 B7 1524twf.doc/〇〇6 五、發明説明（/ ) 本發明.是有關於一種高密度積體電路的形成，且特別 是有關於一種垂直狀傳送電晶體（Pass Transistor)之動態隨 機存取記憶體（Dynamic Random Access Memories, DRAM) 的形成。 由於含有高密度元件之記憶體比早期低密度記憶體提 供更好的儲存能力’且每單位造價比低密度記憶體便宜’ 因此在半導體工業中’常常爲了增加晶片(Wafer)的資料儲 存能力，而提高記憶體的元件密度。 習知常藉由降低積體電路上部份結構的大小來提高積 體電路之元件密度，比如導線（Wirmg Lines)和電晶體閘 極（Transistor Gates)，以及降低各元件間的隔離區來達 成。其中降低電路結構的大小通常是指縮小製造積體電路 元件的、'設計規則（Design Rules) 〃而言。 習知動態隨機存取記憶體資料的儲存方式，是經由在 半導體基底表面所形成的一列電容器（Capacitor)中之每個 電容器，選擇性地帶電（Charging)或放電（Discharging) 而達成儲存資料的目的。其中大部份，是藉由結合邏輯上 爲0的放電電容狀態，和邏輯上爲1的帶電電容狀態，或 者相反，而將二位元資料中的單一位元儲存在每個電容器 中。記憶體電容器的儲存係經由所提供之電壓，而將電荷 儲存在電容器上，其儲存的電荷數量決定於電極的表面 積、電容器介電質（Dielectric)的介電常數與電容器上下電 極之間距（即介電質厚度）等。記憶體讀寫操作可以藉由使 用轉移場效應電晶體（Field Effect Transistor, FET)將電荷 3 -----------裝------訂-----、-線 (誚先閱讀背面之注意事項再填寫本萸)A7 B7 1524twf.doc / 〇〇6 V. Description of the invention (/) The present invention relates to the formation of a high-density integrated circuit, and in particular to the dynamic random storage of a vertical pass transistor (Pass Transistor). Take the formation of Dynamic Random Access Memories (DRAM). Because memory containing high-density components provides better storage capacity than earlier low-density memory 'and is cheaper per unit than low-density memory', it is often used in the semiconductor industry to increase the data storage capacity of wafers. And increase the component density of the memory. It is common practice to increase the component density of integrated circuits by reducing the size of some structures on the integrated circuits, such as wires (Wirmg Lines) and transistor gates (Transistor Gates), and reduce the isolation area between components . Among them, reducing the size of the circuit structure generally refers to reducing the design rules for manufacturing integrated circuit components. The storage method of the conventional dynamic random access memory data is achieved by selectively charging or discharging the capacitors in each row of capacitors formed on the surface of the semiconductor substrate. purpose. For the most part, a single bit in the binary data is stored in each capacitor by combining the state of the discharge capacitor which is logically 0 and the state of the charged capacitor which is logically 1 or vice versa. The storage of the memory capacitor is to store the charge on the capacitor through the voltage provided. The amount of stored charge is determined by the surface area of the electrode, the dielectric constant of the capacitor dielectric and the distance between the capacitor's upper and lower electrodes (ie Dielectric thickness) and so on. Memory read and write operations can use the Field Effect Transistor (FET) to charge 3 --------------------------- Line (诮 Read the notes on the back before filling in this 萸)
朽-;;·部十次杼卑而员T,消於AI:竹社印V 州屮闽囚家標岑（CNS ) Λ4規格（210X297公釐） 3 5 24twf.doc/006 A7 B7 五、發明説明（乙） 儲存電容器選擇性地耦合到位元線（Bit Line)，再將電荷 轉移到電容器或將電荷由電容器中取出而進行。位於位元 線和轉移場效應電晶體之間的接觸窗口（Contact Window)做 爲轉移場效應電晶體的一個源極/汲極（Source / Drain) 電極’電荷儲存電容器則與轉移場效應電晶體的另一個源 極/汲極電極接觸。位元線經由轉移場效應電晶體與電荷 儲存電容器下電極（Lower Electrode )連接，而字元線（Word Line)的訊號由場效應電晶體的閘極供應，使電荷儲存電 容和位元線之間很容易進行電荷的轉移。 將縮小的設計規則應用到動態隨機存取記憶體上，會 降低電容器下電極的表面積，而且，在傳統的平面電容器 設計應用縮小的設計規則，會降低電荷儲存電容器所可以 儲存的電荷量（即電容値，Capacitance )。而電容器上減 少的電容量將導致不同的問題’包括由衰減機制（Decay Mechanisms)和電荷遺漏（Charge Leakage)所造成資料的 喪失等。而電荷的損失會導致動態隨機存取記憶體需要頻 繁的電荷補充，以維持電容器中的電荷量’如此稱之爲更 新週期（Refresh cycles)，但於更新週期期間’記憶體則 無法進行資料的儲存和讀取。此外，若電荷儲存程度降低， 則需要更複雜的資料讀取設計或更靈敏的電荷感應放大器 來加以補償。然而’最新的動態隨機存取記憶體仍要求在 縮小基底面積記憶胞的同時，增加儲存的電量，故爲了達 到此目的，遂發展出各種不同電荷儲存表面之電容器結 構。 cii先閱讀背1&之.江意事項存填寫本萸)Decay-;; · Ten times, the Ministry of Inferiority and T, disappeared in AI: Bamboo Club Seal V, State and Min prisoner's standard Cen (CNS) Λ4 specification (210X297 mm) 3 5 24twf.doc / 006 A7 B7 V. Description of the Invention (B) The storage capacitor is selectively coupled to the bit line, and then the charge is transferred to or removed from the capacitor. The contact window between the bit line and the transfer field effect transistor is used as a source / drain electrode of the transfer field effect transistor. The charge storage capacitor and the transfer field effect transistor are Contact the other source / drain electrode. The bit line is connected to the lower electrode of the charge storage capacitor (Transfer Field Effect Transistor), and the word line signal is supplied by the gate of the Field Effect Transistor. It's easy to transfer charge between them. Applying reduced design rules to dynamic random access memory will reduce the surface area of the lower electrode of the capacitor, and applying reduced design rules to traditional planar capacitor design will reduce the amount of charge that can be stored by the charge storage capacitor (ie Capacitance, Capacitance). And the reduced capacitance on the capacitor will cause different problems, including the loss of data caused by Decay Mechanisms and Charge Leakage. The loss of charge will cause the dynamic random access memory to require frequent charge replenishment to maintain the amount of charge in the capacitor 'so-called refresh cycles, but during the refresh cycle' the memory cannot carry out data Store and read. In addition, if the charge storage level is reduced, more complex data reading designs or more sensitive charge-sensing amplifiers are needed to compensate. However, the latest dynamic random access memory still requires increasing the amount of stored electricity while reducing the memory area of the substrate. In order to achieve this purpose, various capacitor structures with different charge storage surfaces have been developed. cii first read memorandum 1 & zhi.
本紙认尺度这川屮阀家標呤{ (，NS ) Λ4规格（210Χ 297公漦） 3524twf.doc/006 A7 B7 五、發明説明（9) 第1A圖~第1C圖係繪示習知之動態隨機存取記憶體 製造步驟的剖面示意圖。 請參照第1A圖，在一基底100上形成有淺溝渠隔離 (Shallow Trench Isolation)結構 102，閘氧化層 1〇4 與閘極 106，而在閘極106側邊基底100上形成有源/汲極區1〇8。 之後在基底100上形成一氧化物層，作爲絕緣層110 ’並 定義絕緣層110，形成一接觸窗口 112。 請參照第1B圖，之後，在絕緣層110上形成一導電層 114，導電層114塡入接觸窗口 112而與源/汲極區108之 一電性耦接。 請參照第1C圖，再定義導電層114,形成導電層114a， 並在導電層114a上形成一半球形矽晶粒層115(1^1^-Sphencal Grain ; HSG)，而其中接觸窗口 112a、導電層 114a 與半球形矽晶粒層115所形成之柱狀結構作爲電容器之下 電極。之後在半球形砂晶粒層115上，形成一介電層116， 最後在介電層116上形成一導電層118,作爲電容器之上 電極。 在上述習知動態隨機存取記憶體之製造方法中，受限 於現有微影製程光源解析度的限制以及在考慮對準誤差的 情況下’使得不論是閘極寬度、接觸窗開口大小，甚至於 閘極與接觸窗之間的距離，均無法無限的縮小。再加上習 知動態隨機存取記億體之位元線、閘極以及電容器爲平面 分佈，亦即單一記憶胞所佔基底面積要提供給電晶體與電 容器兩者使用，因此實際上得以縮小的面積也實在有限。 (誚先閲讀背面之注意事項再填湾本頁) •裝· 線 衫·::;Λ·'‘部屮欢行卑局 u.T:o.-ir,介 At:ir=il,w 本紙沭尺度诚川屮阈囤家樣々（（、NS ) Λ4%格（210X297公釐） 3 524twf.doc/006 A7 B7 五、發明説明（f) 另外，習知動態隨機存取記憶體之電容器以接觸窗與 字元線之源/汲極電性耦接，且源/汲極區直接與基底接觸， 因此極易因遺漏電流而造成接合遺漏（Junction Leakage)的 現象，如此使得電容器的更新週期增加，而影響記憶體的 操作效能。 因此本發明的主要目的，就是在提供一種縮小動態隨 機存取記憶胞基底面積之方法，以提昇積集度，並避免了 習知界面漏電與高頻率更新週期等缺點。 爲達成本發明之上述和其他目的，發展一種具有垂直 傳送電晶體之動態隨機存取記憶體的結構與製造方法。此 種動態隨機存取記憶體將汲極、閘極、源極與電容器垂直 形成一圓筒結構，縮小了記憶胞的底面積。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： ，第1A〜1C圖係繪示習知之動態髓機存取記憶體製造步 驟的剖面示意圖；以及 第2A〜2]圖係繪示依照本發朋一較佳實施例，一種具 有垂直傳送露晶體之動態隨機存取記憶體的結構與製造方 .法剖面示意圖。· 圖式之標記說明： 100、201 :基底 102 :淺溝渠隔離結構 6 i紙ίΑ尺度適州十國囚家標彳（（、NS)A4規格（2]〇X297公釐） (誚先閱讀背面之注意事項再楨寫本頁) -裝. 1T- -線 A7 B7 3524twf.doc/006 五、發明説明（夂） 104、212 :閘氧化層 106 :閘極 1+Ό8 :源/汲極區 110、202 :絕緣層 112、112a、208、219 :接觸窗口 114、 114a、118、204、210、220、226、210a :導電 層 115、 222 :半球形矽晶粒層 200 :摻雜離子區 206 :內介電層 214 :通道層 216 :光阻 218 :開口 221 :半導體層 223 :電晶體主體 116、 224 :介電層 228 :摻雜離子之主體底部 實施例 請參照第2A圖〜第21圖，其繪示依照本發明的一較 佳實施例，一種具有垂直傳送電晶體之動態隨機存取記憶 體的結構與製造方法剖面示意圖。 請參照第2A圖，第2A圖係以罩幕(未繪出）定義半導 體基底201上之摻雜離子區200，並植入離子，例如N+型 雜質，來形成當作位元線的摻雜離子區200，摻雜離子區 7 本紙ίΑ尺度这w中®^家標彳（（'NS ) Λ4規格（210X297公釐） i J----------裝-----^--.1T------—線 (諳先閲讀背而之注意事項再填寫本頁) 3 524 twf.doc/006 A7 B7 五、發明説明（6) 200將連接至位元線控制電路（未繪示於圖中）。接著，於 半導體基底201上形成一絕緣層202,例如使用化學氣相 沉積法，再於絕緣層202之上形成一層作爲字元線的導電 層204,例如以化學氣相沉積法沉積一層多晶矽層或多晶 矽化物(Polycide)，而絕緣層202之功用即在於分隔摻雜離 子區200與導電層204。 請參照第2B圖，於導電層204上方形成一內介電層 206，例如使用化學氣相沉積法形成。之後，定義內介電 層206，例如以習知之微影蝕刻技術，以導電層204爲蝕 刻終點，在內介電層206中形成一接觸窗口 208，暴露出 導電層204。 請參照第2C圖，之後於接觸窗口 208及內介電層206 之上再形成一層導電層210，例如以化學氣相沉積法沉積 一層摻雜離子之多晶砂(Doped Polysilicon)，爲防止導電層 210形成前，導電層204表面形成原始氧化物(NatWe Oxide) 而影響導電性，因此在沉積導電層210前先以氫氟酸淸洗 導電層204表面。 請參照第2D圖，接著，再對導電層210進行回蝕(Etch Back)的步驟，以非等向性飩刻(Amsotropic)，以絕緣層202 爲蝕刻終點，在接觸窗口 208側壁(Side Wall)形成一導電 層間隙壁（Spacer)210a，其中在回蝕進行的同時，亦蝕刻導 電層204，而暴露出絕緣層202，此一導電層210a間隙壁 作爲垂直電晶體之閘極。之後，再以氫氟酸進行一預淸洗 (Pre-Clean)的步驟。 8 (誚先閱讀背面之注意事項再填寫本頁) •裝- 訂 線 小‘氏依尺度城川屮因丨（（，NS ) Λ4規格（2丨0X297公犮） !4tvv f.doc/006 A7 B7 部 it x 消 /- ίΐ 社 印 五、發明説明（q) 再請參照第2Ε圖，對基底201形成一層氧化層覆蓋 住內介電層206、導電層間隙壁210a與暴露出的絕緣層 202，例如使用化學氣相沉積法，以當作電晶體之閘氧化 層212，例如HTO材質。再沉積一層通道層214，例如使 用化學氣相沉積法形成未摻有雜質之複晶矽層，以保護閘 氧化層212，同時此通道層214作爲電晶體之通道區域 (Channel Region) ° 請參照第2F圖，在通道層214上形成光阻216，並以 光阻216定義通道層214與絕緣層202，以形成汲極接觸 窗，而使摻雜離子區200暴露出。其中光阻之開口 218， 其內徑小於由閘氧化層212所形成圓筒狀側壁之內徑，以 確保後續在蝕刻絕緣層202上的通道層214時，不致過度 蝕刻而使閘氧化層212遭到破壞。 請參照圖第2G圖，接著，進行定義步驟，包括進行 蝕刻步驟，例如非等向性蝕刻，依續蝕刻通道層214、閘 氧化層212與絕緣層202，暴露出當作位元線的摻雜離子 區200,得到一汲極接觸窗口 219。接著，再移除光阻216。 在進行後續步驟前，先對基底進行一氫氟酸淸洗步驟。 請參照圖第2H圖，接著，對基底201形成一層半導 體層221，例如以化學氣相沉積法形成一多晶矽層，再對 多晶矽層進行回蝕步驟，使半導體層221至少塡入汲極接 觸窗口 219，通道層214連同半導體層221當作電晶體主 體223。再植入離子於電晶體主體223底部，形成一摻雜 離子之主體底部228，使其與摻雜離子區200相接觸之界 本紙张尺度適州中KPi!家標彳（（、NS ) Λ4規格（2丨0X297公釐） (却先閱讀背面之注意事項再填寫本頁) -裝· ,ιτ --線This paper recognizes the standard Kawasaki valve family standard {(, NS) Λ4 specification (210 × 297 males) 3524twf.doc / 006 A7 B7 V. Description of the invention (9) Figures 1A to 1C show the dynamics of knowledge A schematic cross-sectional view of a random access memory manufacturing process. Referring to FIG. 1A, a shallow trench isolation structure 102 is formed on a substrate 100, a gate oxide layer 104 and a gate electrode 106, and an active / drain is formed on the substrate 100 on the side of the gate electrode 106. Polar region 108. An oxide layer is then formed on the substrate 100 as the insulating layer 110 'and the insulating layer 110 is defined to form a contact window 112. Referring to FIG. 1B, a conductive layer 114 is formed on the insulating layer 110. The conductive layer 114 penetrates into the contact window 112 and is electrically coupled to one of the source / drain regions 108. Referring to FIG. 1C, the conductive layer 114 is further defined, a conductive layer 114a is formed, and a hemispherical silicon grain layer 115 (1 ^ 1 ^ -Sphencal Grain; HSG) is formed on the conductive layer 114a, and the contact window 112a, conductive The columnar structure formed by the layer 114a and the hemispherical silicon grain layer 115 serves as the lower electrode of the capacitor. Then, a dielectric layer 116 is formed on the hemispherical sand grain layer 115, and finally a conductive layer 118 is formed on the dielectric layer 116 as an electrode on the capacitor. In the above-mentioned manufacturing method of the conventional dynamic random access memory, it is limited by the limitation of the light source resolution of the existing lithography process and considering the alignment error, so that regardless of the gate width, the contact window opening size, and even the The distance between the gate and the contact window cannot be infinitely reduced. In addition, the bit lines, gates, and capacitors of the conventional dynamic random access memory are distributed in a plane, that is, the area occupied by a single memory cell is provided for both the transistor and the capacitor, so it is actually reduced. The area is also really limited. (诮 Please read the precautions on the back before filling in this page) • Outfit · Sweater · ::; Λ "屮 部 屮 喜 行行 局 T: o.-ir, 介 At: ir = il, w This paper 沭The standard Cheng Chuan threshold threshold sample ((, NS) Λ 4% grid (210X297 mm) 3 524twf.doc / 006 A7 B7 V. Description of the invention (f) In addition, the capacitors of the conventional dynamic random access memory are The contact window is electrically coupled to the source / drain of the word line, and the source / drain region is directly in contact with the substrate, so it is easy to cause junction leakage due to leakage current, so that the capacitor refresh cycle Increase, which affects the operating performance of the memory. Therefore, the main object of the present invention is to provide a method for reducing the area of the dynamic random access memory cell base area to improve the accumulation degree and avoid the conventional interface leakage and high frequency update Disadvantages such as cycle. In order to achieve the above and other objectives of the present invention, a structure and a manufacturing method of a dynamic random access memory having a vertical transfer transistor are developed. This type of dynamic random access memory includes a drain, a gate, and a source. The poles form a circle perpendicular to the capacitor The structure reduces the bottom area of the memory cell. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows : Brief description of the drawings:, Figures 1A to 1C are schematic cross-sectional views showing the manufacturing steps of the conventional dynamic memory access memory; and Figures 2A to 2] are drawings showing a preferred embodiment according to the present invention. A structure and manufacturing method of a dynamic random access memory with vertical transmission of exposed crystals. Method cross-section schematic diagram. · Marking of the diagram: 100, 201: Substrate 102: Shallow trench isolation structure. National prisoner's standard ((, NS) A4 specifications (2) × 297 mm) (诮 Please read the precautions on the back before writing this page) -Pack. 1T- -Line A7 B7 3524twf.doc / 006 V. Description of the invention (夂) 104, 212: gate oxide layer 106: gate electrode 1 + Ό8: source / drain region 110, 202: insulating layers 112, 112a, 208, 219: contact windows 114, 114a, 118, 204, 210 220, 226, 210a: conductive layers 115, 222: hemispherical silicon grain layer 200: doped ions Region 206: Internal dielectric layer 214: Channel layer 216: Photoresist 218: Opening 221: Semiconductor layer 223: Transistor body 116, 224: Dielectric layer 228: Ion-doped body. For a bottom example, please refer to Figure 2A ~ FIG. 21 is a schematic cross-sectional view illustrating a structure and a manufacturing method of a dynamic random access memory having a vertical transfer transistor according to a preferred embodiment of the present invention. Please refer to FIG. 2A. In FIG. 2A, a mask (not shown) is used to define the doped ion region 200 on the semiconductor substrate 201, and implanted ions, such as N + type impurities, to form a dopant as a bit line. Ion zone 200, doped ionic zone 7 This paper is ΑA standard this ^ house standard 彳 (('NS) Λ4 size (210X297 mm) i J ---------- install ----- ^-. 1T -------- line (谙 read the precautions before filling in this page) 3 524 twf.doc / 006 A7 B7 V. Description of the invention (6) 200 will be connected to the bit line A control circuit (not shown in the figure). Next, an insulating layer 202 is formed on the semiconductor substrate 201, for example, a chemical vapor deposition method is used, and then a conductive layer 204 is formed as a word line on the insulating layer 202, For example, a polycrystalline silicon layer or a polycide is deposited by chemical vapor deposition, and the function of the insulating layer 202 is to separate the doped ion region 200 from the conductive layer 204. Referring to FIG. 2B, a conductive layer 204 is formed above the conductive layer 204. The inner dielectric layer 206 is formed, for example, using a chemical vapor deposition method. Then, the inner dielectric layer 206 is defined, for example, by a conventional lithography technique, and The electrical layer 204 is the end point of the etching. A contact window 208 is formed in the inner dielectric layer 206 to expose the conductive layer 204. Please refer to FIG. 2C, and then a conductive layer is formed on the contact window 208 and the inner dielectric layer 206. 210. For example, a layer of doped polysilicon is deposited by chemical vapor deposition. In order to prevent the formation of the original oxide (NatWe Oxide) on the surface of the conductive layer 204 before the formation of the conductive layer 210, the conductivity is affected. Before depositing the conductive layer 210, first rinse the surface of the conductive layer 204 with hydrofluoric acid. Please refer to FIG. 2D, and then perform the Etch Back step on the conductive layer 210 to etch it with anisotropic (Amsotropic) A conductive layer spacer 210a is formed on the side wall of the contact window 208 with the insulating layer 202 as the end point of the etching. The conductive layer 204 is also etched at the same time as the etch-back is performed to expose the insulating layer 202. The gap between the conductive layer 210a is used as the gate of the vertical transistor. After that, a pre-cleaning step is performed with hydrofluoric acid. 8 (诮 Please read the precautions on the back before filling this page) • Outfit-Threading Small ' According to the standard Chengchuan 屮 丨 ((, NS) Λ4 specifications (2 丨 0X297 public 犮)! 4tvv f.doc / 006 A7 B7 Department it x 消 /-印 印 5. Description of the invention (q) Please refer to Section 2E again In the figure, an oxide layer is formed on the substrate 201 to cover the inner dielectric layer 206, the conductive layer spacer 210a, and the exposed insulating layer 202. For example, a chemical vapor deposition method is used as the gate oxide layer 212 of the transistor. For example, HTO material. An additional channel layer 214 is deposited. For example, a chemical vapor deposition method is used to form a polycrystalline silicon layer not doped with impurities to protect the gate oxide layer 212. At the same time, the channel layer 214 is used as a channel region of a transistor. ° Please refer to In FIG. 2F, a photoresist 216 is formed on the channel layer 214, and the channel layer 214 and the insulating layer 202 are defined by the photoresist 216 to form a drain contact window, and the doped ion region 200 is exposed. The inside diameter of the photoresist opening 218 is smaller than the inside diameter of the cylindrical sidewall formed by the gate oxide layer 212, so as to ensure that the channel oxide layer 214 on the insulating layer 202 is not etched in the subsequent etching and the gate oxide layer 212 is not over-etched. been destroyed. Please refer to FIG. 2G. Next, a definition step is performed, including an etching step, such as anisotropic etching, and the channel layer 214, the gate oxide layer 212, and the insulating layer 202 are sequentially etched to expose the dopants as bit lines. The hetero-ion region 200 obtains a drain contact window 219. Then, the photoresist 216 is removed. Prior to the subsequent steps, the substrate is first subjected to a hydrofluoric acid rinsing step. Please refer to FIG. 2H. Next, a semiconductor layer 221 is formed on the substrate 201. For example, a polycrystalline silicon layer is formed by a chemical vapor deposition method, and then the polycrystalline silicon layer is etched back to make the semiconductor layer 221 at least enter the drain contact window 219. The channel layer 214 and the semiconductor layer 221 serve as a transistor body 223. Ions are re-implanted on the bottom of the transistor body 223 to form a doped ion body bottom 228, which makes it in contact with the doped ion region 200. The paper size is KPi! Family logo 适 ((, NS) Λ4 Specifications (2 丨 0X297mm) (However, please read the precautions on the back before filling in this page)
"'•',r'部十决";''-^G-T消於合竹"印 V 3 524twf .doc/0 06 A7 ___B7_ 五、發明説明（》） 面電阻値降低，並藉由閘氧化層212與作爲字元線的導電 層204相隔離。 請參照第21圖，形成一層經摻雜離子而具導電性之 多晶矽層，例如以化學氣相沉積法，再定義此多晶矽層、 通道層214和閘氧化層212，例如以微影蝕刻之技術，以 形成導電層220，此導電層220即當作記憶胞之源極及電 容器之下電極主體。 到目前爲止，電晶體已製備已完成，其類似垂直薄膜 電晶體（Vertical Thin Film Transistor ; TFT)，汲極爲摻雜離 子區200，閘極爲導電層210a，源極爲導電層220。 請參照第U圖，接著，在當作電容器下電極主體的 導電層220表面上形成半球形矽晶粒層222，例如使用化 學氣相沉積法、材質例如爲矽，以增加下電極表面積，提 高電容器之電荷儲存量。之後，於半球形矽晶粒層222上 再形成一層介電層224,例如以化學氣相沉積法沉積一具 ◦ N0(氧化矽/氮化矽/氧化矽)三層結構之材質，作爲電容器 所必需之介電層224，其上再形成一層導電層226，例如 以化學氣相沉積法沉積一層多晶矽，以當作電容器之上電 極，如此則完成記憶胞之製作。 由上述本發明較佳實施例可知，應用本發明具有下列 優點。 (1)習知電容器位於電晶體側方時，單一記憶胞所佔基 底面積須提供給電晶體與電容器兩者使用，因此動態隨機 存取記億體所佔面積無法無限縮小。而本發明之電晶體之 I 0 ϋ張尺度述ϋΐ中K阀家彳( rNS ) Λ4规格(2丨0Χ 297公漦） -----------裝------訂-----T線 /H' (誚先閱讀背面之注意事項再填寫本頁) 3 524tvvf.doc/006 A7 __B7_ 五、發明説明（？） 汲極、閘極、源極與電容器於矽基底依序由下往上排列， 形成-·柱狀結構，因所佔底面積小，得以使積集度大幅增 加，故可符合達到元件縮小化且高積集度的目的。 (2) 完整之製程中所使用到光阻之次數少於傳統之方 法，因此製程上比習知的流程容易。 (3) 本發明垂直傳送電晶體，其電晶體通道層爲垂直 狀，源/汲極之一未與基底直接接觸，且電容器未經由導電 層與基底直接接觸，因此不會有電荷遺漏的問題，故可減 少電容的更新週期，藉而增進元件效能。 (4) 在本發明中，由於字元線、位元線與電容器爲垂直 向上排列在一接觸窗口中形成，因此接觸窗開口的高寬比 (Aspect Ratio)較習知爲小，而開口的触刻製程上較容易。 再加上主體底部摻有雜質，因此接觸窗與位元線的接觸電 阻値得以降低。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 _1_.---r---. — 裝------訂------線 (ti先閱讀背面之注意事項再續寫本頁) 部 if jj -Τ 消 本紙张尺度诚川中國闽家標H1 ( (’NS )八4规格（210X297公犛）" '•', r '部 十 决 "' '-^ GT Eliminates the need to make a seal &print; V 3 524twf .doc / 0 06 A7 ___B7_ 5. Description of the invention () The surface resistance 値 is reduced and borrowed The gate oxide layer 212 is isolated from the conductive layer 204 as a word line. Please refer to FIG. 21 to form a polycrystalline silicon layer which is doped with ions and is conductive, for example, by chemical vapor deposition, and then define the polycrystalline silicon layer, the channel layer 214 and the gate oxide layer 212, for example, using a lithography technique In order to form a conductive layer 220, the conductive layer 220 is used as the source of the memory cell and the electrode body under the capacitor. So far, the transistor has been prepared and is similar to a vertical thin film transistor (TFT). The drain electrode is doped with an ion region 200, the gate electrode is a conductive layer 210a, and the source electrode is a conductive layer 220. Please refer to FIG. U. Next, a hemispherical silicon grain layer 222 is formed on the surface of the conductive layer 220 serving as the lower electrode body of the capacitor. For example, a chemical vapor deposition method and a material such as silicon are used to increase the surface area of the lower electrode and increase Capacitor charge storage capacity. After that, a dielectric layer 224 is formed on the hemispherical silicon grain layer 222. For example, a material with a three-layer structure of N0 (silicon oxide / silicon nitride / silicon oxide) is deposited by chemical vapor deposition as a capacitor. The necessary dielectric layer 224 is further formed with a conductive layer 226. For example, a layer of polycrystalline silicon is deposited by a chemical vapor deposition method to serve as an electrode on a capacitor, and thus the production of a memory cell is completed. As can be seen from the above-mentioned preferred embodiments of the present invention, the application of the present invention has the following advantages. (1) When the capacitor is located on the side of the transistor, the base area occupied by a single memory cell must be provided for both the transistor and the capacitor. Therefore, the area occupied by the dynamic random access memory cannot be infinitely reduced. The I 0 scale of the transistor of the present invention is described in the K valve family (rNS) Λ4 specification (2 丨 0 × 297 mm) ----------- installation ------ Order ----- T line / H '(诮 Please read the precautions on the back before filling this page) 3 524tvvf.doc / 006 A7 __B7_ 5. Description of the invention (?) Drain, gate, source and capacitor The silicon substrates are sequentially arranged from the bottom to the top to form a columnar structure. Because the area occupied by the substrate is small, the accumulation degree can be greatly increased, so it can meet the purpose of reducing the size of the device and achieving a high accumulation degree. (2) The number of photoresist used in the complete process is less than the traditional method, so the process is easier than the conventional process. (3) In the vertical transmission transistor of the present invention, the transistor channel layer is vertical, one of the source / drain electrodes is not in direct contact with the substrate, and the capacitor is not in direct contact with the substrate through the conductive layer, so there is no problem of charge leakage. Therefore, the refresh period of the capacitor can be reduced, thereby improving component performance. (4) In the present invention, since the word line, the bit line, and the capacitor are formed vertically in a contact window, the aspect ratio of the opening of the contact window is smaller than conventional, and the opening It is easier to touch the process. In addition, the bottom of the main body is doped with impurities, so the contact resistance between the contact window and the bit line is reduced. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. _1 _.--- r ---. — Install ------ order ------ line (ti read the precautions on the back before continuing to write this page) mini if jj -T Sichuan China Min Family Standard H1 (('NS) 8 4 specifications (210X297 male)