TW440919B - The pattern transfer for polysilicon - Google Patents

Abstract

A pattern transfer method for polysilicon to form a polysilicon layer on the substrate. Then, form a pattern-transferred blocking layer on the polysilicon layer, and form a conformal silicon oxide layer on the blocking layer and the polysilicon layer. Then, etch the silicon oxide layer by anisotropic etch, so that a spacer can be formed on the silicon oxide by the blocking layer. The main feature of the present invention is to use the spacer as the etching mask. After removing the blocking layer, etch the polysilicon layer by using the spacer as the mask, remove the spacer finally.

Description

V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to pattern transfer in a semiconductor process, and in particular to pattern transfer in a polycrystalline silicon. 5-2 Background of the Invention: In the manufacturing process of integrated circuits It is often necessary to make extremely fine k-size patterns on a wafer. The most important way to develop these fine patterns is to use etching technology to transfer the photoresist patterns generated by photolithography (photol i thography), whether they are lines, faces or holes, and transfer them faithfully. To the complex structure of the integrated circuit under the photoresistor. Therefore, the etching process, which is collectively called the pattern transfer technology, occupies an extremely important position. The first picture in the semiconductor shows the transfer of the traditional polycrystalline silicon pattern: the structure diagram. First of all, ... A cuts 0 as shown in the figure, and forms a photoresist 0a on the substrate i 0 〇 polycrystalline silicon 12 2. = 1 2 0, and then the single-doped single material containing single crystal silicon, doped with 100%, usually with a crystal layer of 120, is usually used in m-based integrated circuit structure. Multi-resistance is formed in any suitable manner, i.e., by electro-chemical formation in integrated circuits, such as chemical vapor deposition. J Electric

Page 4 44919919 Five 'invention description (2) The photoresist layer, such as rotation, is exposed in the photoresist line, the photoresist of exposure B picture 0 is the mask, and the process of the square etching process needs to be removed. If you choose the negative picture, you can choose a negative film, which can be coated with 14 0 (layer 1 4 light pattern can be determined by 1 pair of polymorphs. Process, structure. The same feeling to apply to any appropriate spin coating) 〇 Put a photomask (photoresist layer 40). Silicon layer 1 is any kind of wet-type first photo-light material in semiconducting 1 4 0, and then the appropriate dry light at 20 There are many ways to get rid of the photoresist or the light shown. The standard is not to transfer the engraved engraved pattern from the developed pattern in the figure, such as cutting or layer 1 4 0 is a dry deblocking layer 1 4 negative. The pattern of the amorphous stone layer is turned to display) After the formation of the light, the first C wet etching passes through the photoresist, 0 is positive or positive 12 0 shift steps and then proceed as shown in the first resistance 1 4 circle, looking at any suitable formation Such as the film, then the film or the current product remains unique). Suppose that the finer and more semi-conducting leads to 0 · 1 8 have a sudden drop in demand. The same is true of integrated power. The method is to calculate the small size of the wire (M0S comes from a small, broken. Low cost can reduce the density of the road even Shrinking is continuous shrinking. Wide development ^) Transistors are directly lower in semiconductors. Continuously expanding small to continuously shrink the circuit The key lies in the current micro gate, the benefit of multi-body industrial fast small circuit design, and time reduction, in order to reduce the electrical design technology and technology. It is not small to make the chip road to single cell (des development point of view, the line width is large today, but for the cost of the line width (chip) surface level, whether the i gn rule can be reduced to the metal oxide can be reduced to see if the semiconductor process voltage of

丨 4 40 9 1 9 V. Explanation of the invention (4) The first diagram A to the second diagram f are schematic diagrams of the steps in the polycrystalline broken pattern transfer according to the technique disclosed in the present invention. Representative symbols of main parts: 1 0 substrate 2 0 polycrystalline silicon layer 3 0 metal silicide 4 0 photoresist layer 5 0 silicon oxide layer 5 2 interlayer wall 1 0 0 substrate 1 2 0 polycrystalline silicon layer 1 4 0 photoresist layer 5-5 Detailed description of the invention: ^ The semiconductor device of the invention can be applied to semiconductor devices in a wider range and can be made of different semiconductor materials. Because the current call is too respectful to produce the body parts on the Shi Xi substrate. The following statement will be :: shovel; 1 an example of the application of silicon as a substrate on a semiconductor device.廇 uses its + t for 1U 1 · Used on Shi Xi substrate. However, the present invention can also be applied to the development of other materials, such as gallium arsenide. Therefore, the ^ of the present invention is limited to components made of stone salt @ semiconductor material, but includes

η 440 9 1 9 V. Description of the invention (5) On components made of other semiconductor materials. Moreover, the embodiment of the present invention is shown but the illustration of the present invention is not a 彳 α 'non-limiting # is used to limit the present invention and does not intend to make the semiconductor of the present invention through this. The following description shows that the different parts of the semiconductor device according to the preferred embodiment of the present invention have not been exaggerated in comparison with other relevant dimensions, the description of the description and the understanding of the present invention. Furthermore, although the embodiment of the day here is different from the one shown in the two-dimensional section, it should be clearly understood that the domain is only a part of the three-dimensional unit cell of the wafer (ce 丨 丨), including many in three-dimensional space. Aligned unit cells. In the case of a relatively element, the illustrated area has a three-dimensional length. The width and line width formed by traditional lithography are limited by the shorter wavelength of the light source, which provides better resolution. However, in the long-term reform, "the current photoresist cannot be used, and it must be invented to provide a kind of lithography technology." But the line width of the military curtain with the current system can be reduced to 0.1 micron will The scope of application of the semiconductor device of the present invention will be described in detail with the aid of FIG. The architecture shown. This is used and applied. Drawing by the size. In order to provide clearer width and depth in the area shown, where the wafer may be in actual manufacturing height and height. The wavelength of the source and the light's are developed separately as the wave of the light source. This process equipment is compatible with the following. Next-an embodiment. 440919 V. Description of the invention (6) If the second one is to form a plurality of silicide layers 10 in order, then it may be formed in an integrated manner. sa1i c i de) compound 13 gold semiconductor semiconductor electrolyte. If the metal silicide polycrystalline silicon is shown in Figure A, the crystalline silicon layer is 30 times higher, the structure of the metal silicon process is a silicidated crystal. However, the case transfer shows that providing a base 20 with a metal forms a common package. The polycrystalline layer is formed, and the gate crystalline silicon of the physical layer 3 is. The present invention has no effect. It contains a single silicon layer 2 3 0 and the material 0 is not. Generally, the integrated circuit does not matter. Material 1 0 The dream of silicide, 0, is usually based on whether the titanium is necessary in the multi-channel electricity, whether the bottom 30 barrier layer is doped with any self-silicide compound, but the crystal When the resistance is cut, the monocrystalline stone above the metal silicon material 10 and the gold 40 β substrate is traditionally deposited with a quasi-silicide (a material or a crane stone) in the metal oxidation to form a metal without forming a compound. For the barrier layer 40 in the present invention, the simplest is to use silicon nitride during the etching process. It is formed in a pattern conformal oxygen deposition method, such as in anisotropic (anisotropic structure such as the second wall 52). The present invention Carved polycrystalline silicon layer 2 The barrier layer 40 is traditionally passed here through the traditional single barrier layer 4 0 is a barrier layer with a high transfer between silicon oxide 4 0 The sand layer 50 0. The oxide gas phase Deposition method, followed by sotropical ly) dry etching, as shown in Figure C. The main purpose of the resist layer is to remove it with metal silicide 30 to form a photoresist such as photolithography. Forming layer 50 can go down to the side of 4 0 in the oxygen etch. Spacer mask. Formed after the second D picture. However, as long as it is, it can be conformal (using a conventional silicon layer 50 I insect etched, etching the edge to form a gap 5 2 as an etch down, will block the structure.

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440 9 1 9

The material of the layer 4 G is the photoresist '% removed in a conventional wet manner. The material of the barrier layer 40 is a dry-type method (P3). ㈣Right nitrogen cutting, then use the acid immersion tank next to the partition wall 5 2 as a mask, and sequentially etch the polycrystalline silicon layer 20, as shown in the first F picture *: No. Metal silicide] η is etched by traditional etching methods, such as Α 龄 1e 成 —Α ^ υ υ / 挪 Nuo engraving, such as HCL etching in an ion reaction chamber etching machine (R E). The polycrystalline silicon layer 20 is etched by any conventional dry etching method. Finally, the spacer 5 2 is removed by any conventional dry etching method, as shown in the second F diagram. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

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Claims (1)

44η 9 1 9 Patent scope Transfer method A pattern of polycrystalline silicon provides a substrate; the method includes at least: forming a layer on the substrate ~ forming a gap on the polycrystalline silicon layer between the barrier layer and the side of the polyisotropic etching method A polycrystalline silicon layer; a pattern-transferred barrier layer; a conformal silicon oxide layer formed on the crystalline silicon layer; etching the silicon oxide layer so that the barrier layer is removed from the barrier; etching the polycrystalline silicon layer; and The gap wall is used as a mask to remove the gap wall. 2. Form a metal silicide as described in item 1 of the patent application. The method 'includes the method on the polycrystalline silicon layer as in item 2 of the patent application, wherein the above-mentioned metal stone is formed by self-aligning the metal silicide 4. The method as in item 2 of the patent application' is removing the The barrier layer includes the barrier wall as a cover, and the metal silicide layer is left with: 5 method of resisting the application of the scope of the patent No. 1 'where the above-mentioned barrier layer is light 6. If the patent application allows 5 of the Method 'wherein the photoresist layer is removed Page 11 44〇9t 9 VI. The method of applying for the patent scope includes the dry photoresist method or the wet photoresist method. The above barrier layer is nitrogen. 7. As for the method in the first item of the patent scope, the fossil layer . A method for pattern transfer of polycrystalline silicon, the method at least comprises: providing a substrate; forming a polycrystalline silicon layer on the substrate; forming a metal silicide layer on the polycrystalline silicon layer; forming a pattern transfer on the metal oxide layer A photoresist layer; a conformal silicon oxide layer is formed on the 4 photoresist layer and the metal silicide layer; the silicon oxide layer is etched by an anisotropic etching method so that the sides of the photoresist layer Forming a barrier wall; removing the photoresist layer; using the 4 barrier wall as a mask, to sequentially etch the metal oxide layer and the polycrystalline stone layer; and removing the barrier wall a 10, as in the Shen-Hao patent The method of the ninth item, wherein the above-mentioned metal silicide is formed by self-aligning the metal silicide. Page 12 440919 VI. Scope of Patent Application 11 ‘The method of claim 9 in the patent application scope, wherein the method for removing the photoresist layer includes a dry photoresist method or a wet photoresist method. 12. A method for pattern transfer of polycrystalline silicon, the method at least comprising: providing a substrate; forming a polycrystalline silicon layer on the substrate; forming a metallic stone material layer on the polycrystalline silicon layer; Forming a pattern-transferred silicon nitride layer on the metal silicide layer; forming a conformal silicon layer on the silicon nitride layer and the metal silicide layer; using an anisotropic etching method to the oxide oxide layer Engraving so that a gap wall is formed on the side of the silicon layer; removing the silicon nitride layer; sequentially etching the metal silicide layer and the polycrystal with the gap wall as a mask silicon layer; and removing the gap wall. 13. The method according to item 12 of the scope of patent application, wherein the above-mentioned metal silicide is formed by self-aligning the metal silicide. 14. The method according to item 12 of the patent application scope, wherein the method for removing the silicon halide layer includes at least an ion reactive etching method. Page 13