KR960002554A - Gate electrode formation method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode of a semiconductor device. In order to solve the problem that a gate line having a fine line width required in an ultra-high integration device cannot be formed by a lithography process using a photosensitive film in the prior art, a polycrystal for a gate electrode is used. By depositing a polysilicon film on top of the silicon film and rapidly isotropic etching using a gate electrode mask, a polysilicon film pattern of less than a quarter micrometer is formed, and then a gate electrode having a fine line width is formed by a mask process using the polysilicon film pattern. Formation is a technology that improves the productivity and reliability of semiconductor devices and enables ultra-high integration of semiconductor devices.

Description

Gate electrode formation method of semiconductor device

As this is a public information case, the full text was not included.

1A to 1C are cross-sectional views showing a gate electrode forming process of a semiconductor device according to the prior art;

2A to 2C are cross-sectional views showing a gate electrode forming process of a semiconductor device according to an embodiment of the present invention.

Claims (4)

A method of forming a gate electrode of a semiconductor device, comprising: sequentially depositing a gate oxide film, a polycrystalline silicon film for a gate electrode, an interlayer insulating film, and a polysilicon film on a semiconductor substrate, and forming a gate electrode mask thereon; Forming a polysilicon film pattern by etching the polysilicon film by a dry method using a dry method, and removing the gate electrode mask; and using the quarter micrometer or less polycrystalline silicon film pattern formed by the etching process as a mask. And forming a gate electrode and a gate oxide layer pattern by performing an entire surface etching process using the interlayer dielectric pattern as a mask and an etching barrier. The method of claim 1, wherein the gate electrode mask is removed using an oxygen plasma. The method of claim 1, wherein the dry method is performed using a chemical gas based on SF ₆ or Cl ₂ / SF ₆ gas. The method of claim 1, wherein the etching of the interlayer dielectric layer is performed by using an etching selectivity difference between the oxide layer forming the interlayer dielectric layer and the polysilicon layer pattern. ※ Note: The disclosure is based on the initial application.