KR0131718B1 - Gate pole formation method - Google Patents
Gate pole formation methodInfo
- Publication number
- KR0131718B1 KR0131718B1 KR1019940014569A KR19940014569A KR0131718B1 KR 0131718 B1 KR0131718 B1 KR 0131718B1 KR 1019940014569 A KR1019940014569 A KR 1019940014569A KR 19940014569 A KR19940014569 A KR 19940014569A KR 0131718 B1 KR0131718 B1 KR 0131718B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- pattern
- tungsten layer
- forming
- mask
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 28
- 239000010937 tungsten Substances 0.000 claims abstract description 28
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 230000009977 dual effect Effects 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 5
- 238000001459 lithography Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000011056 performance test Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 150000003657 tungsten Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
Abstract
Description
제1a도 내지 제1c는 종래시술에 의한 반도체소자의 게이트전극 형성공정을 도시한 단면도.1A to 1C are cross-sectional views showing a gate electrode forming process of a semiconductor device by a conventional procedure.
제2a도 내지 제2c도는 본 발명의 실시예에 의한 반도체소자의 게이트 전극 형성공정을 도시한 단면도.2A to 2C are cross-sectional views showing a gate electrode forming process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 명칭* Names of symbols for main parts of the drawings
1,11 : 게이트산화막 2 : 게이트산화막1,11 gate oxide film 2: gate oxide film
3,13 : 게이트전극용 다결정실리콘막 4 : 게이트전극3,13 polycrystalline silicon film for gate electrode 4: gate electrode
5 : 감광막 7 : 층간절연막5: photosensitive film 7: interlayer insulating film
7' : 층간절연막 9,17' : 게이트전극 마스크7 ': interlayer insulating film 9,17': gate electrode mask
13' : 게이트전극용 다결정실리콘막패턴 15 : 텅스텐층13 ': polysilicon film pattern for gate electrode 15: tungsten layer
15' : 텅스텐층패턴 17 : 감광막패턴15 ': tungsten layer pattern 17: photoresist pattern
20,30 : 반도체기판20,30: semiconductor substrate
본 발명은 반도체소자의 게이트전극 형성방법에 관한 것으로, 특히 게이트전극용 다결정실리콘막 상부에 텅스텐을 일정두께 증착하고 마스크공정으로 텅스텐 삭각시 MERIE(Magnetically Enhanced Reactive Ion Etching) 장비로 SF6/ Cl2플라즈마 분위기의 특정조건하에서 감광막의 측벽식각을 주로 이용함으로써 기존 0.5 ㎛ 폭의 감광막을 이용하여 텅스텐 / 게이트전극용 다결정실리콘막의 이중구조를 갖는 0.1㎛ 폭의 게이트전극 형성에 관한 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode of a semiconductor device, and in particular, to deposit a certain thickness of tungsten on a polysilicon film for a gate electrode, and to remove tungsten by a mask process, using a MERIE (Magnetically Enhanced Reactive Ion Etching) device with SF 6 / Cl 2 By using sidewall etching of the photoresist film under specific conditions of the plasma atmosphere, a technique for forming a gate electrode having a width of 0.1 μm having a double structure of a polysilicon film for tungsten / gate electrodes using a photoresist film having a width of 0.5 μm is conventional.
일반적으로 종래의 리소그래피 기술로 형성하는 최소선폭의 크기는 0.3㎛를 그 한계로 보고 있으며 그 이하의 크기를 갖는 미세선폭은 엑스레이(X-ray) 또는 이빔(E-beam) 장치를 사용해야만 형성할 수 있어 생산단가를 상승시킨다. 반그로인하여, 반도체소자의 생산성을 저하시키는 문제점을 발생시킨다.In general, the minimum line width formed by the conventional lithography technique is considered to be 0.3 μm, and a fine line width having a size smaller than that can be formed only by using an X-ray or an E-beam device. It can raise the production cost. This causes the problem of lowering the productivity of the semiconductor device.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1c도는 종래기술에 의한 반도체소자의 게이트전극 형성공정을 도시한 단면도이다.1A to 1C are cross-sectional views showing a gate electrode forming process of a semiconductor device according to the prior art.
제1a도는 반도체기판(20) 상부에 게이트산화막(1), 게이트전극용 다결정실리콘막(3) 및 층간절연막(7)을 순차적으로 증착한 다음, 그 상부에 감광막(5)을 도포한 것을 도시한 단면도로서, 상기 층간절연막(7)은 산화막으로 형성한 것이다.FIG. 1A shows that the gate oxide film 1, the polysilicon film 3 for the gate electrode 3 and the interlayer insulating film 7 are sequentially deposited on the semiconductor substrate 20, and then the photoresist film 5 is applied thereon. As a cross-sectional view, the interlayer insulating film 7 is formed of an oxide film.
제1b도는 노광마스크(도시안됨)을 이용하여 상기 감광막(5)을 식각하여 감광막패턴, 즉, 게이트전극 마스트(9)를 형성한 것을 도시한 단면도로서, 상기 게이트전극 마스크(9)는 리소그래피 기술에 의하여 최소선폭으로 형성한 것이다.FIG. 1B is a cross-sectional view illustrating the formation of a photoresist pattern, that is, a gate electrode mast 9 by etching the photoresist film 5 using an exposure mask (not shown). The gate electrode mask 9 is a lithography technique. By forming the minimum line width.
제1c도는 상기 게이트전극 마스크(9)를 이용한 마스크 공정으로 층간절연막패턴(7'), 다결정실리콘막패턴, 즉 게이트전극(4)과 게이트산화막패턴(2)을 형성한 다음, 상기 게이트전극 마스크(9)을 제거함으로써 게이트전극을 형성한 것을 도시한 단면도이다.FIG. 1C illustrates an interlayer insulating film pattern 7 ′, a polysilicon film pattern, that is, a gate electrode 4 and a gate oxide film pattern 2, is formed by a mask process using the gate electrode mask 9. It is sectional drawing which shows that the gate electrode was formed by removing (9).
상기한 종래기술에 의하면, 감광막을 이용하여 게이트전극을 형성하는데 리소그래피 공정으로 형성할 수 있는 최소선폭보다 작은 선폭을 필요로하는 256 M DRAM와 같은 초고집적소자에서의 미세선폭을 형성할 수가 없기 때문에 별도의 장비와 공정을 이용하여 상기 미세선폭을 형성함으로써 생산단가를 상승시켜 반도체소자의 생산성을 저하시킨다.According to the above-mentioned prior art, since the fine electrode width cannot be formed in an ultra-high density device such as 256 M DRAM which requires a line width smaller than the minimum line width that can be formed by the lithography process to form the gate electrode using the photosensitive film. By using the separate equipment and process to form the fine line width to increase the production cost lowers the productivity of the semiconductor device.
따라서, 본 발명은 종래 리소그래피 기술의 한계성을 극복하기 위하여, 게이트전극용 다결정실리콘막 상부에 텅스텐층을 형성한 다음, 그 상부에 게이트전극을 형성하기 위한 감광막패턴을 형성하고 SF6/ Cl2플라즈마 분위기에서 감광막패턴과 텅스텐층을 동시에 식각하되 상기 감광막패턴과 텅스텐층의 수직방향 식각은 억제하고 수평방향으로 식각하여 형성한 게이트전극 마스크와 텅스텐패턴을 이용하여 게이트전극을 형성하는 반도체소자의 게이트전극 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to overcome the limitations of the conventional lithography technique, a tungsten layer is formed on the polysilicon film for the gate electrode, and then a photoresist pattern for forming the gate electrode is formed on the SF 6 / Cl 2 plasma. A gate electrode of a semiconductor device which forms a gate electrode using a tungsten pattern and a gate electrode mask formed by simultaneously etching a photoresist pattern and a tungsten layer in an atmosphere, but suppressing vertical etching of the photoresist pattern and the tungsten layer in a horizontal direction. The purpose is to provide a formation method.
이상의 목적을 달성하기 위한 본 발명의 특징은, 반도체기판 상부에 게이트산화막, 게이트전극용 다결정실리콘막 및 텅스텐층을 일정두께 증착하고 그 상부에 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로하여 일정 력 이상의 플라즈마 분위기에서 MERIE 장비를 이용한 건식방법으로 게이트전극 마스크와 텅스텐패턴을 형성하는 공정과, 상기 게이트전극 마스크와 텅스텐층패턴을 이용하여 상기 게이트전극용 다결정실리콘막을 식각하고 상기 게이트전극 마스크를 제거함으로써 텅스텐패턴과 게이트전극용 다결정실리콘막패턴의 이중구조로 게이트전극을 형성하는 공정을 포함하는 데 있다.A feature of the present invention for achieving the above object is a process of depositing a gate oxide film, a polysilicon film for a gate electrode, and a tungsten layer on a semiconductor substrate to a predetermined thickness, and forming a photoresist pattern on the top, and using the photoresist pattern as a mask Forming a gate electrode mask and a tungsten pattern by a dry method using a MERIE device in a plasma atmosphere having a predetermined force or more, and etching the gate silicon polysilicon film using the gate electrode mask and the tungsten layer pattern to form the gate electrode mask And forming a gate electrode with a double structure of a tungsten pattern and a polysilicon film pattern for the gate electrode by removing the?.
이하 첨부된 도면을 참고로하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2c도는 본 발명의 실시예로서 반도체소자의 게이트전극 형성공정을 도시한 단면도이다.2A to 2C are cross-sectional views showing a gate electrode forming process of a semiconductor device as an embodiment of the present invention.
제2a도는 반도체기판(30) 상부에 게이트산화막(11), 게이트전극용 다결정실리콘막(13) 및 텅스텐층(15)을 순차적으로 증착하고 그 상부에 게이트전극용 감광막패턴(17)을 형성한 것을 도시한 단면도로서 상기 감광막패턴(17)은 폭을 0.5㎛로 형성한 것이다.2A shows a gate oxide film 11, a polysilicon film 13 for gate electrode 13 and a tungsten layer 15 sequentially deposited on the semiconductor substrate 30, and a photoresist film pattern 17 for a gate electrode formed thereon. The photosensitive film pattern 17 is formed to have a width of 0.5 占 퐉.
제2b도는 상기 감광막패턴(17)을 마스크로하여 상기 텅스텐층(15)을 식각한 것을 도시한 단면도로서, 상기 식각공정은 400 m Torr 이상, SF6/ Cl2플리즈마 분위기에서 실시함으로써 수직방향의 식각을 억제하고 수평방향의 식각을 진행시켜 상기 감광막패턴(17)과 텅스텐층(15)을 측면 식각함으로써 0.1 ㎛의 게이트전극 마스크(17')와 텅스텐층패턴(15')을 형성한 것을 도시한 단면도이다.FIG. 2B is a cross-sectional view illustrating the etching of the tungsten layer 15 using the photoresist pattern 17 as a mask, wherein the etching process is performed in a SF 6 / Cl 2 plasma atmosphere of 400 m Torr or more and in a vertical direction. The gate electrode mask 17 'and the tungsten layer pattern 15' having a thickness of 0.1 µm were formed by lateral etching of the photoresist pattern 17 and the tungsten layer 15 by suppressing the etching of the photoresist. It is sectional drawing.
제2c도는 상기 게이트전극 마스크(17')와 텅스텐층패턴(15')을 이용하여 상기 게이트전극용 다결정실리콘막(13)을 식각하고 상디 게이트전극 마스트(17')를 제거함으로써 텅스텐층패턴(15')가 게이트전극용 다결정실리콘막패턴(13')의 이중구조로 0.1㎛의 폭을 갖는 게이트전극을 형성한 것을 도시한 단면도로서, 상기한 본 발명에 의하면, 별도의 장비 또는 공정기술없이 식각가스를 이용한 건식방법으로 초고집적화된 반도체소자의 게이트전극을 형성함으로써 256 메가 디램(M DRAM) 이나 1 기가 디램(G RAM) 트랜지스터 제작 및 성능 테스트를 가능하게 하여 반도체소자의 신뢰성 및 생산성을 향상시킬 수 있다.FIG. 2C illustrates the etching of the polysilicon film 13 for the gate electrode using the gate electrode mask 17 'and the tungsten layer pattern 15' and removing the top gate electrode mask 17 'to remove the tungsten layer pattern ( 15 ') is a cross-sectional view showing a gate electrode having a width of 0.1 [mu] m in a double structure of the polysilicon film pattern 13' for the gate electrode, according to the present invention described above, without any additional equipment or process technology. Improved reliability and productivity of semiconductor devices by enabling the fabrication and performance test of 256 mega DRAM (M DRAM) or 1 Giga DRAM (G RAM) transistors by forming gate electrodes of highly integrated semiconductor devices by dry method using etching gas. You can.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940014569A KR0131718B1 (en) | 1994-06-24 | 1994-06-24 | Gate pole formation method |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019940014569A KR0131718B1 (en) | 1994-06-24 | 1994-06-24 | Gate pole formation method |
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| KR960002574A KR960002574A (en) | 1996-01-26 |
| KR0131718B1 true KR0131718B1 (en) | 1998-04-14 |
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| KR1019940014569A KR0131718B1 (en) | 1994-06-24 | 1994-06-24 | Gate pole formation method |
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| KR (1) | KR0131718B1 (en) |
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