JPS6362351A - Patterning method of polycrystalline silicon layer - Google Patents

Abstract

PURPOSE:To facilitate the covering of a step on a film, which is formed on a polysilicon pattern, by sequentially growing a polycrystalline silicon layer and a metal layer on a substrate, and forming a polycrystalline silicon pattern having a trapezoidal cross section by plasma etching, with a resist pattern, which has the cross section of a rectangular form or an inverted trapezoidal form, as a mask. CONSTITUTION:On a substrate 1, a polysilicon layer 2 and a metal layer 3 are grown by a CVD method. A resist pattern, whose side surface is approximately vertical, is formed on a polysilicon pattern forming region by using an ordinary lithography method. With the resist pattern 4 as a mask, the metal layer 3 and the polysilicon layer 2 are etched by using a plasma etching method. Then the formed pattern has a trapezoidal shape. Thus the covering of a step on a film, which is formed thereon, is readily formed. Wire breakdown faults in, e.g., an aluminum interconnection, do not occur.

Description

[Detailed Description of the Invention] [Summary] In order to form a polycrystalline silicon (polySi) pattern with a trapezoidal cross-sectional shape, the resist pattern is made into a [r] rectangle or inverted trapezoid, and plasma etching is performed with a metal layer in between. A process of improving the step coverage and removing the polySt sidewalls remaining at the steps of the removed region of this layer when forming the upper polySt pattern (a step essential for conventional rectangular cross-section patterning) omitted.

[Industrial application field]

The present invention relates to a method for patterning a poly-Si layer to form a trapezoidal cross-sectional shape.

Poly-Si layers heavily doped with conductive impurities are often used as conductive layer patterns for FET gate electrodes, DRAM cell capacitor storage electrodes, cell plates, etc. in ST devices, and are multilayered on substrates with interlayer insulating layers in between. Often formed into structures.

[Conventional technology]

A conventional polySt pattern has a nearly rectangular cross-sectional shape.

FIGS. 3(1) to 3(5) are cross-sectional views schematically explaining a conventional method of patterning a poly-Si layer.

In FIG. 3(1), poly 5iJ32 is grown by chemical vapor deposition (CVD) on a base 1 such as silicon dioxide (SiO□)N formed on a silicon (Si) substrate.

Next, a resist pattern 4 is formed in the poly-Si pattern forming area using ordinary lithography.

In FIG. 3(2), using the resist pattern 4 as a mask, reactive ion plasma etching (RIP) is performed.
The poly-Si layer 2 is etched using plasma etching such as E).

FIGS. 3(2) to 3(5) show the progress of etching as the etching time elapses.

[Problem that the invention seeks to solve]

Since the conventional poly-Si pattern is formed with a nearly rectangular cross-sectional shape, it is difficult to cover the steps with a film formed thereon, resulting in disconnection of aluminum (At) wiring, for example.

Further, when patterning the upper poly-Si layer, an isotropic etching step was required to remove the sidewall made of poly-St remaining at the step in the area where this layer was removed.

[Means for solving problems]

The solution to the above problem is to sequentially grow a polycrystalline silicon layer and a metal layer on a base, form a resist pattern with a rectangular or inverted trapezoidal cross-section on top of the polycrystalline silicon layer, and use the resist pattern as a mask to layer the metal layer. This is achieved by a polycrystalline silicon layer patterning method in which the polycrystalline silicon layer is plasma etched to form a polycrystalline silicon pattern having a trapezoidal cross-sectional shape.

[Effect]

In the present invention, when patterning a poly-Si layer by plasma etching, (1) sandwiching a metal layer such as tungsten or molybdenum (Mo) IL! between the resist pattern and the poly-Si layer; (2) changing the shape of the resist pattern. This is based on the experimental finding that the cross-sectional shape of a poly-Si pattern can be made trapezoidal by making it rectangular or inverted trapezoidal.

Regarding (2), the etching process of the present invention will be explained in comparison with the conventional example shown in FIG.

FIGS. 1 (1) to (5) are cross-sectional views schematically illustrating the method of patterning a poly-Si layer of the present invention.

In FIG. 1(1), a poly-Si layer 2 and a metal layer 3 are grown on a base 1 by CVD.

Next, a resist pattern 4 whose side surfaces are substantially perpendicular to the poly-Si pattern formation region is formed using normal lamination lithography.

In FIG. 1(2), using the resist pattern 4 as a mask, the metal layer 3 and poly 5i are etched using plasma etching.
Etch i2.

FIGS. 1(2) to 1(5) show the progress of etching as the etching time elapses.

The pattern formed as shown in the figure has a trapezoidal cross section.

The reason why it becomes trapezoidal is not well understood, but the first
In the subsequent etching of the poly-Si layer 2 shown in FIG. It will be done.

Regarding (2), changes in the cross-sectional shape of the poly-Si pattern depending on the cross-sectional shape of the resist pattern were investigated as shown in FIG. 2 below.

FIGS. 2(1) to 2(3) are cross-sectional views of poly-Si patterns whose cross-sectional shapes correspond to a trapezoid, a rectangle, and an inverted trapezoid, respectively.

When the cross-sectional shape of the resist pattern in FIG. 2 (1) is trapezoidal, the cross-section of the poly-Si pattern is also formed close to a substantially rectangular shape; It can be seen that in the case of an inverted trapezoid, the cross section of the poly-Si pattern is formed into a trapezoid.

In addition, the resist pattern with a rectangular cross-sectional shape and an inverted trapezoid is
It is obtained by exposing multiple layers of resist with different sensitivities.

〔Example〕

An embodiment of the present invention will be described with reference to FIG.

In FIG. 1 (1), SiO□ formed on a Si substrate
A poly-Si layer 2 with a thickness of 2,000 thick and a tungsten silicide (WSi) layer 3 with a thickness of 2,000 thick as a metal layer are formed on a base 1 such as a layer by the CVD method.

Next, a resist pattern 4 having a thickness of 1 μm and having side surfaces substantially perpendicular to the poly-Si pattern forming region is formed using normal lamination lithography.

In FIGS. 1(2) to (5), using the resist pattern 4 as a mask, the WSi layer 3 is etched using plasma etching.
and etching poly5iJi2.

The pattern thus formed has a trapezoidal cross section.

The conditions for plasma etching are as follows.

■ Quasi-anisotropic etching Using SF5 + CzCIFs (Freon 115) as the etching gas, it was depressurized to 0.2 Torr and a power with a frequency of 13.56 MIIz was applied to the substrate light or 100-
Apply and etch for about 60 seconds.

In this case, anisotropic etching that is predominant in the vertical direction and a slight isotropic etching are performed, and the base of the trapezoid in the cross section of the poly-Si layer 2 widens.

The expansion width d of the base was approximately 3,000 people.

■ Completely anisotropic etching Using CCl40□ as the etching gas,
, the pressure is reduced to 15 Torr, and a power with a frequency of 13.56 MHz is applied to the substrate for about 60 seconds.

In this case, only anisotropic etching is performed that is predominant in the vertical direction, and the base of the trapezoid in the cross section of the poly-Si layer 2 expands to
Less than.

The expansion width d of the base was approximately 2,000 people.

In the subsequent steps, the resist pattern 4 is peeled off using a stripping solution, and the WSi layer 3 is etched and removed with aqua regia to complete a poly-Si pattern.

Although WSi was used as the metal layer in the example, similar results were obtained when other metals such as MoSi were used instead.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the Bo'JSi
By tapering the pattern, the following effects can be expected for devices using a multilayer poly-Si layer formation process.

(2) It becomes difficult to easily cover the steps of the film formed on the poly-Si pattern, and prevents breakage of the F1 wiring, for example.

(2) The gap between poly-Si patterns in the same layer can be made finer by the amount of Taber, which further contributes to flattening the substrate and improves lithography accuracy.

■ The isotropic etching process for removing the poly-Si sidewalls remaining at the steps in the region where this layer is removed during patterning of the upper poly-SiH layer is omitted, making it easier to manage the width of the upper poly-Si layer. , process defects due to sidewall residue are eliminated.

[Brief explanation of drawings]

1 (1) to (5) are cross-sectional views schematically explaining the poly-SiN patterning method of the present invention, and FIG. A cross-sectional view of a poly-Si pattern corresponding to an inverted trapezoid, and FIGS. 3 (1) to (5) are cross-sectional views schematically explaining a conventional patterning method for poly S[J. In the figure, 1 is Underlayer, 2 is poly-SiN, 3 is metal layer,
4 is resist pattern $1 factor sheep 3 figure AA figure

Claims (1)

[Claims] A polycrystalline silicon layer and a metal layer are sequentially grown on a base, a resist pattern having a rectangular or inverted trapezoidal cross section is formed thereon, and the metal layer and the polycrystalline silicon layer are grown using the resist pattern as a mask. A method for patterning a polycrystalline silicon layer, the method comprising forming a polycrystalline silicon pattern having a trapezoidal cross-sectional shape by plasma etching.