200913167 pt.ap897 25003twf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導 種非揮發性記憶體的製造方法。衣王，且特別是有關於一 【先前技術】 非揮發性記憶體元件因呈 之優點’因此其已成為為個人電腦和;==存 的一種記憶體元件。 于。又備所廣泛採用 典型的非揮發性記憶體元件， 疊式閑極結構，其中包括以摻雜 金屬石夕化物組成)所製作的控制·(e 3 ^ 閘極和基底之間，並處於浮置狀 何電路相連接。而控制閘極則與字树相連接。此外，浮 =極與控制閘極之間還包括賴介電層， 基底之間更包括穿隧介電層。 /、 然而，隨著半導體製程技術的快速發展，為了增進元 件的速度與效能’整個電路_集度賴持續地提升，元 2的尺寸S而必須不斷縮小。—般來說，縮小元件尺寸會 k成材質為多晶矽化金屬的控制閘極之片電阻（让e的 resistance)升高，而降低元件的操作速度。此外，當元件尺 寸縮減時，閘極結構的表面平整度以及晶粒尺寸大小亦會 200913167 pt.ap897 25003twf.doc/p 對片電阻造成影響。 目前所採用作為控制閘極材料的金屬矽化物通常為 矽化鎢(WSix)’其在高溫環境下容易產生w_〇_Si複合物， 而造成閘極結構變形，如圖1A至圖1C所示，其繪示習知 之一種非揮發性記憶體的部分製造流程剖面示意圖。 請參照圖1A，提供矽基底100,矽基底100具有記憶 胞區102以及周邊電路區1〇4。在記憶胞區1〇2之矽基^ C' 1〇0上已形成有閘極結構132與頂蓋層122,且在周邊電路 區1〇4之矽基底1〇0上已形成有閘極結構134。閘極結構 132是由矽化鎢層12〇、摻雜多晶矽層118、閘間介電層 116、摻雜多晶矽層114與穿隧介電層112所組成。矽化^ 層U0與摻雜多晶石夕層118共同作為記憶體的控制閑極， ，摻雜多晶矽層114作為記憶體的浮置閘極。閘極結構134 疋由導體層124與閘極氧化層11〇所組成。導體層124是 作為電晶體之閘極。接著，於周邊電路區1〇4之矽基底1〇〇 , 上形成圖案化光阻層128，以暴露出記憶胞區1〇2。一 、 請參照@ 1B，以圖案化光阻層128為罩幕，進行離 子植入製程，以於記憶胞區102之矽基底1〇〇中形成源極/ 汲極區130。之後’利用氧電漿(〇xygen pksma)進行灰化 (ashing)步驟，以移除圖案化光阻層128。在進行灰化步驟 時’由於閘極結構I32 #側壁會直接暴露在灰化反應的環 i兄中’且氧也可能會和魏鎢發生反應，因此在石夕化 鎢層120的側壁會形成殘留物14〇，而影響後續製程。 請參照® ic ’利用原位蒸汽生成法（in_situ切⑽ 200913167 pt.ap897 25003twf.doc/p generation，ISSG)於閘極結構132的側壁形成一層氧化物 層126。由於矽化鎢層12〇的側壁形成有殘留物140，在進 行原位蒸汽生成法的過程中，容易會在矽化鎢層120的側 壁形成突出物142或是其他缺陷(未繪示），因而導致閘極 結構132變形。如此一來，突出物142或缺陷的形成不僅 會造成片電阻增加，甚至會使相鄰的閘極結構132彼此橋 接而使元件失效，降低元件可靠度。 【發明内容】200913167 pt.ap897 25003twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a semi-conductive non-volatile memory.衣王, and especially related to a [prior art] non-volatile memory components because of its advantages 'so it has become a memory component for personal computers and ==. to. Also widely used are typical non-volatile memory components, stacked idler structures, including those made of doped metal lithium.) (e 3 ^ between the gate and the substrate, and floating The circuit is connected to the word tree, and the control gate is connected to the word tree. In addition, a dielectric layer is included between the floating electrode and the control gate, and a tunnel dielectric layer is further included between the substrates. With the rapid development of semiconductor process technology, in order to improve the speed and performance of components, the entire circuit _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The sheet resistance of the control gate of the polycrystalline germanium metal (to increase the resistance of e), and reduce the operating speed of the component. In addition, when the component size is reduced, the surface flatness and grain size of the gate structure will also be 200913167 Pt.ap897 25003twf.doc/p affects the sheet resistance. The metal telluride currently used as the control gate material is usually tungsten germanium (WSix), which is easy to produce w_〇_Si complex in high temperature environment. The gate structure is deformed, as shown in FIG. 1A to FIG. 1C, which is a schematic cross-sectional view showing a part of a manufacturing process of a non-volatile memory. Referring to FIG. 1A, a germanium substrate 100 is provided, and the germanium substrate 100 has a memory cell region. 102 and the peripheral circuit area 1〇4. The gate structure 132 and the cap layer 122 have been formed on the memory group C C1〇0 of the memory cell region ,2, and the substrate is disposed between the peripheral circuit regions 1〇4 A gate structure 134 has been formed on the substrate 1. The gate structure 132 is composed of a tungsten germanium layer 12, a doped polysilicon layer 118, an intergate dielectric layer 116, a doped polysilicon layer 114, and a tunnel dielectric layer 112. The composition U0 and the doped polycrystalline layer 118 together serve as the control idle of the memory, and the doped polysilicon layer 114 serves as the floating gate of the memory. The gate structure 134 is composed of the conductor layer 124 and the gate The electrode layer 124 is formed as a gate of the transistor. Then, a patterned photoresist layer 128 is formed on the substrate 1〇〇 in the peripheral circuit region 1〇4 to expose the memory cell region. 1〇2. 1. Please refer to @1B to pattern the photoresist layer 128 as a mask to perform the ion implantation process. A source/drain region 130 is formed in the germanium substrate 1 of the memory cell region 102. Thereafter, an ashing step is performed using an oxygen plasma (pick xygen pksma) to remove the patterned photoresist layer 128. When the ashing step is performed, 'the sidewall of the shihuahua tungsten layer 120 is formed because the gate structure I32# sidewall is directly exposed to the ring of the ashing reaction' and the oxygen may also react with the tungsten. The residue is 14 〇, which affects the subsequent process. Please refer to ® ic ' to form an oxide layer on the sidewall of the gate structure 132 by in-situ steam generation (in_situ cut (10) 200913167 pt.ap897 25003twf.doc/p generation, ISSG). 126. Since the sidewalls of the tungsten germanium layer 12 are formed with the residue 140, in the process of performing the in-situ steam generation method, protrusions 142 or other defects (not shown) are easily formed on the sidewalls of the tungsten-deposited tungsten layer 120, thereby causing The gate structure 132 is deformed. As a result, the formation of the protrusions 142 or defects not only causes an increase in sheet resistance, but also causes adjacent gate structures 132 to bridge each other to cause component failure and reduce component reliability. [Summary of the Invention]
有鍟於此，本發明提供一種非揮發性記憶體的製造方 法了以降低閘極結構之片電阻，而提升元件效能。D 本發明另提供一種非揮發性記憶體的製造方法， 避免閘極結構變形。 勺 θ本發明提出一種非揮發性記憶體的製造方法。首务， 第一導體層、閘間介電層與第 ύ 體層與介電層，以形成閘極 曰 構之側壁形成第—彳g厗。 有於閘極結 阻層暴露出預形成摻雜區之基底。J且 詹。 任弟料層形成之後，移除圖案化光阪 在本發明之—實施例中， 方法例如是騎灰化步驟。仅移除®案化光阻層的 在本發明之一實施例中， 上述之弟一保濩層的材料例 200913167 pt.ap897 25003twf.doc/p 如是氧化石夕。 上述之弟一保護層的形成方 在本發明之一實施例中 法例如是熱氧化法。 第一保護層的形成方 在本發明之一實施例中，上述之 法例如是原位蒸汽生成法。 圖案化之 在本發明之-實施例中，在圖案化記憶胞 體層之後及圖案化_介電層之前，更包括在經弟 第二導體層的側壁形成第二保護層。 '、工丨 如是之—細中’ 護層的材料例 在本發明之一實施例中 法例如是熱氧化法。 在本發明之一實施例中 法例如是原位蒸汽生成法。 上述之第—保護層的形成方 上述之第—保護層的形成方 成頂發明之一實施例中，更包括於閘極結構之上方形 、在本發明之一實施例中，上述之頂蓋層的材料例如是 以四乙基矽酸鹽(tetraeth〇xysilane, TE〇S)作為氣體源所形 成之氧化砍。 7 在本發明之一實施例中，上述之第二導體層至少包括 金屬矽化物層。 在本發明之一實施例中，上述之金屬矽化物層的材料 例如是矽化鎢。 在本發明之一實施例中，上述之第二導體層包括摻雜 200913167 pt.ap897 25003twf.doc/p 多晶珍層。 在本發明之一實施例中，上述之第一導體層的材料例 如是摻雜多晶矽。 本發明另提出一種非揮發性記憶體的製造方法。首 先々提供其上已形成有介電層、第一導體層、閘間介電層 與第=導體層之基底。之後，圖案化第二導體層。接著， 導體層之側壁形成第一保護層。繼之，圖案化閘間 w免層、第一導體層與介電層，以形成閘極結構。之後， 2極結構之㈣形成第二賴層。錢，形賴案化光 :’且此_化光阻層暴露出預形祕雜區之基底。隨 底巾形成摻縣。在帛二髓層形成之後，移除 圃案化光阻層。In view of the above, the present invention provides a method of fabricating a non-volatile memory to reduce the sheet resistance of the gate structure and improve component performance. D The present invention further provides a method of manufacturing a non-volatile memory to avoid deformation of the gate structure. Spoon θ The present invention proposes a method of manufacturing a non-volatile memory. The first service, the first conductor layer, the inter-gate dielectric layer and the first germanium layer and the dielectric layer form a sidewall of the gate structure to form a first 彳g厗. A substrate is formed in the gate resist layer to expose the pre-formed doped regions. J and Zhan. After the formation of the faculty layer, the patterned gamma is removed. In an embodiment of the invention, the method is, for example, an ashing step. In the embodiment of the present invention, only the material of the above-mentioned protective layer is removed. In the case of the present invention, the material of the above-mentioned protective layer is 200931167 pt.ap897 25003twf.doc/p. The formation of a protective layer as described above is an example of a thermal oxidation method in an embodiment of the invention. Formation of First Protective Layer In one embodiment of the present invention, the above method is, for example, an in-situ steam generation method. Patterning In an embodiment of the invention, after patterning the memory cell layer and before patterning the dielectric layer, further comprising forming a second protective layer on the sidewall of the second conductor layer. ', 丨 丨 — 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细 细In one embodiment of the invention, the method is, for example, an in situ steam generation process. In the embodiment of the invention described above, the forming of the first protective layer is further included in the embodiment of the first embodiment of the invention, further comprising a square above the gate structure. In an embodiment of the invention, the top cover is The material of the layer is, for example, an oxidized cut formed by using tetraeth〇xysilane (TE〇S) as a gas source. In one embodiment of the invention, the second conductor layer comprises at least a metal halide layer. In an embodiment of the invention, the material of the metal telluride layer is, for example, tungsten telluride. In an embodiment of the invention, the second conductor layer comprises a doping layer of 200913167 pt.ap897 25003 twf.doc/p. In an embodiment of the invention, the material of the first conductor layer is, for example, doped polysilicon. The invention further provides a method of manufacturing a non-volatile memory. First, a substrate on which a dielectric layer, a first conductor layer, a gate dielectric layer, and a = conductor layer are formed is provided. Thereafter, the second conductor layer is patterned. Next, the sidewalls of the conductor layer form a first protective layer. Next, the gate slab w is free of layers, the first conductor layer and the dielectric layer to form a gate structure. Thereafter, (4) of the 2-pole structure forms a second layer. Money, the shape of the light: 'and this _ photoresist layer exposes the base of the pre-shaped miscellaneous area. The county is formed with the undertaste. After the formation of the second marrow layer, the patterned photoresist layer is removed.
、在本發明之一實施例中 方法例如是進行灰化步驟。 如是ίίΓ之—實施例中，上述之第二保護層的材料例 法例實施例中’上述之第二保護層的形成方 在本發明之—實施例中 如是氧化矽。 在本發明之—實施例中 法例如是熱氧化法。 在本發明之—實施例中 法例如是輕私生成法。 上述之移除圖案化光阻層的 上述之第一保護層的材料例 上述之第一保護層的形成方 上述之第一保護層的形成方 200913167 pt.ap897 25003twf.doc/p 法例ΐΐί二汽!’上述之第二保護層的形成方 在本發明之一實施例中， 成頂蓋層 更包括於閘極結構 之上方形 在本發明之一實施例中，、+、 以四乙基鶴作為氣體源所形的材料例如是 金屬itff—實補巾，上述之第二導體層至少包括 例如之—實施财，上叙金屬魏物層的材料 在本發明之一實施例中，上 多晶矽層。 弟一導體層包括摻 雜 如是施例中，上述之第-導體層的材料例 化步料進行灰 心❿匕〜⑺蚀結構的 因此能夠避免金屬⑦化物層產生突出物的情況二二 極結構變形。 而防止閘 提升元件效能 =溫反應使晶粒的尺寸變大:: 舉較 10 200913167 pt.ap897 2^UU3twf.doc/p 【實施方式】 圖2A至圖是依照本發明之—實施例之 記憶體的製造流程剖面示意圖。 戸輝^性 請參照® 2A，提供基底200，其例如是石夕基底 200包括記憶胞區202以及周邊電路區2〇4。接著，二於 胞區搬之基底獅上形成-層介電層皿，^ 區204之基底200上形成一層介電層。介^遠$ 與介電層㈣的材料例如是氧化秒，且其形成方法^如= 化學氣相沉積法。此外，依照之後卿成之元件特性，= 電層212a的厚度與介電層212b的厚度例如是相 二 同。之後’於基底200上形成—層導體層214。導體層J ^料例如是_多於，且其形成方關如化學氣曰相沉 Η人Ϊί述’於基底上形成—層閘間介電層216。閘 ==例如是氧化魏切物層或其他合： 之"電材制。上述這些介電㈣(如氧切、氮 形成方法例如枚學氣相_法或純化法。隨之= 綱之關介電層216。移除周邊電^ 之間間"電層216的方法例如是先於基底2〇〇上形 Ϊ 2^光會示卜此圖案化光阻層暴露出周邊電路 ΐί Γ圖案化光阻層為罩幕，進行乾式钱刻 = Ϊ程移除閘間介電層216,而暴露出周邊 电路£ 204之導體層214。 請繼續參照圖2Α，於基底上依序形成導體層218 200913167 px.apfiy/ ZDuuitwf.doc/pIn one embodiment of the invention, the method is, for example, an ashing step. In the embodiment, in the material example of the second protective layer described above, the formation of the second protective layer is in the embodiment of the invention, such as yttrium oxide. In the embodiment of the invention, the method is, for example, a thermal oxidation method. In the embodiment of the present invention, the method is, for example, a light private generation method. The above-mentioned material for removing the first protective layer of the patterned photoresist layer is the formation of the first protective layer described above. The formation of the first protective layer is as described above. 200913167 pt.ap897 25003twf.doc/p Law ΐΐί 二汽In the embodiment of the present invention, the cap layer is further included in the square structure above the gate structure. In one embodiment of the present invention, +, tetraethyl crane The material shaped as the gas source is, for example, a metal itff-solid towel, and the second conductor layer includes at least the material of the metal layer, for example, in the embodiment of the present invention, the upper polycrystalline layer . The conductor layer includes doping, as in the embodiment, the material of the first conductor layer is instantiated to perform a gray-hearted (~(7) etch structure, thereby avoiding the occurrence of protrusions in the metal stellite layer. . Preventing the function of the gate lifting element = the temperature response makes the size of the crystal grain larger:: 10 1013 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 Schematic diagram of the manufacturing process flow. Referring to ® 2A, a substrate 200 is provided, which is, for example, a stone substrate 200 including a memory cell region 202 and a peripheral circuit region 2〇4. Next, a dielectric layer is formed on the base lion of the cell region, and a dielectric layer is formed on the substrate 200 of the region 204. The material of the dielectric layer (4) is, for example, oxidized seconds, and its formation method is as follows: chemical vapor deposition. Further, the thickness of the electric layer 212a and the thickness of the dielectric layer 212b are, for example, the same as the element characteristics of the subsequent layer. A layer conductor layer 214 is then formed on the substrate 200. The conductor layer J is, for example, more than _, and is formed such that a chemical gas phase is deposited on the substrate to form a interlayer dielectric layer 216. Gate == For example, an oxidized Wei cut layer or other combination: "Electrical material." The above dielectrics (4) (such as oxygen cutting, nitrogen forming methods such as gas phase method or purification method. Follow-up = the dielectric layer 216. The method of removing the electrical layer 216 between the surrounding circuits) For example, it is preceded by the shape of the substrate 2 Ϊ 2 ^ light will show that the patterned photoresist layer exposes the peripheral circuit ΐ Γ Γ patterned photoresist layer as a mask, for dry money engraving = 移除 移除 闸 闸 移除The electrical layer 216 exposes the conductor layer 214 of the peripheral circuit £204. Please continue to refer to FIG. 2Α to sequentially form the conductor layer 218 on the substrate. 200913167 px.apfiy/ ZDuuitwf.doc/p
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/ .i X.J 與導體層220。導體層218的材料例如是摻雜多晶石夕，且 其形成方法例如是化學氣相沉積法。導體層22〇的材料例 如是耐火金屬之金屬矽化物，其可以是矽化鎢。導體層22〇 的形成方法例如是化學氣相沉積法。接著，於基底2〇〇上 依序形成-層介電材料層222及圖案化光阻層η4。介電 材料層222的材料例如是氧化石夕，且其形成方法例如是以 四乙基石夕酸鹽作為氣體源、進行化學氣相沉積法。圖案化光 阻層224的形成方法例如是於整個基底2〇〇上形成一層光 阻材料層（树示），然後騎曝光、顯影步驟而形成之日。 响參照圖2B，以圖案化光阻層224為罩幕，移除 露出的介電材料層222’以於記憶胞區2〇2形成頂。 222a，並同時於周邊電路區204形成頂蓋層222b。移 電材料層222的方法例如是乾式㈣法。繼之，移除 化光阻層224。移除圖案化光阻層224的方法例如是乾^ 去光阻法或濕式去光阻法。 202 $接^#^頂盖層^為罩幕，圖案化位於記憶胞區 ¥體層220、導體層218、閘間介電層216、導 2H士與介電層212a，以於記憶胞區逝形成閘極結構攻曰。 二，層222b為罩幕’圖案化位^周邊電路區204 之¥肢層22〇、導體層2!8、導體層別與介 以於周邊電路區204形成閘極結構234。 12b， 層^上區2〇2之開極結構232例如是由導體 二：V體層服、間間介電層⑽、導體層騎盥 "電層212a，所組成的堆疊結構。導體層純例料 12 200913167 pt.ap897 25003twf.doc/p 後續預形成之s己憶體的浮置閘極，導體層2iga與導體層 220a例如是共同作為後續預形成之記憶體的控制閘極，介 電層212 a ’例如是作為後續預形成之記憶體的穿隧介電 層。而周邊電路區204之閘極結構234例如是由導體層 220b、導體層218b、導體層214b與介電層212b，所袓成的 堆疊結構。導體層214b、導體層21肋與導體層22此例如 是共同作為後續預形成之電晶體的閘極，而介電層2i2b， Γχ 例如是作為後續預形成之電晶體的閘介電層。 特別說明的是，上述圖案化導體層220、導體層218、 閘間介電層216、導體層214、介電層212a與介電層212b 可以是在同-個圖案化製程中完成，或是可以經由^個不 同的圖案化製程來完成。此外，在本實施例中，是以在同 -道圖案化製程巾形賴極結構232與閘極結構2料為例 以作說明，但本發明並不限於此。當然，間極結構说鱼 閘極結構234也可以在不同道的圖#化製程中形成，於此 技術領域具有通常知識者可視其需求調整。 “ 請參照圖2C，於閘極結構232的侧壁形成一層保護 層226。保護層226的材料例如是氧化石夕，且盆形成方法 例如是熱氧化法或是原位蒸汽生成法。此外，在形成保護 層=之前’還可以選擇性地進行濕式清洗製程，以去除 先則衣程所殘留之微粒或雜質’避免後續製程受影響。在 本^^中’濕式清洗製程所使用的清洗液例如是硫酸和 過氧化氫所組成的混合溶液細而也acid吆办吨如 卿她mixture，SPM)以及氨水和過氧化氮所組成的混合 13 200913167 pt.ap897 25003twf.doc/p 溶液(ammonia hydrogen per〇xide mixture，ApM)。 接著，形成圖案化光阻層228。圖案化光阻層228例 如是暴露出後續預形成摻雜區之基底2〇(^在此實施例 中’圖案化光阻層228覆蓋周邊電路區2〇4，而暴露出記 憶胞區202。，圖案化光阻層228的形成方法例如是於整個 基底2〇0上形成-層光阻材料層(未緣示），然後進行曝光、 顯影步驟以形成之。 凊參照® 2D，於記憶胞區2〇2之基底2〇〇中形成換 雜區23G。摻雜區23G爿如是作為後續獅成之記憶體的 源極/沒極區。摻雜區23G的形成方法例如錢子植入法， 且植入的離子例如是_(As)離子。之後，移除圖案化光阻 層228。移除圖案化光阻層挪的方法例如是利用氧電蒙 進行灰化步驟。 特別說明的是，在進行灰化步驟之前，由於在間極結 1 232的彳貞!壁已形成有保護層226，因此有助於防止導體 =20a與氧電祕生反應，而能夠避終體層施的側 土產生突出物，並防止閘極結構232變形。 圖3C是依照本剌另—實施例之非揮發性記 二α Γ# <程剖面示意圖。圖3A是接續上述實施例之 日门^"。此外’於圖3A至圖3C中，與圖2A至圖 相f的構件則使用相_標號並省略其說明。 露出^Ϊί、3Α，以圖案化光阻層224為罩幕，移除暴 222a料層222，以於記憶胞區202形成頂蓋層 並冋¥於周邊電路區2〇4形成頂蓋層22沘。移除介 14 200913167 pt.ap897 25003twf.doc/p 電材料層222的方法例如是乾式 化光阻層224。移除圖宰化㈣移除圖案 去光阻法或濕式去光^級層224的方法例如是乾式 導體ΐΐο 咖與了頁蓋層_為罩幕，圖案化 並於周邊電路區-形成導二 在其他實施例中，導體層2施與 :s a的形成以及導體層220b與導體層218b也可以 ，不同道的賴化製財完成，本發明於此科任何之限 定。 睛繼、，參照目3A’於導體層施與導體層⑽之側 形成-層保護層302。保護層3〇2的材料例如是氧化石夕， $形，方法例如是熱氧化法或是原位蒸汽生成法 。值得/ .i X.J and conductor layer 220. The material of the conductor layer 218 is, for example, doped polycrystalline stone, and its formation method is, for example, chemical vapor deposition. The material of the conductor layer 22 is, for example, a metal halide of a refractory metal, which may be tungsten telluride. The method of forming the conductor layer 22A is, for example, a chemical vapor deposition method. Next, a layer of dielectric material layer 222 and a patterned photoresist layer η4 are sequentially formed on the substrate 2A. The material of the dielectric material layer 222 is, for example, oxidized stone, and is formed by a chemical vapor deposition method using, for example, tetraethylphosphonate as a gas source. The patterning of the patterned photoresist layer 224 is, for example, a layer of a photoresist material (tree) formed over the entire substrate 2, and then formed by the exposure and development steps. Referring to Figure 2B, with the patterned photoresist layer 224 as a mask, the exposed dielectric material layer 222' is removed to form a top in the memory cell region 2〇2. 222a, and simultaneously forming a cap layer 222b in the peripheral circuit region 204. The method of transferring the material layer 222 is, for example, a dry (four) method. Following, the photoresist layer 224 is removed. The method of removing the patterned photoresist layer 224 is, for example, a dry photoresist method or a wet photoresist method. 202 $接^#^Top cover layer ^ is a mask, and is patterned in the memory cell area body layer 220, the conductor layer 218, the inter-gate dielectric layer 216, the conduction 2H and the dielectric layer 212a, so as to memory cell death Form a gate structure attack. Second, the layer 222b is a gate structure 234 of the masking layer ^ peripheral layer 204, the conductor layer 2! 8, the conductor layer and the peripheral circuit region 204. 12b, the open structure 232 of the upper layer 2〇2 is, for example, a stacked structure composed of a conductor 2: a V bulk layer, an interlayer dielectric layer (10), and a conductor layer rider " an electric layer 212a. Conductor layer pure material 12 200913167 pt.ap897 25003twf.doc/p The floating gate of the subsequently preformed simon, the conductor layer 2iga and the conductor layer 220a are, for example, together as the control gate of the subsequently preformed memory The dielectric layer 212a' is, for example, a tunneling dielectric layer that is a subsequently preformed memory. The gate structure 234 of the peripheral circuit region 204 is, for example, a stacked structure formed by the conductor layer 220b, the conductor layer 218b, the conductor layer 214b, and the dielectric layer 212b. The conductor layer 214b, the conductor layer 21 ribs and the conductor layer 22 are, for example, collectively used as the gate of a subsequently preformed transistor, and the dielectric layer 2i2b, Γχ is, for example, a gate dielectric layer as a subsequently preformed transistor. In particular, the patterned conductor layer 220, the conductor layer 218, the inter-gate dielectric layer 216, the conductor layer 214, the dielectric layer 212a, and the dielectric layer 212b may be completed in the same patterning process, or This can be done via ^ different patterning processes. Further, in the present embodiment, the description is made by taking the same patterning process of the towel-shaped structure 232 and the gate structure 2 as an example, but the present invention is not limited thereto. Of course, the interpole structure said that the fish gate structure 234 can also be formed in different processes, which can be adjusted by the general knowledge in the technical field. Referring to FIG. 2C, a protective layer 226 is formed on the sidewall of the gate structure 232. The material of the protective layer 226 is, for example, oxidized oxide, and the pot forming method is, for example, thermal oxidation or in-situ steam generation. In the formation of the protective layer = before 'we can also selectively carry out the wet cleaning process to remove the particles or impurities remaining in the first coat of clothing 'to avoid subsequent processes are affected. In this ^ ^ 'wet cleaning process used The cleaning solution is, for example, a mixed solution of sulfuric acid and hydrogen peroxide, and is also a mixture of ammonia and her nitrogen and nitrogen peroxide. 13 200913167 pt.ap897 25003twf.doc/p solution ( Subsequently, a patterned photoresist layer 228 is formed. The patterned photoresist layer 228 is, for example, a substrate 2 that exposes a subsequent pre-formed doped region (^ in this embodiment 'patterned The photoresist layer 228 covers the peripheral circuit region 2〇4 to expose the memory cell region 202. The method for forming the patterned photoresist layer 228 is, for example, forming a layer of photoresist layer on the entire substrate 2〇0. ), then expose And developing step to form. 凊Reference ® 2D, forming a replacement region 23G in the substrate 2〇〇 of the memory cell 2〇2. The doped region 23G is used as the source/no-polar of the memory of the subsequent lion a method of forming the doped region 23G, such as a money implantation method, and the implanted ions are, for example, _(As) ions. Thereafter, the patterned photoresist layer 228 is removed. The method of removing the patterned photoresist layer is removed. For example, the ashing step is performed by using an oxy-electricity. Specifically, before the ashing step, since the protective layer 226 is formed on the wall of the inter-pole junction 1232, it helps to prevent the conductor = 20a. Reacts with the oxygen electricity secret, and can avoid the lateral soil applied to the end layer to produce protrusions, and prevent the gate structure 232 from being deformed. Fig. 3C is a non-volatile memory of the non-volatile memory according to another embodiment of the present invention. Fig. 3A is a splicing of the door of the above embodiment. In addition, in Figs. 3A to 3C, the components of Fig. 2A to Fig. f are denoted by the same reference numerals and the description thereof is omitted. 3, with the patterned photoresist layer 224 as a mask, the 222a layer 222 is removed to the memory cell region 202. Forming a cap layer and forming a cap layer 22沘 in the peripheral circuit region 2〇4. The method of removing the dielectric layer 222.13167 pt.ap897 25003twf.doc/p is performed, for example, by dry-drying the photoresist layer 224. In addition to the tarnishing (four) method of removing the pattern to the photoresist or the wet grading layer 224, for example, the dry conductor ΐΐ 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖In other embodiments, the formation of the conductor layer 2: sa and the conductor layer 220b and the conductor layer 218b may be performed in different ways, and the present invention is not limited to this subject. Further, referring to the item 3A', a layer of the protective layer 302 is formed on the side of the conductor layer to which the conductor layer (10) is applied. The material of the protective layer 3〇2 is, for example, an oxidized oxide, and the method is, for example, a thermal oxidation method or an in-situ steam generation method. worth it
、生的疋，在形成保護層3〇2之前，還可選擇性地進行濕 式清洗製程，以去除先前製賴殘留之絲或雜質，避免 ^續製程《彡響。在本實闕巾，狀清洗製輯使用的 清，液例如是硫酸和過氧化氫所組成的混合溶液(spM)以 及氨水和過氧化氫所組成的混合溶液(APM)。 立請參照圖3B，以頂蓋層222a為罩幕，圖案化位於記 ^胞區202之閘間介電層216、導體層214與介電層212a， 以於記憶胞區202形成閘極結構232。同時，以頂蓋層222b 為罩幕’圖案化位於周邊電路區204之導體層214與介電 層2l2b ’以於周邊電路區204形成閘極結構234。 接著’於閘極結構232的側壁形成另一層保護層304。 15 200913167 pt.ap897 25003twf.doc/p 的材料例如是氧切，且其形成方法例如是叛 氧化法或疋原位蒸汽生成法。如圖3δ所示 ^ 與導體層施之砸已形成有保護層地，耻部; f::!形Γ保護層302之外側。此外，在形成保護層 3〇4之則，亦可以選擇性地以硫酸和過氧化氫所組成的^ 合浴液（sm)以及氨水和過氧化氣所 作為清錄來蹄赠絲程，財_留的= Γ、 u 請繼續參照圖3Β，形成圖案化光阻層挪。圖案 阻^ 228例如是暴露出後續預形成摻雜區之基纟綱。在 例中，圖案化光阻層228覆蓋周邊電路區2〇4 = · 2〇2。圖案化光阻層228的形成方法例如 =j基底上H層光輯料層（树示），然後 進行曝光、顯影步驟以形成之。 曼 請參照® 3C，於記憶胞區2〇2之基底中形成換 =區⑽。摻雜區23G的形成方法例如是離子植入法，^ =入如是夠離子。接著，移除圖案化光阻層 ΞίΓ 層228的方法例如是利用氧電衆進行 紗進歧化步縣除_域阻層228之前，閉 極結構232的側壁已形成有保護層3〇2盥 」 ，免導體層2施與氧_發纽應，因此防止導二 層220a的㈣形成突出物，且避免閉極結構加變形體 此外’猎由進行多次形成保護層的反應(在此實施例中 16 200913167 pt.apsy/ 25UU3twf.doc/p 為兩次），在反應過程中的高溫會使晶粒的尺寸變大，因而 可以進一步降低片電阻，改善元件效能。 值得一提的是，在上述實施例中，是以在圖案化光阻 層228形成之前與保護層3〇2形成之後，於閘極結構232 的側壁形成保護層304為例來進行說明，但本發明並不限 於此。在其他實施例中，只要在進行灰化步驟移除圖案化 光阻層228之前’由石夕化鶴所構成之導體層2施的侧壁形 〇 成有保護層，即可有效避免閘極結構232變形，熟知本領 域之技術人員當可知其應用，故於此不再贅述。、7 综上所述，本發明之方法因在進行灰化步驟之前 於閘極結構之侧壁形成保護層，因此可以避免石夕化鎮 電漿發生反應，防止突出物的產生或閘極結 低片電阻。 胃 再者，本發明之方法在形成保護層的過程中， 應能夠使晶粒的尺寸變大，而更進一步降 雖然本發明已以較佳實施例揭露如上，然其並 限疋本發明，任何所屬技術領域巾具有通常知 脫離本發明之精神和範#可作㈣之更_ ^不 =本發明之賴_當視_之申料利範_界定者 圖式簡單說明】 圖1A至圖1C是習知之—種非揮發性記憶體的部分製 200913167 pt.ap897 25003twf.doc/p 造流程剖面示意圖。 圖2A至圖20是依照本發明之一實施例之非揮發性 記憶體的製造流程剖面示意圖。 圖3A至圖3C是依照本發明另一實施例之非揮發性記 憶體的製作流程剖面示意圖。 【主要元件符號說明】 100 ·珍基底 102、202 :記憶胞區 104、204 :周邊電路區 110 :閘極氧化層 112 :穿隧介電層 114 :摻雜多晶矽層 116、216、216a :閘間介電層 118 :摻雜多晶矽層 120 :矽化鎢層 122、222a、222b :頂蓋層 124、214、214a、214b、218、218a、218b、220、220a、 220b :導體層 126 :氧化物層 128、224、228 :圖案化光阻層 130 ·源極/没極區 132、134、232、234 :閘極結構 140 :殘留物 18 200913167 pt.ap897 25003twf.doc/p 142 :突出物 200 :基底 212a、212a，、212b、212b，：介電層 222 :介電材料層 226、302、304 :保護層 230 :摻雜區The raw enamel can also be selectively wet-cleaned before the formation of the protective layer 3〇2 to remove the residual silk or impurities previously removed, and to avoid the process of “sounding”. In the actual wipes, the cleaning liquid used is, for example, a mixed solution (spM) composed of sulfuric acid and hydrogen peroxide, and a mixed solution (APM) composed of ammonia water and hydrogen peroxide. Referring to FIG. 3B, the capping layer 222a is used as a mask to pattern the inter-gate dielectric layer 216, the conductor layer 214 and the dielectric layer 212a of the cell region 202 to form a gate structure in the memory cell region 202. 232. At the same time, the conductor layer 214 and the dielectric layer 2l2b' located in the peripheral circuit region 204 are patterned by the cap layer 222b as a mask to form the gate structure 234 in the peripheral circuit region 204. Next, another protective layer 304 is formed on the sidewall of the gate structure 232. 15 200913167 pt.ap897 The material of 25003twf.doc/p is, for example, oxygen cut, and its formation method is, for example, a rebel method or an in situ steam generation method. As shown in Fig. 3δ, the conductive layer is formed with a protective layer, the mascara; and the f::! shape is outside the protective layer 302. In addition, in the case of forming the protective layer 3〇4, it is also possible to selectively use the bath liquid (sm) composed of sulfuric acid and hydrogen peroxide, and the ammonia water and the peroxidized gas as the clearing records. _Remaining = Γ, u Please continue to refer to Figure 3Β to form a patterned photoresist layer. The pattern resistor 228 is, for example, a substrate that exposes a subsequent pre-formed doped region. In the example, the patterned photoresist layer 228 covers the peripheral circuit region 2〇4 = · 2〇2. The method of forming the patterned photoresist layer 228 is, for example, a H-layer optical layer (tree) on the substrate, and then subjected to an exposure and development step to form it. Please refer to ® 3C to form a change zone (10) in the base of the memory cell 2〇2. The method of forming the doped region 23G is, for example, an ion implantation method, and if it is an ion. Then, the method of removing the patterned photoresist layer 228 is, for example, that the sidewall of the closed-pole structure 232 has been formed with a protective layer 3〇2盥 before the yarn is disproportionated by the oxygen generator. The conductor-free layer 2 is applied with oxygen, so that the (4) of the second layer 220a is prevented from forming protrusions, and the closed-pole structure is added to the deformation body. In addition, the reaction of forming the protective layer is performed multiple times (in this embodiment). Medium 16 200913167 pt.apsy/ 25UU3twf.doc/p is twice), the high temperature during the reaction will increase the size of the crystal grains, which can further reduce the sheet resistance and improve the device performance. It should be noted that in the above embodiment, the protective layer 304 is formed on the sidewall of the gate structure 232 after the formation of the patterned photoresist layer 228 and the protective layer 3〇2, but the protective layer 304 is formed as an example. The invention is not limited to this. In other embodiments, as long as the sidewall layer of the conductor layer 2 composed of Shi Xihua crane is formed into a protective layer before the ashing step is performed to remove the patterned photoresist layer 228, the gate can be effectively avoided. The structure 232 is modified, and the application is well known to those skilled in the art, and thus will not be described herein. 7 In summary, the method of the present invention forms a protective layer on the sidewall of the gate structure before the ashing step, thereby preventing the reaction of the plasma in the Xixia Town, preventing the occurrence of protrusions or gate junctions. Low sheet resistance. Further, in the process of forming a protective layer, the method of the present invention should be able to increase the size of the crystal grains, and further down. Although the present invention has been disclosed in the preferred embodiments as above, it is not limited to the present invention. Any of the technical fields of the present invention are generally known to be deviated from the spirit of the present invention and can be used as the fourth. _ ^================================================================ A well-known part of the non-volatile memory system 200913167 pt.ap897 25003twf.doc/p schematic diagram of the process flow. 2A through 20 are schematic cross-sectional views showing a manufacturing process of a non-volatile memory according to an embodiment of the present invention. 3A to 3C are schematic cross-sectional views showing a manufacturing process of a non-volatile memory material according to another embodiment of the present invention. [Main component symbol description] 100 · Jane substrate 102, 202: Memory cell region 104, 204: Peripheral circuit region 110: Gate oxide layer 112: Tunneling dielectric layer 114: Doped polysilicon layer 116, 216, 216a: Gate Inter-dielectric layer 118: doped polysilicon layer 120: tungsten-deposited tungsten layer 122, 222a, 222b: cap layer 124, 214, 214a, 214b, 218, 218a, 218b, 220, 220a, 220b: conductor layer 126: oxide Layers 128, 224, 228: patterned photoresist layer 130 • source/no-polar regions 132, 134, 232, 234: gate structure 140: residue 18 200913167 pt.ap897 25003twf.doc/p 142: protrusion 200 : Substrate 212a, 212a, 212b, 212b, dielectric layer 222: dielectric material layer 226, 302, 304: protective layer 230: doped region