CN102136465A - Open-circuit embedding-removing test structure for trimmer-capacitance MOS (metal oxide semiconductor) varactor and variable capacitance diode - Google Patents
Open-circuit embedding-removing test structure for trimmer-capacitance MOS (metal oxide semiconductor) varactor and variable capacitance diode Download PDFInfo
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- CN102136465A CN102136465A CN 201010102404 CN201010102404A CN102136465A CN 102136465 A CN102136465 A CN 102136465A CN 201010102404 CN201010102404 CN 201010102404 CN 201010102404 A CN201010102404 A CN 201010102404A CN 102136465 A CN102136465 A CN 102136465A
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Abstract
The invention discloses an open-circuit embedding-removing test structure for a trimmer-capacitance MOS (metal oxide semiconductor) varactor and a variable capacitance diode, which comprises a plurality of metal layers and an active area; the plurality of metal layers comprise a top metal layer, a first metal layer connected with the active area, and at least one middle metal layer between the top metal layer and the first metal layer; the first metal layer comprises a loop; the top metal layer is divided into four unconnected port top metal layer areas; the scopes of the areas of the middle metal layer below each area are all in the scopes of the corresponding port top metal layer areas; an earthing port top metal layer area is connected with the middle metal layer area below thereof and the loop of the first metal layer one by one; and at least one layer of middle metal area below a signal port top metal layer area is removed to cut off the connection between the signal port top metal layer area and the first metal layer. The open-circuit embedding-removing test structure can effectively eliminate parasitic capacitances, and improve the consistency between the parameters of the test structure and the actual circuit parameters.
Description
Technical field
The present invention relates to technical field of semiconductors, the open circuit that relates in particular to a kind of little capacity MOS varactor and variable capacitance diode removes the embedding test structure.
Background technology
Metal-oxide semiconductor (MOS) (MetalOxide Semicoductor, hereinafter to be referred as: MOS) varactor and variable capacitance diode all are the element of electric capacity with change in voltage, it is radio frequency and mixed signal (mix-signal) circuit, especially (Voltage Controlled Oscillator is hereinafter to be referred as the VCO) critical elements in the circuit for voltage-controlled oscillator.And along with development of integrated circuits, the driving operating frequency of some circuit has surpassed 3GHz, and for example, in high speed circuit, the VCO circuit of clocking need adopt position of minimum capacitance to be less than or equal to 100fF (10
-10F) little capacity MOS varactor or variable capacitance diode.
For each parameter of acquisition circuit in the circuit design process, and utilize these parameters to carry out circuit design, need to adopt test structure that the circuit of design is tested.In test process, because the electric capacity of little capacity MOS varactor and variable capacitance diode self is very little, therefore, the electric capacity of little capacity MOS varactor and variable capacitance diode is easy to be subjected to the influence of himself the parasitic capacitance and the parasitic capacitance of test structure, and then can make the very big deviation of existence between side circuit and the design circuit.Therefore in the circuit design process, need to introduce and go the embedding test structure to remove parasitic capacitance in little capacity MOS varactor and variable capacitance diode self and the test structure.But existing parasitic capacitance of going the embedding test structure only to provide to remove MOS varactor and variable capacitance diode self remove the embedding test structure.
Because the used test structure of variable capacitance diode and MOS varactor is similar, so be that example describes with the MOS varactor.Prior art utilizes gate oxide to constitute the grid capacitance of MOS varactor (hereinafter to be referred as C usually
Gg), the thickness of gate oxide changes with the variation of grid voltage, thereby reaches by voltage control C
GgPurpose.But so just produced the parasitic capacitance of little capacity MOS varactor self, because the existence of this parasitic capacitance can bring adverse effect to the performance of little capacity MOS varactor.
The parasitic capacitance of little capacity MOS varactor self and the parasitic capacitance of test structure can reveal by the tuning ratio parameter list of MOS varactor to come to little capacity MOS varactor element Effect on Performance.
The tuning ratio Ratio of MOS varactor is
Wherein, C
Gg.maxBe C by effective voltage control
GgMaximum, C
Gg.minBe C by effective voltage control
GgMinimum value, C
pBe parasitic capacitance.If in the measurement process to parasitic capacitance to go embedding to handle not thorough, will cause parasitic capacitance C in the formula
PPart increases, thereby reduces the tuning ratio of MOS varactor.
The schematic diagram of Figure 1A tuning rate of change that to be prior art increase with the active zone area of MOS varactor.Shown in Figure 1A, wherein, ordinate is tuning ratio Ratio, and abscissa is active zone area (um
2), wherein the active zone area is relevant with the structure of MOS varactor.As can be seen, along with the increase of the active zone area of MOS varactor, the tuning ratio of MOS varactor increases to 7.95 by 5.55, has very large deviation with the tuning ratio of MOS varactor in theory.Therefore parasitic capacitance has appreciable impact to the tuning ratio of MOS varactor, that is to say that the tuning ratio of MOS varactor can reflect the influence of parasitic capacitance to the MOS varactor element.
Figure 1B is the schematic diagram that prior art four steps commonly used removes the embedding test structure.Shown in Figure 1B, this test structure 101B comprises simple open circuit 102B, simple short circuit 103B, short circuit one 104B, short circuit two 105B and five kinds of test structures of open circuit 106B.Wherein, G is a grounding ports, and S connects signal port, and in each test structure shown in Figure 1B, with regard to the MOS varactor, the signal port S that connects on right side connects source/drain electrode end, and the signal port S that connects in left side connects gate terminal, 4 equal ground connection of grounding ports G.
Fig. 1 C is the structure chart that the employed open circuit of prior art removes the embedding test structure.Shown in Fig. 1 C, the zone of figure bend representative is top metal level 101C, at this moment, the right side that is connected with the source/drain electrode end of MOS varactor meet signal port S and connecing between the signal port S of being connected with gate terminal disconnects.Adopt this test structure, port only be connected with the top metal level and the top metal level under do not have other metal levels, this can make disconnecting fully among the metal level 101C of top between the adjacent grounding ports of two couples of two signal port line direction both sides, at this moment, the top metal level introduces parasitic capacitance can for whole test structure, and this parasitic capacitance is not the parasitic capacitance of MOS varactor element self, but the parasitic capacitance of test structure, parasitic capacitance with regard to test structure, the existing embedding structure of going only can be removed that part of parasitic capacitance that metal level above test structure in test structure top is introduced, and can't remove the parasitic capacitance that the test structure top-level metallic is introduced to test structure between source/drain electrode end and the gate port, this can cause the parasitic capacitance of total can't be fully by going embedding to remove.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
For removing the embedding test structure, the open circuit that solves little capacity MOS varactor and variable capacitance diode can't remove the problem of parasitic capacitance fully, improve the consistency of open test structural parameters and side circuit parameter, the invention provides a kind of open circuit that is used for little capacity MOS varactor and variable capacitance diode and remove the embedding test structure, described open circuit goes the embedding test structure to comprise: a plurality of metal levels and active area; Described a plurality of metal level comprises the top metal level, at least one intermediate metal layer between the 1st metal level that is connected with described active area and described top metal level and described the 1st metal level, and described the 1st metal level comprises a loop; Described top metal level is divided into four mutual disjunct zones, described zone comprises: the metal level zone, two signal port tops that is connected with two signal ports respectively, and will be positioned at the metal level zone, two grounding ports tops that two adjacent grounding ports of described two signal port line direction homonymies link together respectively; Described intermediate metal layer comprises with metal level zone, described signal port top and is positioned at the intermetallic metal layer region under the metal level zone, signal port top accordingly and is positioned at intermetallic metal layer region under the metal level zone, grounding ports top accordingly with metal level zone, described grounding ports top, and described intermetallic metal layer region under the metal level zone, signal port top and the described coverage that is positioned at the intermetallic metal layer region under the metal level zone, grounding ports top of being positioned at is all in the coverage in corresponding described signal port top metal level zone and metal level zone, described grounding ports top; Described grounding ports top metal level zone and describedly be positioned at intermetallic metal layer region under the metal level zone, grounding ports top and the loop of described the 1st metal level successively is connected; At least remove the described intermetallic metal layer region that is positioned under the metal level zone, signal port top of one deck, metal level zone, the described signal port of realization disconnection top is connected with described the 1st metal level.
Further, described intermediate metal layer has 7, comprising: by and described active area between ascending the 2nd metal level to the 8 metal levels that are arranged in order of distance; Metal level zone, described grounding ports top successively is connected with the loop regional and described the 1st metal level of the 8th metal level zone to the 2 metal levels under being positioned at metal level zone, grounding ports top; At least remove any one deck that is arranged in the 2 metal level zones, the 8th metal level zone to the under the metal level zone, signal port top, metal level zone, the described signal port of realization disconnection top is connected with described the 1st metal level.
Further, describedly remove described any one deck that is arranged in the 2 metal level zones, the 8th metal level zone to the under the metal level zone, signal port top at least and comprise: remove described the 2nd metal level zone that is positioned under the metal level zone, signal port top, metal level zone in described signal port top successively is connected with the described 3 metal level zones, the 8th metal level zone to that are positioned under the metal level zone, signal port top.
Further, be connected by through hole between described a plurality of metal level and between described the 1st metal level and the described active area.
Further, the through hole of described top metal level and described the 8th metal interlevel is the bigger biserial through hole of diameter, and the through hole between described the 8th metal level to the 1 metal interlevel and described the 1st metal level and described active area is three less row through holes of diameter.
Further, there are identical structure and annexation in the described 2 metal level zones, the 8th metal level zone to that are positioned under the metal level zone, described grounding ports top.
Further, there are identical structure and annexation in the described 2 metal level zones, the 8th metal level zone to that are positioned under the metal level zone, described signal port top.
Further, the size of the size of described a plurality of metal levels and described little capacity MOS varactor or variable capacitance diode is complementary.
Further, the size of described a plurality of metal levels comprises the width and the length of described a plurality of metal levels.
Further, described variable capacitance diode comprises the PN junction variable capacitance diode.
The open circuit that can effectively solve little capacity MOS varactor and variable capacitance diode according to test structure of the present invention goes the embedding test structure can't remove the problem of parasitic capacitance fully, improves the consistency of test structure parameter and side circuit parameter.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
The schematic diagram of Figure 1A tuning rate of change that to be prior art increase with the active zone area of MOS varactor;
Figure 1B is the schematic diagram that prior art four steps commonly used removes the embedding test structure;
Fig. 1 C is the structure chart that the employed open circuit of prior art removes the embedding test structure;
Fig. 2 A is the structure chart that the open circuit of little capacity MOS varactor according to an embodiment of the invention removes the embedding test structure;
Fig. 2 B is the structure chart of the 102E of the open circuit of little capacity MOS varactor according to an embodiment of the invention Fig. 2 A of removing the embedding test structure;
Fig. 2 C is the A cross-sectional view that the open circuit of little capacity MOS varactor according to an embodiment of the invention removes Fig. 2 B of embedding test structure;
Fig. 2 D is the B cross-sectional view that the open circuit of little capacity MOS varactor according to an embodiment of the invention removes Fig. 2 B of embedding test structure;
Fig. 3 is the schematic diagram that the open circuit of little capacity MOS varactor according to an embodiment of the invention goes the tuning rate of change that the active zone area with the MOS varactor of embedding test structure increases;
Fig. 4 is that the open circuit of little capacity MOS varactor according to a preferred embodiment of the invention removes the johning knot composition between the metal level of embedding test structure.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, detailed structure will be proposed, in following description so that how explanation the present invention solves the open circuit of little capacity MOS varactor and variable capacitance diode to go the embedding test structure can't remove the problem of parasitic capacitance fully.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Can't remove the problem of parasitic capacitance fully for the open circuit that overcomes little capacity MOS varactor and variable capacitance diode removes the embedding test structure, the open circuit that the present invention proposes a kind of little capacity MOS varactor and variable capacitance diode goes the embedding test structure to overcome this problem.
Fig. 2 A is the structure chart that the open circuit of little capacity MOS varactor according to an embodiment of the invention removes the embedding test structure, Fig. 2 B is the structure chart of the 102E of the open circuit of little capacity MOS varactor according to an embodiment of the invention Fig. 2 A of removing the embedding test structure, for embodiment is illustrated better, Fig. 2 C is the A cross-sectional view that the open circuit of little capacity MOS varactor according to an embodiment of the invention removes Fig. 2 B of embedding test structure.Shown in Fig. 2 A, Fig. 2 B and Fig. 2 C, the structure of present embodiment can comprise: a plurality of metal levels and active area 209B.
Specifically, the structure shown in Fig. 2 B and the 2C also comprises, SN ion implanted region 211B, N well region 213B, SP ion implanted region 212B.Because SN ion implanted region 211B, N well region 213B, SP ion implanted region 212B structurally with prior art go the embedding test structure identical, therefore, no longer be described in greater detail.
A plurality of metal levels comprise top metal level 101C, at least one intermediate metal layer between the 1st metal level 201B that is connected with active area 209B and top metal level 101C and the 1st metal level 201B, the 1st metal level 201B comprises a loop, makes between each metal level on the loop that is connected to the 1st metal level 201B to be connected to each other.
Though only provided the schematic diagram of 7 intermediate metal layers among Fig. 2 A, 2B and Fig. 2 C, those skilled in the art should understand, can expand the technical scheme of the intermediate metal layer of the number beyond drawing 7 fully with reference to the structure shown in Fig. 2 A, 2B and Fig. 2 C.
Intermediate metal layer in one embodiment is specially: between top metal level 101C and the 1st metal level 201B 7 intermediate metal layers are arranged, these 7 intermediate metal layers by and active area 209B between ascending the 2nd metal level 202B to the 8 metal level 208B that are followed successively by of distance.
Intermediate metal layer comprise with signal port top metal level zone 101CS1 and 101CS2 be positioned at accordingly signal port top metal level zone 101CS1 and 101CS2 down the intermetallic metal layer region and be positioned at intermetallic metal layer region under regional 101CG1 of grounding ports top metal level and the 101CG2 accordingly with grounding ports top metal level zone 101CG1 and 101CG2.The coverage that is positioned at the intermetallic metal layer region under each metal level zone, port top is all in each metal level zone, port top coverage.
Grounding ports top metal level zone 101CG1 and 101CG2 and be positioned at intermetallic metal layer region under metal level zone, grounding ports top 101CG1 and the 101CG2 and the loop of the 1st metal level 201B successively is connected keep being connected thereby make between the loop of the regional 101CG1 of grounding ports top metal level and 101CG2 and the 1st metal level 201B.
Between top metal level 101C and the 1st metal level 201B, have under the situation of 7 intermediate metal layers, grounding ports top metal level zone 101CG1 is with 101CG2 and be positioned at metal level zone, grounding ports top 101CG1 and successively be connected with 101CG2 the 8th metal level zone to the 2 metal levels down loop regional and the 1st metal level 201B, keeps being connected thereby make between the loop of the regional 101CG1 of grounding ports top metal level and 101CG2 and the 1st metal level 201B.
At least remove one deck and be positioned at intermetallic metal layer region under signal port top metal level zone 101CS1 and the 101CS2.Wherein, with 4 layers of intermediate metal layer is example, can be positioned at the 2nd metal level zone under signal port top metal level zone 101CS1 and the 101CS2 by removal, and/or be positioned at the 3rd metal level zone under signal port top metal level zone 101CS1 and the 101CS2, and/or be positioned at signal port top metal level zone 101CS1 and 101CS2 the 4th metal level zone down, realize being connected of the regional 101CS1 of cut-off signal port top metal level and 101CS2 and the 1st metal level 201B.At this moment, with regard to the effect of going embedding to handle, the embedding treatment effect that goes of only removing the 2nd metal level zone that is positioned under signal port top metal level zone 101CS1 and the 101CS2 is better than the effect that only removal is positioned at the 3rd metal level zone under signal port top metal level zone 101CS1 and the 101CS2, that is to say, be arranged in the process of the intermetallic metal layer region under signal port top metal level zone 101CS1 and the 101CS2 in removal, the intermetallic metal layer region that is positioned under signal port top metal level zone 101CS1 and the 101CS2 that is connected with signal port top metal level zone 101CS1 and 101CS2 maintenance is many more, and the effect of going embedding to handle is just good more.
Fig. 2 D is the B cross-sectional view that the open circuit of little capacity MOS varactor according to an embodiment of the invention removes Fig. 2 B of embedding test structure.Shown in Fig. 2 D, at least remove and be arranged in signal port top metal level zone 101CS1 and 101CS2 the 8th metal level zone down to any one deck that is positioned at signal port top metal level zone 101CS1 and 101CS2 the 2nd metal level zone down, the regional 101CS1 of realization cut-off signal port top metal level and 101CS2 are connected with the 1st metal level 201B's.By being connected of cut-off signal port top metal level zone 101CS1 and 101CS2 and the 1st metal level 201B, making and realized disconnection between two signal port S.What need describe is, remove the schematic diagram that is positioned at the second metal level zone under signal port top metal level zone 101CS1 and the 101CS2 though only provided among Fig. 2 D, but those skilled in the art should understand, can expand fully to draw with reference to Fig. 2 D and remove the technical scheme that is positioned at other intermetallic metal layer regions under signal port top metal level zone 101CS1 and the 101CS2.The 1st metal level 201B comprises a loop, makes to have formed connection between two grounding ports top metal levels zone 101CG1 on the loop be connected to the 1st metal level 201B and the 101CG2, thereby four grounded port G is linked together.
Present embodiment is when opening a way the embedding test, each signal port S is disconnected each other, and make between each grounding ports G and be connected to each other, thereby avoided in the existing test structure situation about between the adjacent grounding ports G of two couples of two signal port S line direction both sides, disconnecting fully, satisfied the requirement of going embedding to handle.Simultaneously because the existence of each metal level under the metal level 101C of top, when going embedding to handle, not only can remove the parasitic capacitance that metal level above test structure in test structure top is introduced, can also in going the embedding processing procedure, make and wholely go in the embedding test structure parasitic capacitance between each metal interlevel under the metal level of top and each metal level and active area 209B itself to remove by removing the embedding test structure.Compared with prior art, parasitic capacitance of going the embedding test structure can effectively remove whole test structure of the present invention.Because the present invention only relates to the embedding test structure, therefore not to going the embedding processing procedure to be elaborated, those skilled in the art should understand, by the embedding test structure that goes of the present invention, go accordingly embedding to handle, can reach the purpose that little capacity MOS varactor of effective removal and variable capacitance diode go the parasitic capacitance in the embedding test structure.
Preferably; Signal port top metal level zone 101CS1 and 101CS2 can realize by following structure with disconnection between the 1st metal level 201B: signal port top metal level zone 101CS1 and 101CS2 be positioned at metal level zone, signal port top 101CS1 and the 8th metal level zone under the 101CS2 and successively be connected with the 3rd metal level zone under the 101CS2 to being positioned at the regional 101CS1 of signal port top metal level, thereby make the regional 101CS1 of signal port top metal level and 101CS2 and each the metal level joint area between the 3rd metal level zone under the regional 101CS1 of signal port top metal level and the 101CS2 together. By removal be positioned at signal port top metal level zone 101CS1 and 101CS2 down the 3rd metal level zone and the 1st metal level 201B between be positioned at the 2nd metal level zone under regional 101CS1 of signal port top metal level and the 101CS2; The 3rd metal level zone that realization is positioned under signal port top metal level zone 101CS1 and the 101CS2 is separated with the 1st metal level 201B; Thereby guarantee that signal port top metal level zone 101CS1 and 101CS2 and the 1st metal level 201B are separated; And the 1st metal level 201B comprises a loop in structure.Be connected between two grounding ports top metal levels zone 101CG1 on the loop of the 1st metal level 201B and 101CG2 and be connected with each other, and then 4 grounding ports G that are connected on the loop of the 1st metal level 201B by grounding ports top metal level zone 101CG1 and 101CG2 are connected to each other.
Present embodiment is being opened a way embedding when test, can make wholely to go in the embedding test structure parasitic capacitance between each metal interlevel under the metal level of top and each metal level and active area 209B itself to remove by removing the embedding test structure in going the embedding processing procedure.By the embedding test structure that goes of the present invention, go embedding to handle accordingly, can reach and remove the purpose that little capacity MOS varactor and variable capacitance diode go the parasitic capacitance in the embedding test structure fully.
Fig. 3 is the schematic diagram that the open circuit of little capacity MOS varactor according to an embodiment of the invention goes the tuning rate of change that the active zone area with the MOS varactor of embedding test structure increases.As shown in Figure 3, wherein, ordinate is tuning ratio Ratio, and abscissa is active zone area (um
2), wherein the active zone area is relevant with the structure of MOS varactor.As can be seen, increase along with the active zone area of MOS varactor, the embodiment of the invention go tuning ratio that the embedding test structure makes the MOS varactor near 10, this tuning ratio with MOS varactor in theory is very approaching, open circuit goes the embedding test structure to obtain the good embedding technique effect of going.
Fig. 4 is that the open circuit of little capacity MOS varactor according to a preferred embodiment of the invention removes the johning knot composition between the metal level of embedding test structure.As shown in Figure 4, the structure of this preferred embodiment may further include on the basis of the structure shown in Fig. 2 A to Fig. 2 D: be connected by through hole 401 between the metal level and between described the 1st metal level 201B and the active area 209B.
Specifically, through hole 401 is passages of reserving for metal connecting line 402 is passed in the medium of metal interlevel.What need describe is illustrate the medium of knowing the metal interlevel that do not draw in order to make among Fig. 4, and two through holes that only drawn to describe.Though provided circular through hole in the accompanying drawing of the present invention, the present invention is not limited thereto, all should include scope of the present invention in as long as can guarantee the through hole of the Any shape that metal wire can pass.
Through hole between top metal level 101C and the 8th metal level 208B is that the through hole that reaches between the 1st metal level 201B and described active area 209B between the bigger biserial through hole of diameter 401, the 8 metal level 208B to the 1 metal level 201B is three less row through holes of diameter.
Specifically, for make between top metal level 101C and the 8th metal level 208B be connected more solid and reliable, between top metal level 101C and the 8th metal level 208B, used the bigger biserial through hole 401 of diameter, and the through hole of all the other metal interlevels three less row through holes that are diameter.With regard to configuration aspects, the structure of these two kinds of through holes is the same, and difference only is the columns and the diameter of through hole, therefore, no longer three less row through holes of diameter is described in detail.What those skilled in the art should understand is; this preferred embodiment has only provided optimized technical scheme; but the present invention is not limited thereto; through hole columns and diameter can be selected according to the actual design needs fully, and these selections of being carried out on the basis of the disclosed technical scheme of the present invention all should be included protection scope of the present invention in.
The structure of a preferred embodiment of the present invention may further include on the basis of the structure shown in Fig. 2 A to Fig. 2 D: being positioned at grounding ports top metal level zone 101CG1 has identical structure and annexation with 2 metal level zones, the 8th metal level zone to the under the 101CG2.Be positioned at signal port top metal level zone 101CS1 and identical structure and annexation arranged with 2 metal level zones, the 8th metal level zone to the under the 101CS2.Adopt this centrosymmetric structure and annexation, can make test structure more carefully and neatly done, can save the design time of test structure.
The size of the size of metal level and used little capacity MOS varactor arrangement is complementary.
Specifically, because the size of used little capacity MOS varactor has difference in the test structure, therefore the size of test structure also can correspondingly be regulated, but this adjusting can not change each metal level that the present invention removes the embedding test structure, active area 209B, and the relative position relation and the annexation of each port, therefore, the modification to the metal level size and dimension also should be included scope of the present invention on the basis that does not change above-mentioned relation.
The size of metal level comprises the width and the length of described metal level.Specifically, the modification to the size of metal level mainly comprises the width of metal level and the modification of length.
Because the similitude of MOS varactor and the required test structure of variable capacitance diode, therefore, those skilled in the art are on the basis that does not change each metal level of embedding test structure, active area 209B, the relative position relation that reaches port and annexation, what the device correct that MOS varactor test structure is connected can obtain variable capacitance diode removes the embedding test structure, therefore, the embedding test structure that goes that comprises the variable capacitance diode of PN junction variable capacitance diode also should be included scope of the present invention in.
The present invention is when opening a way the embedding test, each signal port S is disconnected each other, and make between each grounding ports G and be connected to each other, thereby avoided in the existing test structure situation about between the adjacent grounding ports G of two couples of two signal port S line direction both sides, disconnecting fully, satisfied the requirement of going embedding to handle.Simultaneously because the existence of each metal level under the metal level 101C of top, when going embedding to handle, can in going the embedding processing procedure, make and wholely go in the embedding test structure parasitic capacitance between each metal interlevel under the metal level of top and each metal level and active area 209B itself to remove by removing the embedding test structure.Compared with prior art, parasitic capacitance of going the embedding test structure can effectively remove whole test structure of the present invention.Because the present invention only relates to the embedding test structure, therefore not to going the embedding processing procedure to be elaborated, those skilled in the art should understand, by the embedding test structure that goes of the present invention, go accordingly embedding to handle, can reach the purpose that little capacity MOS varactor of effective removal and variable capacitance diode go the parasitic capacitance in the embedding test structure.
The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. the open circuit of little capacity MOS varactor and variable capacitance diode removes the embedding test structure, it is characterized in that described open circuit goes the embedding test structure to comprise: a plurality of metal levels and active area;
Described a plurality of metal level comprises the top metal level, at least one intermediate metal layer between the 1st metal level that is connected with described active area and described top metal level and described the 1st metal level, and described the 1st metal level comprises a loop;
Described top metal level is divided into four mutual disjunct zones, described zone comprises: the metal level zone, two signal port tops that is connected with two signal ports respectively, and will be positioned at the metal level zone, two grounding ports tops that two adjacent grounding ports of described two signal port line direction homonymies link together respectively;
Described intermediate metal layer comprises with metal level zone, described signal port top and is positioned at the intermetallic metal layer region under the metal level zone, signal port top accordingly and is positioned at intermetallic metal layer region under the metal level zone, grounding ports top accordingly with metal level zone, described grounding ports top, and described intermetallic metal layer region under the metal level zone, signal port top and the described coverage that is positioned at the intermetallic metal layer region under the metal level zone, grounding ports top of being positioned at is all in the coverage in corresponding described signal port top metal level zone and metal level zone, described grounding ports top;
Described grounding ports top metal level zone and describedly be positioned at intermetallic metal layer region under the metal level zone, grounding ports top and the loop of described the 1st metal level successively is connected;
At least remove the described intermetallic metal layer region that is positioned under the metal level zone, signal port top of one deck, metal level zone, the described signal port of realization disconnection top is connected with described the 1st metal level.
2. open circuit according to claim 1 removes the embedding test structure, it is characterized in that, described intermediate metal layer has 7, comprising: by and described active area between ascending the 2nd metal level to the 8 metal levels that are arranged in order of distance;
Metal level zone, described grounding ports top successively is connected with the loop regional and described the 1st metal level of the 8th metal level zone to the 2 metal levels under being positioned at metal level zone, grounding ports top;
At least remove any one deck that is arranged in the 2 metal level zones, the 8th metal level zone to the under the metal level zone, signal port top, metal level zone, the described signal port of realization disconnection top is connected with described the 1st metal level.
3. open circuit according to claim 2 removes the embedding test structure, it is characterized in that, describedly remove described any one deck that is arranged in the 2 metal level zones, the 8th metal level zone to the under the metal level zone, signal port top at least and comprise: remove described the 2nd metal level zone that is positioned under the metal level zone, signal port top, metal level zone in described signal port top successively is connected with the described 3 metal level zones, the 8th metal level zone to that are positioned under the metal level zone, signal port top.
4. open circuit according to claim 2 removes the embedding test structure, it is characterized in that, is connected by through hole between described a plurality of metal levels and between described the 1st metal level and the described active area.
5. open circuit according to claim 4 removes the embedding test structure, it is characterized in that, the through hole of described top metal level and described the 8th metal interlevel is the bigger biserial through hole of diameter, and the through hole between described the 8th metal level to the 1 metal interlevel and described the 1st metal level and described active area is three less row through holes of diameter.
6. open circuit according to claim 2 removes the embedding test structure, it is characterized in that, there are identical structure and annexation in the described 2 metal level zones, the 8th metal level zone to that are positioned under the metal level zone, described grounding ports top.
7. open circuit according to claim 2 removes the embedding test structure, it is characterized in that, there are identical structure and annexation in the described 2 metal level zones, the 8th metal level zone to that are positioned under the metal level zone, described signal port top.
8. open circuit according to claim 1 removes the embedding test structure, it is characterized in that, the size of the size of described a plurality of metal levels and described little capacity MOS varactor or variable capacitance diode is complementary.
9. open circuit according to claim 8 removes the embedding test structure, it is characterized in that, the size of described a plurality of metal levels comprises the width and the length of described a plurality of metal levels.
10. open circuit according to claim 1 removes the embedding test structure, it is characterized in that, described variable capacitance diode comprises the PN junction variable capacitance diode.
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| CN103839921A (en) * | 2012-11-26 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Through si via radio frequency test structure and parasitic extracting method thereof |
| CN105428271A (en) * | 2015-12-22 | 2016-03-23 | 上海集成电路研发中心有限公司 | Modeling method for radio frequency MOS device and test structure |
| CN105891628A (en) * | 2016-03-30 | 2016-08-24 | 清华大学 | Universal four-port on-wafer high-frequency de-embedding method |
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| US6858890B2 (en) * | 2002-06-04 | 2005-02-22 | Infineon Technologies Aktiengesellschaft | Ferroelectric memory integrated circuit with improved reliability |
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| CN103839921A (en) * | 2012-11-26 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Through si via radio frequency test structure and parasitic extracting method thereof |
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| CN105428271A (en) * | 2015-12-22 | 2016-03-23 | 上海集成电路研发中心有限公司 | Modeling method for radio frequency MOS device and test structure |
| CN105428271B (en) * | 2015-12-22 | 2018-05-29 | 上海集成电路研发中心有限公司 | The modeling method and test structure of radio frequency MOS device |
| CN105891628A (en) * | 2016-03-30 | 2016-08-24 | 清华大学 | Universal four-port on-wafer high-frequency de-embedding method |
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| CN108899320A (en) * | 2018-07-20 | 2018-11-27 | 上海华力微电子有限公司 | A kind of MOSFET gate oxide capacitance calibration structure |
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