CN113641605A - Polling arbiter suitable for asynchronous circuit and method thereof - Google Patents
Polling arbiter suitable for asynchronous circuit and method thereof Download PDFInfo
- Publication number
- CN113641605A CN113641605A CN202110804144.2A CN202110804144A CN113641605A CN 113641605 A CN113641605 A CN 113641605A CN 202110804144 A CN202110804144 A CN 202110804144A CN 113641605 A CN113641605 A CN 113641605A
- Authority
- CN
- China
- Prior art keywords
- output
- arbitration
- signal
- data
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 12
- 230000007717 exclusion Effects 0.000 claims abstract description 21
- 230000004044 response Effects 0.000 claims abstract description 17
- 230000005540 biological transmission Effects 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 5
- 230000009471 action Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 3
- 241001522296 Erithacus rubecula Species 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
The invention discloses a polling arbiter suitable for an asynchronous circuit and a method thereof. The polling arbiter comprises an arbitration part, a mutual exclusion lock part and a multi-path selection part; the arbitration part is formed by cascading a plurality of levels of arbitration units, the input of the arbitration part is a request signal and weight information of each request, and the output of the arbitration part is a response signal reflecting an arbitration result; the mutual exclusion locking part is formed by cascading a plurality of stages of mutual exclusion units, the input of the mutual exclusion locking part is a response signal output from the arbitration part and a handshake signal output from the later stage pipeline structure, and the output of the mutual exclusion locking part is a gating signal and a handshake signal transmitted to the former stage pipeline structure; the input of the multi-path selection part is the gating signal and the input data output by the mutual exclusion lock part, and the output of the multi-path selection part is the valid data with the highest arbitration priority. The polling arbiter of the present invention is suitable for asynchronous circuits, and eliminates the dependence on the global clock.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a polling priority arbiter for routing scheduling of asynchronous circuits.
Background
An arbiter is a common structure for scheduling and allocating shared resources in a digital integrated system, and mainly functions to respond according to a certain rule according to a request for the shared resources. One common arbiter usage scenario is: in the bus system, a plurality of main modules share the same bus, each main module firstly sends a request to the arbiter before occupying the bus to transmit data, if the requests of a plurality of modules arrive at the same time, the arbiter determines the sequence of using the bus by each module according to the designed priority rule, so that the data transmission of each module can be executed in order, and the data loss or error caused by conflict is avoided.
One important characteristic of an arbiter is fairness. If the arbiter gives a fixed priority to requests from different modules, although the high priority module can transmit data without blocking, the request of the low priority module may not be responded to, and the bus is always occupied by the high priority module and the data of the low priority module is blocked. In view of the above problems, structures such as a variable priority arbiter, a round robin arbiter, etc. have appeared. A basic n-input polling arbitrator structure is shown in FIG. 1, and is composed of multiple stages of arbitrator units with weight input, D flip-flops, etc., wherein the output end Q of the D flip-flop is connected with the weight input port of the next stage of arbitrator unit, and there is only one weight signal p in the same clock cycleiAnd the priority level is set to be high, the priority level of the arbitration unit at the level is the highest, and the priority levels of the rest units are sequentially arranged in a descending order. For the sake of illustration, assuming that all data transmission processes can be completed in one clock cycle, in a certain clock cycle, if the i-th arbitration unit receives the request signal and has the highest priority in all arbitration units receiving valid requests, the response signal g of the arbitration unitiWith request signal riPulling high, the high level signal passes through the D flip-flop, and is transmitted to the weight input port of the i +1 th level arbitration unit when the next clock cycle arrives, namely pi+1Will be set to high level, in which clock cycle the i +1 th level arbitration unit has the highest priority, and the above circuit action completes the update of the whole arbiter weight. When there is no clock cycleAny valid request signal, i.e. riWhen all are 0, giAll 0, if updated to piAll 0 s will cause arbitration failure, so a logic gate structure composed of a multi-input NOR gate and a multi-stage NAND gate is added between the arbitration unit and the D flip-flop, which has the function when g isiAll 0 s, the D flip-flop passes the original p in the next clock cycleiSignals, i.e. all piThe signals remain unchanged, with the priority unchanged, until one or more request signals are pulled high and updated.
The arbitration unit in the polling arbiter is essentially an arbitration unit structure with variable weights, and is composed of a plurality of logic gates, as shown in fig. 2. For an n-level cascade arbitration structure, the response signal g output by the i-th level arbitration unitiThe essential conditions for the drawing-up are as follows: 1. request signal riActive, put at high level; 2. carry input signal c from stage i-1iPull-up, or weight, signal piIs placed at a high level. Carry signal c for outputting the ith stage arbitration unit to the (i + 1) th stagei+1The essential conditions for the drawing-up are as follows: 1. request signal riInvalid, put low level; 2. carry input signal c from stage i-1iPull-up, or weight, signal piIs placed at a high level. Therefore, the structure ensures that at most one response signal g exists in the same clock cycleiAt high level, the carry signal ensures the priority of each stage of arbitration unit to be weighted by the weight signal piThe ith-stage units which are put at high level start to be sequentially arranged in descending order.
Under the circumstances that the requirements for the speed and the power consumption of an integrated circuit are more and more strict, particularly along with the rise and the wide application of a system on a chip and a network on a chip, the realization of a global synchronous clock is more and more difficult, and the problem of the power consumption generated by the clock can not be well solved; asynchronous circuits that do not rely on a global clock are therefore gaining increasing attention as a promising solution. However, the polling arbiter is only applicable to synchronous circuits, needs to update the weights by using a D flip-flop and a synchronous clock signal, and is not applicable to asynchronous circuits.
Disclosure of Invention
In order to overcome the defects of the prior art and solve the problem that the conventional polling arbitration structure is not suitable for an asynchronous circuit, the invention aims to design a polling arbiter suitable for the asynchronous circuit and a method thereof, and the dependence on a global clock is eliminated.
The technical scheme adopted by the invention is as follows:
a polling arbiter adapted for an asynchronous circuit, the polling arbiter comprising an arbitration section, a mutual exclusion lock section, and a multiplexing section; the arbitration part is formed by cascading a plurality of levels of arbitration units, the input of the arbitration part is a request signal and weight information of each request, and the output of the arbitration part is a response signal reflecting an arbitration result; the mutual exclusion locking part is formed by cascading a plurality of stages of mutual exclusion units, the input of the mutual exclusion locking part is a response signal output from the arbitration part and a handshake signal output from the later stage pipeline structure, and the output of the mutual exclusion locking part is a gating signal and a handshake signal transmitted to the former stage pipeline structure; the input of the multi-path selection part is the gating signal and the input data output by the mutual exclusion lock part, and the output of the multi-path selection part is the valid data with the highest arbitration priority.
Further, the mutual exclusion unit is formed by cascading a plurality of stages of C units and a multi-input NOT gate.
The arbitration method of the polling arbiter is utilized by the invention, and the specific process is as follows: assume that the polling arbiter with n inputs receives multiple valid request signals at the same time, i.e. ri，ri+m0，ri+m1,，……,ri+mnPull high, data _ ini，data_ini+m0，data_ini+m1,，……,data_ini+mnIs a non-empty effective input, wherein m0 is more than m1 is more than … … is more than mn, the integers are positive integers, i is more than or equal to 0 and more than i + mn is more than or equal to n; suppose that weight information p requested at this time q1, i.e. the q-th arbitration unit has the highest priority; at this time, the priority is calculated in descending order from the q-level by the request signal rsObtaining the response signal g with the highest priority and output by the corresponding exclusive lock partsIs pulled up when q is present<When s is less than or equal to n, the value of s satisfies (s-q) minimum, otherwise, the value of s satisfies (q-s) maximum; the exclusive lock part being responsive to the signal gsAfter being pulled upThe corresponding strobe signal selsPull high, multiplex part will data _ insOutput as valid data; after the multi-path selection part finishes the output of the data _ out, the handshake signal ack _ in transmitted by the later stage pipeline structure is pulled high, so that the C unit of the s-th stage mutex unit outputs the handshake signal ack _ outsThen pulling up to inform the former-stage unit that the data transmission is completed; the rest handshake signals transmitted to the preceding stage are still kept low, and the weight information ps+1The weight signals are pulled high, and the rest weight signals are set low, so that the updating of the weight information is completed; in this case, the priorities are calculated in descending order starting from the s +1 level, based on the request signal rjObtaining the response signal g with the highest priority and output by the corresponding exclusive lock partjIs pulled up when s is present<When j is less than or equal to n, the value of j satisfies (j-s) minimum, otherwise, the value of j satisfies (s-j) maximum; but the handshake signal ack _ out is due to the characteristics of the C-cellsStill remains 1, all other strobe signals are 0, so the j-th stage strobe signal is actually latched in the mutex; until the data _ insAfter the transmission is finished and the next stage pipeline confirms the reception, the global pipeline carries out reset action, the handshake signal ack _ in is pulled down, the jth stage strobe signal is unlocked, and the corresponding strobe signal seljPull-up, output handshake signal ack _ outjPull high, multiplex part will data _ injOutput as valid data; after the multi-path selection part finishes the output of the data _ out, the handshake signal ack _ in transmitted by the post-stage pipeline structure is pulled high, so that the C unit of the j-th stage exclusive unit outputs the handshake signal ack _ outjThen pulling up to inform the former-stage unit that the data transmission is completed; the rest handshake signals transmitted to the preceding stage are still kept low, and the weight information pj+1The weight signals are pulled high, the rest weight signals are set low, the weight information is updated again, and the process is continuously repeated.
The invention is based on a basic polling arbitration structure, replaces a D trigger by a mutual exclusion lock part constructed by a multistage C unit and a multi-input non-AND gate cascade, and realizes the polling arbiter suitable for an asynchronous circuit by orderly updating weight information and orderly outputting data by means of handshake signals of a pipeline structure.
Drawings
Fig. 1 is a diagram illustrating a basic structure of an n-input polling arbiter in the prior art.
Fig. 2 is a diagram illustrating a basic arbitration unit structure in the prior art.
FIG. 3 is a schematic diagram of a polling arbiter for asynchronous circuits according to the present invention.
FIG. 4 is a diagram of a mutex unit according to an embodiment of the present invention.
Fig. 5 is a circuit diagram of a C unit according to an embodiment of the present invention.
Detailed Description
The polling arbiter structure suitable for the asynchronous circuit adopted by the invention is shown in fig. 3, and the arbiter comprises an arbitration part, a mutual exclusion lock part and a multi-path selection part by means of a pipeline structure of the asynchronous circuit. Wherein the arbitration part is formed by cascading multiple stages of arbitration units shown in FIG. 2, r0To rnFor request signals, p0To pnFor each request weight information, output g0To gnA response signal reflecting the arbitration result.
The mutual exclusion lock part is formed by cascading a plurality of mutually exclusive units as shown in FIG. 4, and the input is except for the response signal g obtained from the arbitration part0To gnAnd ack _ in handshake signals obtained from the pipeline structure of the later stage, and sel is output0To selnAck _ out as a strobe signal0To ack _ outnA handshake signal transmitted to the front-stage pipeline structure; input of multiplex section other than sel0To selnFurther includes data _ in0To data _ innThe data with the highest arbitration priority is output as data _ out, and the function of the part is described as follows: when and only when the communication signal seliPull high while data _ iniFor valid data input, the data _ out has valid output data _ ini. In addition, the C unit used by the mutex lock portion is a circuit structure of a Muller C unit, and as shown in fig. 5, the function of the C unit is described as follows: when the two inputs are all 0, the output is set to 0; when the two inputs are all 1, the output is set to 1; if not, then,the output does not change.
The working principle and process of the polling arbiter of the present embodiment are described as follows:
assume that a polling arbiter having n inputs receives multiple valid request signals at the same time, i.e., ri，ri+m0，ri+m1,，……,ri+mn(m0 is more than m1 is more than m … … is more than mn and is a positive integer, i is more than or equal to 0 and is more than i + mn is more than or equal to n) pull-up height, data _ ini，data_ini+m0，data_ini+m1,，……,data_ini+mnFor non-null valid inputs, assume that p is now presentqIs 1, i.e. the q-th arbitration unit has the highest priority. At this time, the priority is calculated in descending order from the q-level, and there is a request signal rsObtaining the response signal g with the highest priority and corresponding outputsAnd (5) drawing high. The exclusive lock part is in gsAfter being pulled high, the corresponding strobe signal selsPull high, multiplex part will data _ insOutput as valid data; after the data _ out is output, the ack _ in signal transmitted by the pipeline structure of the later stage is pulled high, so the C unit of the s-th stage exclusive unit outputs a handshake signal ack _ outsThen pulling up to inform the former-stage unit that the data transmission is completed; the remaining handshake signals transmitted to the preceding stage remain low, ps+1The weight signals are pulled high, and the rest weight signals are set low, so that the update of the weight information is completed.
At this time, the priorities are calculated in descending order from the s +1 level, and there is a request signal rjObtaining the response signal g with the highest priority and corresponding outputjAnd (5) drawing high. But ack _ out due to the characteristics of the C cellsStill remains at 1 and all remaining strobe signals are 0, so the strobe signal of the j-th stage is effectively "latched" in the mutex. Up to data _ insAfter the data transmission is finished and the next stage pipeline confirms the reception, the overall pipeline carries out reset action, ack _ in is pulled low, the gating signal of the j stage is unlocked, and the corresponding gating signal seljPull-up, output handshake signal ack _ outjPull high, multiplex part will data _ injOutput as valid data; after the data _ out is output, the ack _ in signal transmitted from the next stage pipeline structure is pulled high, so that the j-th stage mutexThe C unit of the unit outputs a handshake signal ack _ outjThen pulling up to inform the former-stage unit that the data transmission is completed; the remaining handshake signals transmitted to the preceding stage remain low, pj+1The weight signals are pulled high, the rest weight signals are set low, the weight information is updated again, and the process is continuously repeated.
Claims (3)
1. A polling arbitrator suitable for asynchronous circuit, wherein the polling arbitrator includes arbitrating part, exclusive lock part and multipath selection part; the arbitration part is formed by cascading a plurality of levels of arbitration units, the input of the arbitration part is a request signal and weight information of each request, and the output of the arbitration part is a response signal reflecting an arbitration result; the mutual exclusion locking part is formed by cascading a plurality of stages of mutual exclusion units, the input of the mutual exclusion locking part is a response signal output from the arbitration part and a handshake signal output from the later stage pipeline structure, and the output of the mutual exclusion locking part is a gating signal and a handshake signal transmitted to the former stage pipeline structure; the input of the multi-path selection part is the gating signal and the input data output by the mutual exclusion lock part, and the output of the multi-path selection part is the valid data with the highest arbitration priority.
2. The polling arbiter of claim 1 wherein the mutex unit comprises a multi-stage C unit and a multi-input nand gate cascade.
3. The arbitration method using the polling arbiter adapted for asynchronous circuit as claimed in claim 1, wherein the method comprises the following steps:
assume that the polling arbiter with n inputs receives multiple valid request signals at the same time, i.e. ri，ri+m0，ri+m1,，……,ri+mnPull high, data _ ini，data_ini+m0，data_ini+m1,，……,data_ini+mnIs a non-empty effective input, wherein m0 is more than m1 is more than … … is more than mn, the integers are positive integers, i is more than or equal to 0 and more than i + mn is more than or equal to n; suppose that weight information p requested at this timeq1, i.e. the q-th arbitration unit has the highest priority; at this time, the priority is calculated in descending order from the q-level by the request signal rsObtaining the response signal g with the highest priority and output by the corresponding exclusive lock partsIs pulled up when q is present<When s is less than or equal to n, the value of s satisfies (s-q) minimum, otherwise, the value of s satisfies (q-s) maximum; the exclusive lock part being responsive to the signal gsAfter being pulled high, the corresponding strobe signal selsPull high, multiplex part will data _ insOutput as valid data; after the multi-path selection part finishes the output of the data _ out, the handshake signal ack _ in transmitted by the later stage pipeline structure is pulled high, so that the C unit of the s-th stage mutex unit outputs the handshake signal ack _ outsThen pulling up to inform the former-stage unit that the data transmission is completed; the rest handshake signals transmitted to the preceding stage are still kept low, and the weight information ps+1The weight signals are pulled high, and the rest weight signals are set low, so that the updating of the weight information is completed; in this case, the priorities are calculated in descending order starting from the s +1 level, based on the request signal rjObtaining the response signal g with the highest priority and output by the corresponding exclusive lock partjIs pulled up when s is present<When j is less than or equal to n, the value of j satisfies (j-s) minimum, otherwise, the value of j satisfies (s-j) maximum; but the handshake signal ack _ out is due to the characteristics of the C-cellsStill remains 1, all other strobe signals are 0, so the j-th stage strobe signal is actually latched in the mutex; until the data _ insAfter the transmission is finished and the next stage pipeline confirms the reception, the global pipeline carries out reset action, the handshake signal ack _ in is pulled down, the jth stage strobe signal is unlocked, and the corresponding strobe signal seljPull-up, output handshake signal ack _ outjPull high, multiplex part will data _ injOutput as valid data; after the multi-path selection part finishes the output of the data _ out, the handshake signal ack _ in transmitted by the post-stage pipeline structure is pulled high, so that the C unit of the j-th stage exclusive unit outputs the handshake signal ack _ outjThen pulling up to inform the former-stage unit that the data transmission is completed; the rest handshake signals transmitted to the preceding stage are still kept low, and the weight information pj+1The weight signals are pulled high, and the rest weight signals are set lowAnd finishing the updating of the weight information again, and continuously repeating the process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110804144.2A CN113641605A (en) | 2021-07-16 | 2021-07-16 | Polling arbiter suitable for asynchronous circuit and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110804144.2A CN113641605A (en) | 2021-07-16 | 2021-07-16 | Polling arbiter suitable for asynchronous circuit and method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113641605A true CN113641605A (en) | 2021-11-12 |
Family
ID=78417521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110804144.2A Pending CN113641605A (en) | 2021-07-16 | 2021-07-16 | Polling arbiter suitable for asynchronous circuit and method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113641605A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114925004A (en) * | 2022-07-19 | 2022-08-19 | 中科声龙科技发展（北京）有限公司 | Polling arbitrator and its polling arbitrating method and chip |
| CN114968866A (en) * | 2022-08-01 | 2022-08-30 | 中科声龙科技发展（北京）有限公司 | Priority group polling arbitrator and arbitrating method thereof, cross bar switch and chip |
| CN115080474A (en) * | 2022-07-19 | 2022-09-20 | 中科声龙科技发展（北京）有限公司 | Weighted polling arbitrator and polling arbitrating method and chip thereof |
| CN115686864A (en) * | 2022-11-17 | 2023-02-03 | 沐曦集成电路(南京)有限公司 | Arbitration system |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030151425A1 (en) * | 2002-02-12 | 2003-08-14 | Hagedorn Michael S. | Asynchronous serial poll circuit |
| US20120047310A1 (en) * | 2009-02-13 | 2012-02-23 | The Regents Of The University Of Michigan | Crossbar circuitry for applying a pre-selection prior to arbitration between transmission requests and method of operation of such crossbar circuitry |
| US8521930B1 (en) * | 2010-02-25 | 2013-08-27 | Fresco Logic, Inc. | Method and apparatus for scheduling transactions in a host-controlled packet-based bus environment |
| CN106970842A (en) * | 2017-03-27 | 2017-07-21 | 南京大学 | A kind of dynamic reconfigurable real time signal processing load balance system |
| CN107315703A (en) * | 2017-05-17 | 2017-11-03 | 天津大学 | Double priority level control type fair arbitration device |
| CN111475439A (en) * | 2020-04-08 | 2020-07-31 | 北京龙鼎源科技股份有限公司 | Communication control method and device based on asynchronous transmission protocol and electronic equipment |
| CN112052206A (en) * | 2020-08-31 | 2020-12-08 | 浙江双成电气有限公司 | Multi-port data storage system based on arbitration |
-
2021
- 2021-07-16 CN CN202110804144.2A patent/CN113641605A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030151425A1 (en) * | 2002-02-12 | 2003-08-14 | Hagedorn Michael S. | Asynchronous serial poll circuit |
| US20120047310A1 (en) * | 2009-02-13 | 2012-02-23 | The Regents Of The University Of Michigan | Crossbar circuitry for applying a pre-selection prior to arbitration between transmission requests and method of operation of such crossbar circuitry |
| US8521930B1 (en) * | 2010-02-25 | 2013-08-27 | Fresco Logic, Inc. | Method and apparatus for scheduling transactions in a host-controlled packet-based bus environment |
| CN106970842A (en) * | 2017-03-27 | 2017-07-21 | 南京大学 | A kind of dynamic reconfigurable real time signal processing load balance system |
| CN107315703A (en) * | 2017-05-17 | 2017-11-03 | 天津大学 | Double priority level control type fair arbitration device |
| CN111475439A (en) * | 2020-04-08 | 2020-07-31 | 北京龙鼎源科技股份有限公司 | Communication control method and device based on asynchronous transmission protocol and electronic equipment |
| CN112052206A (en) * | 2020-08-31 | 2020-12-08 | 浙江双成电气有限公司 | Multi-port data storage system based on arbitration |
Non-Patent Citations (3)
| Title |
|---|
| SYED RAMEEZ NAQVI等: "Artificial Neural Networks based Dynamic Priority Arbitration for Asynchronous Flow Control", 《NEURAL COMPUTING AND APPLICATIONS》, 27 August 2016 (2016-08-27), pages 627 - 637, XP036470905, DOI: 10.1007/s00521-016-2571-6 * |
| YANG YINTANG等: "An Asynchronous Adaptive Priority Round-Robin arbiter Based on Four-Phase Dual-rail Protocol", 《CHINESE JOURNAL OF ELECTRONICS》, vol. 24, no. 1, 31 January 2015 (2015-01-31), pages 1 - 7, XP006072624, DOI: 10.1049/cje.2015.01.001 * |
| 谢林等: "3D NoC 网络架构设计", 《计算机工程》, vol. 39, no. 9, 15 September 2013 (2013-09-15), pages 150 - 152 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114925004A (en) * | 2022-07-19 | 2022-08-19 | 中科声龙科技发展（北京）有限公司 | Polling arbitrator and its polling arbitrating method and chip |
| CN115080474A (en) * | 2022-07-19 | 2022-09-20 | 中科声龙科技发展（北京）有限公司 | Weighted polling arbitrator and polling arbitrating method and chip thereof |
| CN114925004B (en) * | 2022-07-19 | 2022-10-21 | 中科声龙科技发展（北京）有限公司 | Polling arbitrator and its polling arbitrating method and chip |
| CN115080474B (en) * | 2022-07-19 | 2022-12-02 | 中科声龙科技发展（北京）有限公司 | Weighted polling arbitrator and polling arbitrating method and chip thereof |
| WO2024016647A1 (en) * | 2022-07-19 | 2024-01-25 | 声龙(新加坡)私人有限公司 | Weighted polling arbiter and polling arbitration method therefor, and chip |
| WO2024016646A1 (en) * | 2022-07-19 | 2024-01-25 | 声龙(新加坡)私人有限公司 | Polling arbiter and polling arbitration method therefor, and chip |
| CN114968866A (en) * | 2022-08-01 | 2022-08-30 | 中科声龙科技发展（北京）有限公司 | Priority group polling arbitrator and arbitrating method thereof, cross bar switch and chip |
| CN114968866B (en) * | 2022-08-01 | 2022-11-01 | 中科声龙科技发展（北京）有限公司 | Priority group polling arbitrator and arbitrating method thereof, cross bar switch and chip |
| CN115686864A (en) * | 2022-11-17 | 2023-02-03 | 沐曦集成电路(南京)有限公司 | Arbitration system |
| CN115686864B (en) * | 2022-11-17 | 2023-09-15 | 沐曦集成电路(南京)有限公司 | Arbitration system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113641605A (en) | Polling arbiter suitable for asynchronous circuit and method thereof | |
| CN106992770B (en) | Clock circuit and method for transmitting clock signal | |
| US6246256B1 (en) | Quantized queue length arbiter | |
| US9372818B2 (en) | Proactive quality of service in multi-matrix system bus | |
| CN110083563B (en) | Arbitration circuit for realizing fair arbitration based on cyclic priority | |
| CN1493036A (en) | Global interrupt and barrier network | |
| US9842180B2 (en) | NoC timing power estimating device and method thereof | |
| US4016539A (en) | Asynchronous arbiter | |
| EP1468372B1 (en) | Asynchronous crossbar with deterministic or arbitrated control | |
| EP0892352A1 (en) | Computer system with a bus having a segmented structure | |
| JPS5876961A (en) | External scheduling method | |
| JP2016167726A (en) | Arithmetic processing unit, information processor, and control method for information processor | |
| US8106683B2 (en) | One phase logic | |
| CN114816739B (en) | On-chip network increment task mapping method for load balancing | |
| CN107315703B (en) | Dual priority control type fair arbiter | |
| CN114374651A (en) | Transport flow control method, network on chip, electronic device, and storage medium | |
| US5572687A (en) | Method and apparatus for priority arbitration among devices in a computer system | |
| CN102937915B (en) | For hardware lock implementation method and the device of polycaryon processor | |
| US8145823B2 (en) | Parallel wrapped wave-front arbiter | |
| US20240193116A1 (en) | Event-driven readout system with non-priority arbitration for multichannel data sources | |
| Kutuzov et al. | Crossbar switch arbitration with traffic control for NoC | |
| CN106933663B (en) | A kind of multithread scheduling method and system towards many-core system | |
| Imai et al. | N-way ring and square arbiters | |
| CN111597138B (en) | Multi-concurrency RAM data transmission method and structure of X-type link structure | |
| Ramanathan | Deadlock Free Hardware Router with Dynamic Arbiter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |