CN114925004B - Polling arbitrator and its polling arbitrating method and chip - Google Patents
Polling arbitrator and its polling arbitrating method and chip Download PDFInfo
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- CN114925004B CN114925004B CN202210844780.2A CN202210844780A CN114925004B CN 114925004 B CN114925004 B CN 114925004B CN 202210844780 A CN202210844780 A CN 202210844780A CN 114925004 B CN114925004 B CN 114925004B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a polling arbiter, a polling arbitration method and a chip thereof. Wherein the polling arbiter comprises: at least two arbitration circuits, a priority control circuit and an output circuit; each arbitration circuit is connected with a request source; each arbitration circuit is sequentially connected into a ring and is respectively connected with the output circuit and the priority control circuit; the output circuit is connected with a target device; each arbitration circuit responds to the highest priority control signal sent by the priority control circuit or an enabling control signal sent by the previous arbitration circuit based on no request of the connected request source, transmits the request sent by the connected request source to the output circuit and sends the request to the target equipment through the output circuit, or sends the enabling control signal to the next arbitration circuit based on no request of the connected request source; the priority control circuit is also connected with each request source, and adjusts the highest priority control signal based on the request of the request source. The invention can make a plurality of request sources obtain arbitration more uniformly.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a polling arbiter, a polling arbitration method and a chip thereof.
Background
In a computer structure, when a plurality of request sources request the same resource simultaneously, if the resource can only accept one request, an arbitration structure is needed, if the plurality of request sources need to obtain the resource uniformly, polling arbitration is needed, otherwise, a certain request source always occupies the resource, so that other request sources cannot obtain the resource, and the performance of a computing function is influenced.
Disclosure of Invention
The invention provides a polling arbiter, an arbitration method and a chip thereof, which can enable a plurality of request sources to obtain arbitration more uniformly.
In a first aspect, the present invention provides a polling arbiter, comprising: at least two arbitration circuits, a priority control circuit and an output circuit; wherein the content of the first and second substances,
each arbitration circuit is connected with a request source; the arbitration circuits are sequentially connected to form a ring and are respectively connected with the output circuit and the priority control circuit; the output circuit is connected with a target device;
each arbitration circuit responds to the highest priority control signal sent by the priority control circuit or an enable control signal sent by the previous arbitration circuit based on no request of the connected request source, transmits the request sent by the connected request source to the output circuit and sends the request to the target equipment through the output circuit, or sends the enable control signal to the next arbitration circuit based on no request of the connected request source;
the priority control circuit is also respectively connected with the corresponding request source of each arbitration circuit, and adjusts the highest priority control signal based on the request of the request source.
According to the polling arbiter provided by the invention, each arbitration circuit comprises a first OR gate, a NOT gate, a first AND gate and a second AND gate;
the first input end of the first OR gate is connected with one output end of the priority control circuit, the second input end of the first OR gate is connected with the previous arbitration circuit, and the output end of the first OR gate is respectively connected with the first input ends of the first AND gate and the second AND gate;
the second input end of the first AND gate is connected with a corresponding request source, and the output end of the first AND gate is connected with one input end of the output circuit;
and the second input end of the second AND gate is connected with the output end of the NOT gate, the input end of the NOT gate is connected with the corresponding request source, and the output end of the second AND gate is connected with the next arbitration circuit.
According to the polling arbiter provided by the invention, each arbitration circuit is also respectively connected with the target device;
each of the arbitration circuits transmits a request issued by the connected request source to the output circuit based on the target device being in a ready state.
According to the polling arbiter provided by the invention, each arbitration circuit further comprises a third and gate; and the first input end of the third AND gate is connected with the output end of the first AND gate, the second input end of the third AND gate is connected with the target device, and the output end of the third AND gate is connected with the corresponding request source.
According to the polling arbiter provided by the invention, the priority control circuit is also connected with the target device;
the priority control circuit issues the highest priority control signal based on the target device being in a ready state.
According to the polling arbiter provided by the present invention, the priority control circuit determines the one of the arbitration circuits having a highest priority in the current clock cycle with a request;
determining the priority order of each arbitration circuit in the next clock cycle based on the determined priority order of the arbitration circuit with the highest priority and the preset arbitration circuit;
adjusting the highest priority control signal based on the determined priority order of each of the arbitration circuits for the next clock cycle.
According to the polling arbiter provided by the present invention, the priority control circuit keeps the highest priority control signal unchanged based on that each request source has no request.
According to the polling arbiter provided by the invention, the output circuit comprises a second or gate, an input end of the second or gate is connected with each arbitration circuit, and an output end of the second or gate is connected with the target device.
In a second aspect, the present invention further provides a polling arbitration method applied to the polling arbiter in the first aspect, where the method includes:
determining one of said arbitration circuits currently having a highest priority in response to a highest priority control signal issued by said priority control circuit;
transmitting a request sent by the connected request source to the output circuit, and sending the request to the target equipment through the output circuit, or sending an enabling control signal to the next arbitration circuit based on no request of the connected request source;
and in response to the enabling control signal issued by the former arbitration circuit based on no request of the connected request source, the latter arbitration circuit is taken as the arbitration circuit with the highest priority currently.
In a third aspect, the present invention further provides a chip, including the polling arbiter in the first aspect.
The invention provides a polling arbitrator and a polling arbitrating method and a chip thereof, wherein each arbitrator circuit is connected with a request source, more than two arbitrator circuits are connected in sequence to form a ring and are respectively connected with a priority control circuit and an output circuit, and are connected with a target device through the output circuit, so that each arbitrator circuit can respond to a highest priority control signal sent by the priority control circuit, or a previous arbitrator circuit transmits an enabling control signal sent by the connected request source to the output circuit based on the fact that the connected request source does not request, and sends the enabling control signal to the target device through the output circuit, or sends the enabling control signal to the next arbitrator circuit based on the fact that the connected request source does not request, wherein the priority control circuit is also respectively connected with the request sources corresponding to the arbitrator circuits, so as to adjust the highest priority control signal based on the request source, thus a plurality of request sources can be arbitrated more uniformly, the load balance of a system on chip using the arbitrator is ensured, higher data volume is maintained, higher efficiency and stability are achieved, and higher performance is ensured.
Drawings
In order to more clearly illustrate the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a block diagram of a polling arbiter according to an embodiment of the present invention;
FIG. 2 is a flow chart of a polling arbitration method provided by the present invention;
FIG. 3 is a block diagram of a polling arbiter according to another embodiment of the present invention;
FIG. 4 is a schematic flow chart of the priority control circuit adjusting the highest priority control signal according to the present invention;
FIG. 5 is a block diagram of a polling arbiter according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of the structure of the arbitration circuit shown in FIG. 5;
fig. 7 is a schematic diagram of the input and output ports of the priority control circuit of fig. 5.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a configuration of a polling arbiter according to an embodiment of the present invention. The polling arbiter provided by the present invention comprises: at least two arbitration circuits, a priority control circuit and an output circuit. Each arbitration circuit is connected with a request source, the arbitration circuits are sequentially connected to form a ring and are respectively connected with an output circuit and a priority control circuit, and the output circuit is connected with a target device. As shown in fig. 1, S00, S01, S02 are request sources, S4 is a polling arbiter, S5 is a target device where the requested resource is located, and the request sources S00, S01, S02 are connected to the target device S5 through the polling arbiter S4. The polling arbiter S4 includes: three arbitration circuits S10, S11, S12, one priority control circuit S2 and one output circuit S3. The arbitration circuit S10 is connected to the request source connection S00 to process a request from the request source S00, the arbitration circuit S11 is connected to the request source connection S01 to process a request from the request source S01, the arbitration circuit S12 is connected to the request source connection S02 to process a request from the request source S02, and the arbitration circuits S10, S11, and S12 are connected in sequence to form a ring. The priority control circuit S2 is connected to the arbitration circuits S10, S11, and S12, respectively, and adjusts the priorities of the arbitration circuits S10, S11, and S12. The output circuit S3 is connected to the arbitration circuits S10, S11, and S12, respectively, and summarizes the requests of the arbitration circuits S10, S11, and S12 to the target device S5.
Each arbitration circuit transmits a request from the connected request source to the output circuit and transmits the request to the target device through the output circuit in response to the highest priority control signal from the priority control circuit or an enable control signal from the previous arbitration circuit based on no request from the connected request source, or transmits an enable control signal to the next arbitration circuit based on no request from the connected request source. As shown in fig. 1, the arbitration circuit S10 transmits a request issued by the connected request source S00 to the output circuit S3 and transmitted to the target device S5 through the output circuit S3 in response to the highest priority control signal issued by the priority control circuit S2 or an enable control signal issued by the previous arbitration circuit S12 based on no request issued by the connected request source S02, or issues an enable control signal to the next arbitration circuit S11 based on no request issued by the connected request source S00. The arbitration circuit S11 transmits the request issued by the connected request source S01 to the output circuit S3 and transmits it to the target device S5 through the output circuit S3 in response to the highest priority control signal issued by the priority control circuit S2 or the enable control signal issued by the previous arbitration circuit S10 based on no request issued by the connected request source S00, or issues the enable control signal to the next arbitration circuit S12 based on no request issued by the connected request source S01. The arbitration circuit S12 transmits the request issued by the connected request source S02 to the output circuit S3 and transmits it to the target device S5 through the output circuit S3 in response to the highest priority control signal issued by the priority control circuit S2 or the enable control signal issued by the previous arbitration circuit S11 based on no request issued by the connected request source S01, or issues the enable control signal to the next arbitration circuit S10 based on no request issued by the connected request source S02.
The priority control circuit is also respectively connected with the corresponding request source of each arbitration circuit, and adjusts the highest priority control signal based on the request of the request source. As shown in fig. 1, the priority control circuit S2 is also connected to a request source S00 corresponding to the arbitration circuit S10, a request source S01 corresponding to the arbitration circuit S11, and a request source S02 corresponding to the arbitration circuit S12, respectively, and adjusts the highest priority control signal based on the requests of the request sources S00, S01, and S02.
FIG. 1 illustrates three arbitration circuits S10, S11, and S12 as an example, but the number of arbitration circuits in the polling arbiter is not limited in the embodiment of the present invention, the number of arbitration circuits in the polling arbiter can be determined according to the actual application requirements, and the number of arbitration circuits in the polling arbiter can be denoted as N, where N is an integer, and N ≧ 2.
Referring to fig. 2, fig. 2 is a schematic flow chart of a polling arbitration method according to the present invention. The round-robin arbitration method provided by the present invention is applied to the round-robin arbiter shown in fig. 1, and as shown in fig. 2, the round-robin arbitration method at least includes:
an arbitration circuit currently having the highest priority is determined 201 in response to the highest priority control signal from the priority control circuit.
202, transmitting the request from the connected request source to the output circuit and sending it to the target device through the output circuit, or sending an enable control signal to the next arbitration circuit based on no request from the connected request source.
The latter arbitration circuit is made the arbitration circuit currently having the highest priority in response to the previous arbitration circuit issuing an enable control signal based on no request from the connected request source 203.
The polling arbiter and the arbitration method thereof provided by the embodiments of the present invention are characterized in that each arbitration circuit is connected to one request source, more than two arbitration circuits are connected in sequence to form a ring, and are respectively connected to the priority control circuit and the output circuit, and are connected to a target device through the output circuit, so that each arbitration circuit can respond to a highest priority control signal sent by the priority control circuit, or a previous arbitration circuit transmits an enable control signal sent by the connected request source to the output circuit based on no request of the connected request source, and sends the request to the target device through the output circuit, or sends an enable control signal to a next arbitration circuit based on no request of the connected request source, wherein the priority control circuit is further connected to the request sources corresponding to the arbitration circuits, so as to adjust the highest priority control signal based on the request of the request source, so that a plurality of request sources can be arbitrated more uniformly, thereby ensuring load balance of a system on chip using the arbiter, maintaining higher throughput, having higher efficiency and stability, and ensuring higher performance.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a structure of a polling arbiter according to another embodiment of the present invention. The polling arbiter of fig. 3 differs from the polling arbiter of fig. 1 in that the respective arbitration circuits of the polling arbiter of fig. 3 are also respectively connected to the target device, and each arbitration circuit transmits a request from the connected request source to the output circuit based on the target device being in a ready state. As shown in fig. 3, the three arbitration circuits S10, S11, S12 of the polling arbiter S4 are also connected to the target device S5, respectively, the arbitration circuit S10 transmits a request issued by the connected request source S00 to the output circuit S3 based on the target device S5 being in the ready state, the arbitration circuit S11 transmits a request issued by the connected request source S01 to the output circuit S3 based on the target device S5 being in the ready state, and the arbitration circuit S12 transmits a request issued by the connected request source S02 to the output circuit S3 based on the target device S5 being in the ready state.
Optionally, the priority control circuit is further connected to the target device, and the priority control circuit issues the highest priority control signal based on the target device being in a ready state. As shown in fig. 3, the priority control circuit S2 is also connected to the target device S5, and the priority control circuit S2 issues the highest priority control signal based on the target device S5 being in the ready state.
Referring to fig. 4, fig. 4 is a schematic flow chart illustrating a priority control circuit adjusting a highest priority control signal according to the present invention. As shown in fig. 4, the priority control circuit adjusting the highest priority control signal based on the request of the request source includes at least:
401, the one arbitration circuit having the highest priority for the current clock cycle is determined to have the request.
The priority order of the arbitration circuits for the next clock cycle is determined based on the determined priority order of the requesting arbitration circuit having the highest priority and the predetermined arbitration circuit 402.
The highest priority control signal is adjusted 403 based on the determined priority order of the arbitration circuits for the next clock cycle.
Optionally, the priority control circuit keeps the priority control signal unchanged based on no request from each request source.
In the above embodiments, the arbitration circuit in the polling arbiter may be implemented by using a logic circuit. Referring to fig. 5, fig. 6 and fig. 7, fig. 5 is a schematic diagram of a polling arbiter according to another embodiment of the present invention, fig. 6 is a schematic diagram of an arbitration circuit in fig. 5, and fig. 7 is a schematic diagram of an input/output port of a priority control circuit in fig. 5. The polling arbiter of fig. 5 differs from the polling arbiter of fig. 1 in that each arbitration circuit of the polling arbiter of fig. 5 comprises an or gate S100, a not gate S110 and two and gates S120, S130.
As shown in fig. 6, each arbitration circuit includes three input terminals i1, i3, i4 and two output terminals o1, o3. The input terminal i1 is connected with a request source corresponding to the arbitration circuit, receives a request sent by the request source, the input terminal i3 is connected with a previous arbitration circuit of the arbitration circuit, receives an enable control signal sent by the previous arbitration circuit, the input terminal i4 is connected with an output terminal of the priority control circuit S2, and receives a priority control signal sent by the priority control circuit S2. The output end o1 is connected with one input end of the output circuit S3 to transmit the request to the output circuit S3, and the output end o3 is connected with the next arbitration circuit of the arbitration circuits and sends an enable control signal to the next arbitration circuit.
As shown in fig. 6, the first input terminal of the or gate S100 is the input terminal i4 of the arbitration circuit, the second input terminal of the or gate S100 is the input terminal i3 of the arbitration circuit, and the output terminal of the or gate S100 is connected to the first input terminals of the and gate S120 and the and gate S130, respectively. The second input terminal of the and gate S120 is the input terminal i1 of the arbitration circuit, and the output terminal of the and gate S120 is the output terminal o1 of the arbitration circuit. The second input end of the and gate S130 is connected to the output end of the nand gate S110, the input end of the not gate S110 is the input end i1 of the arbitration circuit, and the output end of the and gate S130 is the output end o3 of the arbitration circuit.
Optionally, as shown in fig. 5, each arbitration circuit may further include an and gate S140. As shown in fig. 6, each arbitration circuit may further include an input terminal i2 and an output terminal o2. The input end i2 is connected with the target device S5 and receives the status signal of the target device S5, and the output end o2 is connected with the request source corresponding to the arbitration circuit and sends the status of the target device S5 to the request source. The first input terminal of the and gate S140 is the output terminal o1 of the arbitration circuit, the second input terminal of the and gate S140 is the input terminal i2 of the arbitration circuit, and the output terminal of the and gate S140 is the output terminal o2 of the arbitration circuit.
The truth table for each input i1, i2, i3, i4 and output o1, o2, o3 of the arbitration circuit in FIG. 6 is shown in Table 1.
TABLE 1
Wherein x can be 1 or 0; i4 is 1 to indicate that the priority control circuit S2 sends the highest priority control signal, and i4 is 0 to indicate that the priority control circuit S2 does not send the highest priority control signal; i3 is 1 to indicate that the previous arbitration circuit sends out the enable control signal, and i3 is 0 to indicate that the previous arbitration circuit does not send out the enable control signal; i2 is 0, which means that the target device S5 is in a ready state; an i1 is 1 to indicate that the request source sends a request, and an i1 is 0 to indicate that the request source does not send a request; an o3 value of 1 indicates that the enable control signal is issued to the next arbitration circuit, and an o3 value of 0 indicates that the enable control signal is not issued to the next arbitration circuit; o2 being 0 indicates that the target device S5 is in the ready state; an o1 of 1 indicates that the request is transmitted to the output circuit S3, and an o1 of 0 indicates that the request is not transmitted to the output circuit S3.
As shown in fig. 7, the priority control circuit S2, alternatively referred to as a priority control module, includes three input terminals i1, i2, i3 and two output terminals o1, o2, o3. The input terminal i1 is connected to the request source S00 corresponding to the arbitration circuit S10 and receives the request from the request source S00, the input terminal i2 is connected to the request source S01 corresponding to the arbitration circuit S11 and receives the request from the request source S01, and the input terminal i3 is connected to the request source S02 corresponding to the arbitration circuit S12 and receives the request from the request source S02. The output terminal o1 is connected to the arbitration circuit S12, and transmits a priority control signal to the arbitration circuit S12, the output terminal o2 is connected to the arbitration circuit S11, and transmits a priority control signal to the arbitration circuit S11, and the output terminal o3 is connected to the arbitration circuit S10, and transmits a priority control signal to the arbitration circuit S10.
Alternatively, as shown in fig. 5, the priority control circuit S2 may also be connected to the target device S5. As shown in fig. 7, the priority control circuit S2 may further include an input terminal i4, where the input terminal i4 is connected to the target device S5 and receives a status signal of the target device S5.
The truth table of the inputs i1, i2, i3, i4 and the outputs o1, o2, o3 of the priority control circuit S2 in FIG. 7 is shown in Table 2.
TABLE 2
Wherein x can be 1 or 0; i4 is 1 to indicate that the target device S5 is in the ready state, and i4 is 0 to indicate that the target device S5 is not in the ready state; an i3 value of 1 indicates that the request source S02 sends out the request, and an i3 value of 0 indicates that the request source S02 does not send out the request; an i2 is 1, which means that the request source S01 sends out the request, and an i2 is 0, which means that the request source S01 does not send out the request; an i1 is 1, which means that the request source S00 sends out the request, and an i1 is 0, which means that the request source S00 does not send out the request; o3 being 1 means that the highest priority control signal is sent to the arbitration circuit S10, and o3 being 0 means that the highest priority control signal is not sent to the arbitration circuit S10; an o2 of 1 indicates that the highest priority control signal is transmitted to the arbitration circuit S11, and an o2 of 0 indicates that the highest priority control signal is not transmitted to the arbitration circuit S11; o1 being 1 means issuing to the arbitration circuit S12Sending the highest priority control signal, wherein o1 is 0, which means that the highest priority control signal is not sent to the arbitration circuit S12; o3 n 、o2 n And o1 n Indicating the current clock cycle, o3 n+1 、o2 n+1 And o1 n+1 Indicating the next clock cycle; of the outputs o1, o2, o3 of the priority control circuit S2, 1 is output at the same time and only 1 output, so that the arbitration circuit has the highest priority, for example, the output of the priority control circuit S2 is o3=0, o2=0, o1=1 in the initial state, and the arbitration circuit S10 has the highest priority.
As shown in fig. 5, the priority control circuit S2 controls the arbitration circuits S10, S11, and S12 through S102, S112, and S122 to have a priority order of S10> S11> S12, where the arbitration circuit S10 has the highest priority, and if the request source S00 has a request to the arbitration circuit S10, the request from the request source S00 will reach the target device S5 through the arbitration circuit S10 and the output circuit S3, and the priority control circuit S2 will adjust the priority order of the arbitration circuits S10, S11, and S12 through S102, S112, and S122 to be S11> S12> S10.
If the request source S01 has a request to the arbitration circuit S11, since the arbitration circuit S11 is the port with the highest priority, the request from the request source S01 will reach the target device S5 through the arbitration circuit S11 and the output circuit S3, and the priority control circuit S2 will adjust the priority order of the arbitration circuits S10, S11, S12 to S12> S10> S11 through S102, S112, S122.
If the request source S01 has no request to the arbitration circuit S11, the arbitration circuit S11 will enable the arbitration circuit S12, and if the request source S02 has a request to the arbitration circuit S12, since the arbitration circuit S12 is the port with a request with the highest priority, the request from the request source S02 will reach the target device S5 through the arbitration circuit S12 and the output circuit S3, and the priority control circuit S2 will adjust the priority order of the arbitration circuits S10, S11, S12 to S10> S11> S12 through S102, S112, S122.
If the request source S01 does not send a request to the arbitration circuit S11, the arbitration circuit S11 will enable the arbitration circuit S12, if the request source S02 does not send a request to the arbitration circuit S12, the arbitration circuit S12 will enable the arbitration circuit S10, if the request source S00 sends a request to the arbitration circuit S10, since the arbitration circuit S10 is the port with the highest priority, the request from the request source S00 will reach the target device S5 through the arbitration circuit S10 and the output circuit S3, and the priority control circuit S2 will adjust the priority order of the arbitration circuits S10, S11, S12 to S11> S12> S10 through S102, S112, S122.
If there is no request from any of the three request sources S00, S01, and S02, the priority control circuit S2 will keep the priority unchanged, wait for the request from the request sources S00, S01, and S02, and adjust the priority order of the arbitration circuits S10, S11, and S12 through S102, S112, and S122.
Alternatively, the output circuit in the polling arbiter may also be implemented using a logic circuit. As shown in fig. 5, the output circuit S3 may include an or gate S150, an input terminal of the or gate S150 being connected to each of the arbitration circuits S10, S11, S12, and an output terminal of the or gate S150 being connected to the target device S5.
The polling arbiter provided by the embodiment of the invention realizes the arbitration circuit and the output circuit through the logic circuit, can shorten a critical path, improves the working frequency, and enables the circuit scale to be smaller and the power consumption to be lower.
The present invention also provides a chip that may include the polling arbiter of fig. 1, 3, or 5.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A polling arbiter, comprising: at least two arbitration circuits, a priority control circuit and an output circuit; wherein the content of the first and second substances,
each arbitration circuit is connected with a request source; the arbitration circuits are sequentially connected to form a ring and are respectively connected with the output circuit and the priority control circuit; the output circuit is connected with a target device;
each arbitration circuit responds to the highest priority control signal sent by the priority control circuit or an enable control signal sent by the previous arbitration circuit based on no request of the connected request source, transmits the request sent by the connected request source to the output circuit and sends the request to the target equipment through the output circuit, or sends the enable control signal to the next arbitration circuit based on no request of the connected request source;
the priority control circuit is also respectively connected with the corresponding request source of each arbitration circuit, and adjusts the highest priority control signal based on the request of the request source.
2. The polling arbiter of claim 1, wherein each of the arbitration circuits comprises a first OR gate, a NOT gate, a first AND gate, and a second AND gate;
the first input end of the first OR gate is connected with one output end of the priority control circuit, the second input end of the first OR gate is connected with the previous arbitration circuit, and the output end of the first OR gate is respectively connected with the first input ends of the first AND gate and the second AND gate;
the second input end of the first AND gate is connected with a corresponding request source, and the output end of the first AND gate is connected with one input end of the output circuit;
and the second input end of the second AND gate is connected with the output end of the NOT gate, the input end of the NOT gate is connected with the corresponding request source, and the output end of the second AND gate is connected with the next arbitration circuit.
3. The polling arbiter of claim 2 wherein each of the arbitration circuits is further coupled to the target device;
each of the arbitration circuits transmits a request issued by the connected request source to the output circuit based on the target device being in a ready state.
4. The polling arbiter of claim 3, wherein each of the arbitration circuits further comprises a third AND gate; and the first input end of the third AND gate is connected with the output end of the first AND gate, the second input end of the third AND gate is connected with the target equipment, and the output end of the third AND gate is connected with the corresponding request source.
5. The polling arbiter of claim 3, wherein the priority control circuit is further coupled to the target device;
the priority control circuit issues the highest priority control signal based on the target device being in a ready state.
6. The polling arbiter of any one of claims 1-5 wherein the priority control circuit determines the requesting one of the arbitration circuits having the highest priority for the current clock cycle;
determining the priority order of each arbitration circuit in the next clock cycle based on the determined priority order of the arbitration circuit with the highest priority and the preset arbitration circuit;
adjusting the highest priority control signal based on the determined priority order of each of the arbitration circuits for the next clock cycle.
7. The polling arbiter of claim 6 wherein the priority control circuit maintains the highest priority control signal constant based on each of the request sources having no request.
8. The polling arbiter of any one of claims 1-5 wherein the output circuit comprises a second OR gate having an input connected to each of the arbitration circuits and an output connected to the target device.
9. A polling arbitration method applied to the polling arbiter of any one of claims 1 to 8, the method comprising:
determining one of said arbitration circuits currently having a highest priority in response to a highest priority control signal issued by said priority control circuit;
transmitting a request sent by the connected request source to the output circuit, and sending the request to the target equipment through the output circuit, or sending an enabling control signal to the next arbitration circuit based on no request of the connected request source;
and in response to the enabling control signal issued by the former arbitration circuit based on no request of the connected request source, the latter arbitration circuit is taken as the arbitration circuit with the highest priority currently.
10. A chip comprising the polling arbiter of any one of claims 1-8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210844780.2A CN114925004B (en) | 2022-07-19 | 2022-07-19 | Polling arbitrator and its polling arbitrating method and chip |
| PCT/CN2023/076171 WO2024016646A1 (en) | 2022-07-19 | 2023-02-15 | Polling arbiter and polling arbitration method therefor, and chip |
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| CN202210844780.2A CN114925004B (en) | 2022-07-19 | 2022-07-19 | Polling arbitrator and its polling arbitrating method and chip |
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| CN114925004B (en) * | 2022-07-19 | 2022-10-21 | 中科声龙科技发展（北京）有限公司 | Polling arbitrator and its polling arbitrating method and chip |
| CN115905088B (en) * | 2022-12-27 | 2023-07-14 | 声龙(新加坡)私人有限公司 | Data collection structure, method, chip and system |
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| JP2019113917A (en) * | 2017-12-21 | 2019-07-11 | ルネサスエレクトロニクス株式会社 | Data processing device, and control method of data processing device |
| FR3091766A1 (en) * | 2019-01-16 | 2020-07-17 | Stmicroelectronics Sa | Arbitration system |
| US10838892B1 (en) * | 2019-07-29 | 2020-11-17 | Xilinx, Inc. | Multistage round robin arbitration |
| CN114925004B (en) * | 2022-07-19 | 2022-10-21 | 中科声龙科技发展（北京）有限公司 | Polling arbitrator and its polling arbitrating method and chip |
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- 2022-07-19 CN CN202210844780.2A patent/CN114925004B/en active Active
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| CN1643481A (en) * | 2002-03-08 | 2005-07-20 | 飞思卡尔半导体公司 | Low power system and method for a data processing system |
| CN101038573A (en) * | 2006-03-17 | 2007-09-19 | 上海奇码数字信息有限公司 | Bus arbitration method |
| CN101038574A (en) * | 2006-03-17 | 2007-09-19 | 上海奇码数字信息有限公司 | Bus arbitration device |
| CN101887382A (en) * | 2010-06-28 | 2010-11-17 | 中兴通讯股份有限公司 | Method and device for arbitrating dynamic priority |
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| WO2024016646A1 (en) | 2024-01-25 |
| CN114925004A (en) | 2022-08-19 |
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