CN101030183A - Direct memory access controller and method for realizing memory batch processing - Google Patents
Direct memory access controller and method for realizing memory batch processing Download PDFInfo
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Abstract
A method for realizing internal memory batch-process by direct internal memory access controller includes launching up internal memory batch-process and providing entrance address of the first chain list by central processor, finding out the first chain list by said controller as per entrance address, carrying out DMA transmission on data corresponding to said chain list by said controller according to transmission parameter in current chain list, judging whether transmission of all data requiring to be batch-processed is finished or not by said controller and ending operation if it is or otherwise seeking next chain list to repeat finding out step.
Description
Technical field
The present invention relates to direct memory access controller (dma controller), relate in particular to the method for a kind of direct memory access controller and the batch processing of realization internal memory thereof.
Background technology
In the system that contains central processing unit (CPU), in order to improve internal memory and CPU service efficiency, when a large amount of internal storage datas were clocklike operated, (Direct MemoryAccess Control, mode DMA) was operated data to adopt direct memory access usually.And the operation of DMA is that (DMA Controller DMAC) realizes by dma controller.
After software loading operating system, real physical address is replaced by the physical vlan address in the internal memory.When physical vlan address consecutive hours, the actual physical address may not be continuous.In the prior art, dma controller can only transmit actual physical address and discontinuous data in the internal memory if desired at the work of actual physical address, just must initiate repeatedly the DMA transmission by CPU; Dma controller can only transmit one section data that the actual physical address is continuous at every turn, will transmit one piece of data down again by the control of CPU then; Can't realize the internal memory batch facility.
Summary of the invention
At above-mentioned deficiency, the invention provides a kind of direct memory access controller and realize the method for internal memory batch processing, discontinuous data can be transmitted by dma controller fully.
The technical solution used in the present invention is:
A kind of direct memory access dma controller is characterized in that, comprises main control module, chain module of meter control, bus control module and registers group;
Described registers group is used to deposit the entry address of chained list, and the transmission parameter in the internal memory batch process;
Described main control module is used for sending addressing instruction to the chain module of meter control after the reception central processing unit begins the instruction of internal memory batch processing; The addressing that receives the chain module of meter control sends the beginning transfer instruction to bus control module after finishing signal; Issuing bus control module after the data transmission of current chained list correspondence is intact stops transfer instruction and issues chained list control module addressing instruction; Signal is finished in the transmission that receives the chain module of meter control, finishes this internal memory batch operation;
Described chain module of meter control is used to receive the addressing instruction of described main control module, in internal memory, find corresponding chained list according to the entry address of preserving in the described registers group, after reading in the entry address of transmission parameter in this chained list and next chained list and upgrading described registers group, issue the main control module address and finish signal with it; When the entry address in the registers group is full stop, issues the transmission of main control module and finish signal;
Described bus control module receives the beginning transfer instruction of described main control module, carries out the DMA transmission according to the transmission parameter of preserving in the described registers group; And the transfer instruction that stops that receiving described main control module stops the DMA transmission.
Further, described registers group comprises source address register, destination address register, transmission length register and entry address register;
Described source address register is used to deposit the source address of this transmission internal storage data;
Described destination address register is used to deposit the destination address of this transmission internal storage data;
Described transmission length register is used to deposit the length value of the data of this transmission;
Described entry address register is used to deposit the entry address of transmission chained list; The entry address of first chained list is provided by central processing unit;
Described chain module of meter control reads in after the control information transmission data in the chained list the corresponding renewal source address register in entry address, destination address register, transmission length register and the entry address register with source address, destination address, transmission length and the next chained list of this transmission in these data.
Further, described direct memory access controller also comprises a counter, is used for when carrying out the DMA transmission current data quantity transmitted being counted;
The counting of the described counter of described main control module monitors when it reaches the value of described transmission length register, thinks that the internal storage data with current chained list correspondence has transmitted.
Further, finish this internal memory batch operation after the instruction of the termination internal memory batch processing of described main control module reception central processing unit transmission.
Further, described direct memory access controller also comprises the transport-type register, starts transmission register and stops transmission register; Described main control module receives the instruction of beginning internal memory batch processing according to the value of described startup transmission register and transport-type register; Value according to described termination transmission register receives the instruction that stops the internal memory batch processing.
The present invention also provides a kind of direct memory access controller to realize the method for internal memory batch processing, it is characterized in that, comprising:
(a) central processing unit is initiated the internal memory batch operation, and the entry address of first chained list is provided; The direct memory access controller finds first chained list according to this entry address;
(b) the direct memory access controller carries out the DMA transmission according to the transmission parameter in the current chained list to the pairing data of this chained list, has transmitted the back and has carried out (c);
(c) the direct memory access controller judges whether to need the data of internal memory batch processing all to transmit, is then to finish this internal memory batch operation; Otherwise find next chained list and return (b) according to the entry address of next chained list in the current chained list.
Further, in the step (b), the direct memory access controller reads in the control information transmission data in the current chained list, and with the corresponding renewal source address register in entry address, destination address register, transmission length register and the entry address register of source address, destination address, transmission length and the next chained list of this transmission in these data; Dma controller carries out the DMA transmission according to the numerical value of depositing in described source address register, destination address register and the transmission length register to the pairing internal storage data of current chained list.
Further, the method for the entry address of first chained list is provided is that it is left in the register of entry address to central processing unit; The direct memory access controller finds corresponding chained list according to the entry address in the register of described entry address; When the value in the register of described entry address is full stop, the direct memory access controller is thought will need the data of internal memory batch processing all to transmit, finish this internal memory batch operation.
Further, in the step (b), when carrying out the DMA transmission, current data quantity transmitted is counted with counter, the direct memory access controller monitors the counting of counter, when it thinks that current chained list is corresponding data transmission finishes when numerical value in the described transmission length register equates.
Further, in the internal memory batch process, described direct memory access controller stops this internal memory batch operation according to the command for stopping of CPU at any time.
After having adopted the solution of the present invention, can make dma controller resolve internal storage data fully without the control of CPU voluntarily and initiate and transmit.And no longer be confined at the work of actual physical address, therefore, the solution of the present invention can realize with dma controller the transmission of a large amount of discrete dates in the internal memory promptly realizing the internal memory batch operation.
Description of drawings
Fig. 1 is the synoptic diagram of list structure and chained list content implication in the internal memory;
Fig. 2 is the structural representation of dma controller of the present invention;
Fig. 3 is the process flow diagram that dma controller of the present invention is realized the internal memory batch processing.
Embodiment
Below in conjunction with drawings and Examples technical scheme of the present invention is described in detail.
At first introduce the structure and the effect of chained list in the internal memory, when needs transmission data, CPU can set up the chained list that several are used to deposit this control information transmission in internal memory, as shown in Figure 1, here the internal memory of saying not only comprises traditional intrasystem storer, also comprise nonvolatile memories such as ROM/FLASH---be nonvolatile memory, the continuous data to be transmitted in every section actual physical address is all corresponding with a chained list in the internal memory, and each chained list is all being stored the control information transmission data of pairing that section internal storage data.
As shown in Figure 1, store 4 sections each control information transmission data of 32 in each chained list, the i.e. data of 4 words, first to the 3rd word is followed successively by this transmission internal storage data source address, this transmission internal storage data destination address and this transmission length, and these triliteral data are collectively referred to as transmission parameter; The 4th word is the entry address of next transmission chained list.Next chain table entry address is a full stop---such as 0 o'clock, represent that whole transmission course finishes.In internal memory, what described source address and transmission length defined is one section storage space that the actual physical address is continuous in this internal memory, or one section storage space that the actual physical address is continuous in other internal memory, has wherein deposited data waiting for transmission; And described destination address and transmission length have defined the continuous storage space in another section actual physical address in the internal memory, and this space is the transmission destination space of data to be transmitted, promptly prepare to deposit the storage space that will transmit the data of coming.Chained list order one by one links to each other, thereby a section and discontinuous storage space logically have been connected in together.
A kind of dma controller as shown in Figure 2, comprises chain module of meter control, bus control module, main control module, FIFO (first-in first-out register), passage, counter and registers group;
Described registers group comprises source address register, destination address register, transmission length register, entry address register, transport-type register, the startup transmission register of each passage and stops transmission register;
Described source address register is used to deposit the source address of this transmission internal storage data;
Described destination address register is used to deposit the destination address of this transmission internal storage data;
Described transmission length register is used to deposit the length value of the data of this transmission;
The entry address that described entry address register is used to deposit next transmission chained list; Wherein the address of first chained list is provided when initiating the internal memory batch processing by CPU.
Described transport-type register is used to deposit the numerical value of expression transport-type, such as 1 corresponding internal memory batch processing, and 2 corresponding common DMA transmission etc.;
Described startup transmission register is used to deposit expression and starts or do not start numerical value when prepass, starts passage such as 1 indication, and other numerical value indication does not start;
Described termination transmission register is used to deposit the numerical value that expression stopped or do not stop working as prepass, stops passage such as 1 indication, and other numerical value indication does not stop;
More than three registers by CPU (central processing unit) configuration, initiate or stop dma controller to carry out the internal memory batch operation.
Described main control module receives the instruction that CPU begins the internal memory batch processing according to the value that starts transmission register and transport-type register, such as when CPU will carry out the internal memory batch processing, can configuration start transmission register and transport-type register, just change their value, detect the value change of startup transmission register when the main control module after, learn and to transmit, be worth knowing that according to the transport-type register what will carry out is the internal memory batch operation then; After receiving sign on, the main control module is issued chain module of meter control addressing instruction; The addressing of reception chain module of meter control is finished signal and is issued bus control module and begins transfer instruction, indicates the passage that transmits in this instruction;
Described main control module also receives CPU according to the value that stops transmission register and stops the instruction of internal memory batch processing and finish this internal memory batch processing, if transmit this moment, then issues bus control module and stops transfer instruction; Monitor the counting of counter, when it reaches the value of transmission length register, think that the data transmission of current chained list correspondence is intact, issue bus control module and stop transfer instruction and issue chained list control module addressing instruction; Signal is finished in the transmission that receives the chain module of meter control, finishes this internal memory batch operation, sends interruption to CPU, returns bus control right.
Described counter is used in the process of the pairing data of each chained list being carried out the DMA transmission current transmission channel DMA data quantity transmitted being counted.
Described chain module of meter control receives the addressing instruction of described main control module, write on value in the register of entry address according to CPU, be that corresponding chained list is found in the entry address in internal memory, after reading in the control information transmission data in the current chained list and upgrading source address register, destination address register, transmission length register and the entry address register of current transmission channel successively, issue the main control module address and finish signal with first to the 4th word of these data; And when the value in the register of entry address is full stop, issues the transmission of main control module and finish signal.
Described bus control module receives the beginning transfer instruction of described main control module, source address register according to respective channel, the value of destination address register, by described passage the pairing data of chained list are carried out the DMA transmission, its process is to find the source address of data to be transmitted earlier according to the value in the described source address register, find the destination address of transmission again according to the value in the described destination address register, then will be from the data the storage space that source address begins, read in successively among the FIFO earlier, correspondingly put into successively again in the storage space that begins from destination address; And the transfer instruction that stops that receiving described main control module stops the DMA transmission.
A kind of described dma controller is realized the method for internal memory batch processing, as shown in Figure 3, may further comprise the steps:
(a1) CPU initiates the internal memory batch operation, concrete steps be the entry address of the first chained list of the CPU data that will carry out the internal memory batch processing earlier leave in a passage of dma controller the entry address register in, dispose the transport-type register of this passage then, what indicate that this passage will carry out is the internal memory batch operation, when then transmitting as the common DMA of initiation, the startup transmission register that disposes this passage starts dma controller work;
(a2) dma controller detects and learns and will transmit after the value that starts transmission register changes, and be worth knowing that according to the transport-type register of described passage what will carry out is the internal memory batch processing, so ignore the value of source address register, destination address register, transmission length register dma controller, directly in internal memory, find first chained list in this transmission according to the entry address in the register of entry address;
The control information transmission data of middle storage that (b1) dma controller reads in current chained list by word---chained list that promptly finds---, and upgrade current transmission channel successively with first to the 4th word that reads in data source address register, destination address register, transmission length register and the entry address register of---being the passage that the CPU indication starts the internal memory batch operation---; Described " renewal " promptly replaces original value in the register with reading in data;
(b2) dma controller is according to the transmission parameter in the control information transmission data in the described register---and be that source address, destination address and transmission length are carried out the DMA transmission to the pairing data of current chained list; The concrete steps of carrying out the DMA transmission repeat no more with above writing.
In transmission, be that 0 counter is counted current transmission channel data quantity transmitted with initial value; In the transmission course, whether dma controller monitors always that one piece of data with current chained list correspondence has transmitted, and promptly data quantity transmitted---just whether the counting of counter has reached the numerical value in the described transmission length register; When reaching, finish the DMA transmission of pairing that section internal storage data of current chained list, the counting of counter is reverted to 0 and carry out (c);
(c) it is intact that dma controller will need to judge whether the data transmission of internal memory batch processing, determination methods is to see whether the data in the register of entry address are end mark, be that the data that all chained list correspondences in this internal memory batch operation then are described have all been transmitted, at this moment finish this internal memory batch operation, initiate to interrupt to CPU, return the bus right to occupation; Otherwise in internal memory, find next chained list according to the address in the register of entry address, and return (b1), promptly carry out the DMA transmission of next section internal storage data; Described end mark is represented with 0 usually.
In the process of whole internal memory batch processing, CPU can indicate when the termination transmission register of prepass by configuration at any time and stop the internal memory batch operation, is equivalent to initiate accidental interruption one time.Dma controller monitors the state of described termination transmission register all the time in the internal memory batch process, be final state in case find it, just stops this internal memory batch operation.
In actual applications, so long as the transmission of this discrete date clocklike, such as the TV data, the dma controller that can use the present invention to propose.In addition, the optional position that chained list described in the present invention can be in internal memory, the source address of transmission and destination address also can be the optional positions in the internal memory.
Above-mentioned is optimum embodiment of the present invention; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding distortion according to the present invention, but these corresponding distortion all should belong in the scope that claims of the present invention protect.
Claims (10)
1, a kind of direct memory access dma controller is characterized in that, comprises main control module, chain module of meter control, bus control module and registers group;
Described registers group is used to deposit the entry address of chained list, and the transmission parameter in the internal memory batch process;
Described main control module is used for sending addressing instruction to the chain module of meter control after the reception central processing unit begins the instruction of internal memory batch processing; The addressing that receives the chain module of meter control sends the beginning transfer instruction to bus control module after finishing signal; Issuing bus control module after the data transmission of current chained list correspondence is intact stops transfer instruction and issues chained list control module addressing instruction; Signal is finished in the transmission that receives the chain module of meter control, finishes this internal memory batch operation;
Described chain module of meter control is used to receive the addressing instruction of described main control module, in internal memory, find corresponding chained list according to the entry address of preserving in the described registers group, after reading in the entry address of transmission parameter in this chained list and next chained list and upgrading described registers group, issue the main control module address and finish signal with it; When the entry address in the registers group is full stop, issues the transmission of main control module and finish signal;
Described bus control module receives the beginning transfer instruction of described main control module, carries out the DMA transmission according to the transmission parameter of preserving in the described registers group; And the transfer instruction that stops that receiving described main control module stops the DMA transmission.
2, direct memory access controller as claimed in claim 1 is characterized in that, described registers group comprises source address register, destination address register, transmission length register and entry address register;
Described source address register is used to deposit the source address of this transmission internal storage data;
Described destination address register is used to deposit the destination address of this transmission internal storage data;
Described transmission length register is used to deposit the length value of the data of this transmission;
Described entry address register is used to deposit the entry address of transmission chained list; The entry address of first chained list is provided by central processing unit;
Described chain module of meter control reads in after the control information transmission data in the chained list the corresponding renewal source address register in entry address, destination address register, transmission length register and the entry address register with source address, destination address, transmission length and the next chained list of this transmission in these data.
3, direct memory access controller as claimed in claim 2 is characterized in that, also comprises a counter, is used for when carrying out the DMA transmission current data quantity transmitted being counted;
The counting of the described counter of described main control module monitors when it reaches the value of described transmission length register, thinks that the internal storage data with current chained list correspondence has transmitted.
4, direct memory access controller as claimed in claim 1 is characterized in that, finishes this internal memory batch operation after the instruction of the termination internal memory batch processing that described main control module reception central processing unit sends.
5, direct memory access controller as claimed in claim 1 is characterized in that, also comprises the transport-type register, starts transmission register and stops transmission register; Described main control module receives the instruction of beginning internal memory batch processing according to the value of described startup transmission register and transport-type register; Value according to described termination transmission register receives the instruction that stops the internal memory batch processing.
6, a kind of direct memory access controller is realized the method for internal memory batch processing, comprising:
(a) central processing unit is initiated the internal memory batch operation, and the entry address of first chained list is provided; The direct memory access controller finds first chained list according to this entry address;
(b) the direct memory access controller carries out the DMA transmission according to the transmission parameter in the current chained list to the pairing data of this chained list, has transmitted the back and has carried out (c);
(c) the direct memory access controller judges whether to need the data of internal memory batch processing all to transmit, is then to finish this internal memory batch operation; Otherwise find next chained list and return (b) according to the entry address of next chained list in the current chained list.
7, method as claimed in claim 6, it is characterized in that: in the step (b), the direct memory access controller reads in the control information transmission data in the current chained list, and with the corresponding renewal source address register in entry address, destination address register, transmission length register and the entry address register of source address, destination address, transmission length and the next chained list of this transmission in these data; Dma controller carries out the DMA transmission according to the numerical value of depositing in described source address register, destination address register and the transmission length register to the pairing internal storage data of current chained list.
8, method as claimed in claim 7 is characterized in that: it is that it is left in the register of entry address that central processing unit provides the method for the entry address of first chained list; The direct memory access controller finds corresponding chained list according to the entry address in the register of described entry address; When the value in the register of described entry address is full stop, the direct memory access controller is thought will need the data of internal memory batch processing all to transmit, finish this internal memory batch operation.
9, method as claimed in claim 7, it is characterized in that, in the step (b), when carrying out the DMA transmission, with counter current data quantity transmitted is counted, the direct memory access controller monitors the counting of counter, when it thinks that current chained list is corresponding data transmission finishes when numerical value in the described transmission length register equates.
10, method as claimed in claim 7 is characterized in that, in the internal memory batch process, described direct memory access controller stops this internal memory batch operation according to the command for stopping of CPU at any time.
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| CNB2007100651089A CN100561453C (en) | 2007-04-03 | 2007-04-03 | A kind of direct memory access controller |
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| CNB2007100651089A CN100561453C (en) | 2007-04-03 | 2007-04-03 | A kind of direct memory access controller |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100547572C (en) * | 2007-10-22 | 2009-10-07 | 威盛电子股份有限公司 | Dynamically set up the method and system of direct memory access path |
| CN101625666B (en) * | 2009-08-26 | 2011-08-17 | 福建星网锐捷网络有限公司 | Method and system for copying data and writing in parameter information |
| CN102314400A (en) * | 2011-09-27 | 2012-01-11 | 广东威创视讯科技股份有限公司 | Method and device for dispersing converged DMA (Direct Memory Access) |
| CN103870404A (en) * | 2014-03-13 | 2014-06-18 | 武汉精测电子技术股份有限公司 | IIC (Inter-Integrated Circuit) batch command processing control method |
| CN105468550A (en) * | 2015-11-19 | 2016-04-06 | 深圳国微技术有限公司 | System and method capable of achieving linked list cycle |
| CN107678987A (en) * | 2017-10-10 | 2018-02-09 | 郑州云海信息技术有限公司 | The method, apparatus and equipment of a kind of DMA transfer |
| WO2018041074A1 (en) * | 2016-08-31 | 2018-03-08 | 华为技术有限公司 | Method, apparatus, and system for accessing memory device |
| CN108228497A (en) * | 2018-01-11 | 2018-06-29 | 湖南国科微电子股份有限公司 | A kind of DMA transfer method based on sgl chained lists |
| CN114328316A (en) * | 2021-11-22 | 2022-04-12 | 北京智芯微电子科技有限公司 | DMA controller, SOC system and data carrying method based on DMA controller |
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| CN100547572C (en) * | 2007-10-22 | 2009-10-07 | 威盛电子股份有限公司 | Dynamically set up the method and system of direct memory access path |
| CN101625666B (en) * | 2009-08-26 | 2011-08-17 | 福建星网锐捷网络有限公司 | Method and system for copying data and writing in parameter information |
| CN102314400A (en) * | 2011-09-27 | 2012-01-11 | 广东威创视讯科技股份有限公司 | Method and device for dispersing converged DMA (Direct Memory Access) |
| CN102314400B (en) * | 2011-09-27 | 2014-12-24 | 广东威创视讯科技股份有限公司 | Method and device for dispersing converged DMA (Direct Memory Access) |
| CN103870404A (en) * | 2014-03-13 | 2014-06-18 | 武汉精测电子技术股份有限公司 | IIC (Inter-Integrated Circuit) batch command processing control method |
| CN103870404B (en) * | 2014-03-13 | 2016-09-14 | 武汉精测电子技术股份有限公司 | A kind of IIC criticizes command process control method |
| CN105468550A (en) * | 2015-11-19 | 2016-04-06 | 深圳国微技术有限公司 | System and method capable of achieving linked list cycle |
| CN105468550B (en) * | 2015-11-19 | 2018-10-19 | 深圳国微技术有限公司 | A kind of system and method for achievable chained list cycle |
| WO2018041074A1 (en) * | 2016-08-31 | 2018-03-08 | 华为技术有限公司 | Method, apparatus, and system for accessing memory device |
| CN107678987A (en) * | 2017-10-10 | 2018-02-09 | 郑州云海信息技术有限公司 | The method, apparatus and equipment of a kind of DMA transfer |
| CN107678987B (en) * | 2017-10-10 | 2021-06-29 | 郑州云海信息技术有限公司 | DMA transmission method, device and equipment |
| CN108228497A (en) * | 2018-01-11 | 2018-06-29 | 湖南国科微电子股份有限公司 | A kind of DMA transfer method based on sgl chained lists |
| CN114328316A (en) * | 2021-11-22 | 2022-04-12 | 北京智芯微电子科技有限公司 | DMA controller, SOC system and data carrying method based on DMA controller |
| CN114328316B (en) * | 2021-11-22 | 2024-01-26 | 北京智芯微电子科技有限公司 | DMA controller, SOC system and data carrying method based on DMA controller |
| CN114338567A (en) * | 2021-12-27 | 2022-04-12 | 锐迪科创微电子（北京）有限公司 | SDIO interface data transmission method and device and SDIO interface equipment |
| CN114338567B (en) * | 2021-12-27 | 2023-09-05 | 锐迪科创微电子（北京）有限公司 | SDIO interface data transmission method and device and SDIO interface equipment |
| CN116775524A (en) * | 2023-06-19 | 2023-09-19 | 无锡摩芯半导体有限公司 | Lli dynamic writing method of dma linked list mode |
| CN116775524B (en) * | 2023-06-19 | 2024-02-02 | 无锡摩芯半导体有限公司 | Lli dynamic writing method of dma linked list mode |
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