CN1908925A - Method for improving PCI communication credibility and efficiency - Google Patents
Method for improving PCI communication credibility and efficiency Download PDFInfo
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- CN1908925A CN1908925A CN 200610019993 CN200610019993A CN1908925A CN 1908925 A CN1908925 A CN 1908925A CN 200610019993 CN200610019993 CN 200610019993 CN 200610019993 A CN200610019993 A CN 200610019993A CN 1908925 A CN1908925 A CN 1908925A
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Abstract
The related method to improve reliability and efficiency for PCI communication comprises: arranging processor and memory on every board, assigning two or three independent areas with same structure on memory as DMA data buffer; alternative operating the two or three areas every with a state flag bit. This invention can prevent data error operation, and improves reliability and efficiency for communication.
Description
Technical field
The invention belongs to communication technical field, relate to the high reliability and the high efficiency method that guarantee communication between the integrated circuit board that adopts the connection of pci bus standard in the communication system.
Background technology
In the PCI communication, extensively exist in fields such as telecommunication systems at present in the many integrated circuit boards communication system that adopts the pci bus standard to connect, integrated circuit board can be seen compact computer as, integrated circuit board each has processor CPU, internal memory etc., carry out high speed, general direct memory visit DMA (the Direct Memeory Access) technology that adopts of mass data transmission between integrated circuit board, data can reach the maximum data transfer rate of pci bus standard under dma mode, its transmission course is finished by dma controller, needs the intervention of system kernel hardly.The DMA communication mechanism is as follows: mark off corresponding region of memory as the data transmit-receive buffer zone on the two boards card of needs communication, the data block of filling in a certain size starts the transmission that dma controller comes log-on data then to sending buffer zone.By the correlation behavior position of dma controller is set, produces and interrupt after data are sent completely, notice receives data terminal and begins the reception of data.Receiving end begins Data Receiving and processing after receiving the notice of transmitting terminal, the send buffer state flag bit is set for idle after finishing.
In the general design, a data transmitting-receiving buffer zone is set on the every integrated circuit board, at dma operation is not that data volume very frequent, that handle is not when being very big, the time interval between two dma operations can guarantee finishing of a dma operation flow process, therefore can not occur because of waiting as long for the situation that available internal memory zone (promptly receiving and dispatching buffer zone) causes next dma operation to be failed; When data volume between integrated circuit board is big especially, this rough sledding: DMA may occur and handle data in the buffer zone, and have this moment data to arrive, need write buffer zone, data are untreated and start the DMA data transmission again before finishing in the transmitting-receiving buffer zone like this, the reentry (covering) of data will occur, cause error of transmission; Perhaps because of data processing in the transmitting-receiving buffer zone do not finish cause DMA not have the transmitting-receiving buffer zone can be with postponing, the DMA bust this will occur and lose the data that will transmit.
Summary of the invention
The method that the purpose of this invention is to provide a kind of PCI of raising communication reliability and efficient is used for the PCI communication between the two boards card, avoids in the dma operation data to reentry or loses wrong generation, guarantees reliability of data transmission, improves communication efficiency simultaneously.
Technical scheme of the present invention is: the method for a kind of PCI of raising communication reliability and efficient, it is characterized in that: processor and internal memory are arranged respectively on the every integrated circuit board, on internal memory, distribute 2 or 3 independently, the identical region of memory of structure is as DMA data transmit-receive buffer zone, these 2 or 3 internal memories are taken turns flow operation, each region of memory is provided with a state flag bit, before region of memory being operated, detect the state of region of memory at every turn, determine whether this region of memory can carry out next operation, thereby effectively prevent data reentry maloperation.
In the general design, a data transmitting-receiving buffer zone is set on the every integrated circuit board, at dma operation is not that data volume very frequent, that handle is not when being very big, the time interval between two dma operations can guarantee finishing of a dma operation flow process, therefore can not occur because of waiting as long for the situation that available internal memory zone (promptly receiving and dispatching buffer zone) causes next dma operation to be failed; When dma operation data volume relatively more frequent, that handle was very big, when next dma operation arrived, a last dma operation also took the transmitting-receiving buffer zone, next dma operation failure at this moment will occur, thereby caused the failure of PCI communication.
The present invention adopts the mode of two region of memorys wheel flow operations to solve the problems referred to above, and is frequent at dma operation, when data volume is very big: dma operation takies transmitting-receiving buffer zone Memory I for the first time; Needn't wait for finishing of dma operation for the first time when dma operation arrives for the second time, and take transmitting-receiving buffer zone Memory II; When dma operation arrival for the third time, for the first time dma operation finish (for the first time DMA and for the third time between the DMA at interval dma operation for the second time, the time interval is enough finished dma operation for the first time), transmitting-receiving buffer zone Memory I has been in idle condition, can be taken by dma operation for the third time ... cycling like this, guaranteed that each dma operation all has idle transmitting-receiving buffer zone to call, just can solve because dma operation is frequent, the problem of the dma operation failure that data volume is brought greatly, also can improve simultaneously the utilization factor of DMA passage greatly, thereby improve the efficient of PCI communication.
Major technique of the present invention is for having adopted region of memory wheel flow operation, prevented that the problem that data are reentried from (having two region of memorys to select, each region of memory carries out state description by its zone bit and operation is selected), effectively solve the mistake that communication data that the dma operation failure causes is lost, improved the efficient that the utilization factor of DMA passage is communicated by letter with PCI simultaneously.This method is simple, suitable, and is also not high to the internal memory capacity requirement, is reliable, high-efficiency method in the dma mode communication.
Description of drawings
Fig. 1 is the dma operation flow process that prior art adopts the two boards card to distribute a buffer zone respectively.
Fig. 2 is embodiments of the invention: described the dma operation flow process that adopts the two boards card to distribute two buffer zones respectively.
Fig. 3 is embodiments of the invention: described in the actual DMA exchange two region of memorys and distributed and use synoptic diagram.
Fig. 4 is that synoptic diagram is implemented in practical application of the present invention.
Concrete embodiment
Enforcement of the present invention: utilize this algorithm, use language programming,, realize the high capacity reliable communication of PCI in conjunction with integrated circuit board hardware.
Further specify technical scheme of the present invention by the following examples.
Referring to Fig. 1, Fig. 1 is the dma operation flow process that prior art adopts the two boards card to distribute a buffer zone respectively.Theing contents are as follows in this flow process:
Can step 10 detects the state that No. 1 integrated circuit board sends buffer zone, confirm currently carry out dma operation;
Step 11 sends buffer zone and is in busy condition, and dma operation enters time-delay and waits for, constantly detects and sends buffer state;
Step 12, the time-delay stand-by period of setting arrives, and it is unavailable to send buffer zone, and alarm is sent in the dma operation failure;
Step 13, sending buffer zone can use, and its state is set for busy, writes the data that will send toward sending buffer zone then;
Can step 14 detects the state of No. 2 integrated circuit board send buffers, confirm currently carry out dma operation;
Step 15, send buffer is in busy condition, and dma operation enters time-delay and waits for, constantly detects the send buffer state;
Step 16, the time-delay stand-by period of setting arrives, and send buffer is unavailable, and alarm is sent in the dma operation failure;
Step 17 starts the DMA passage, the beginning data transmission;
Step 18 is provided with the corresponding control bit of dma controller, produces No. 2 integrated circuit boards of interrupt notification and begins Data Receiving;
Step 19, No. 2 integrated circuit boards receive data and finish, and it is idle condition that its send buffer is set;
Step 110, data transmission is finished, and it is idle condition that No. 1 integrated circuit board transmission buffer zone is set;
Step 111, dma operation is finished, and withdraws from the PCI communication process.
The performance of the defective of prior art in Fig. 1 flow process is: when transmitted data amount between integrated circuit board is big especially, following situation: DMA can occur and handle data in the buffer zone, and have this moment data to arrive, need write buffer zone, the reentry (covering) of data can occur, cause error of transmission; Perhaps do not finish and cause the DMA no-buffer to use, the DMA bust this will occur and lose the data that to transmit because of data processing in the buffer zone.Usually solution is to increase integrated circuit board to increase the processing capacity, handles identical data such as employing 2 cover systems, but has strengthened cost so undoubtedly.
Referring to Fig. 2, Fig. 2 has described the present invention and has adopted the two boards card to distribute the dma operation flow process of two buffer zones respectively.Theing contents are as follows in this flow process:
Fa Ming advantage shows in the present embodiment: central idea is to work by turns, prolong the interval that each sheet internal memory is operated the time, coordinate the time that dma controller deal with data and buffering are used, guaranteeing has idle internal memory as DMA data transmit-receive buffer zone when communication is initiated each time, avoid data to be capped and abandon.
Referring to Fig. 3, Fig. 3 has described in the actual DMA exchange two Memory Allocation and operation chart in turn: in the communication process, use for the first time internal memory I, use for the second time internal memory II, use internal memory I for the third time, take turns successively, prolong each operated time interval of sheet internal memory, guaranteeing has idle internal memory as DMA data transmit-receive buffer zone when communication initiation each time.Wherein: DMAn represents dma operation the n time, is dma operation, the i.e. number of run of DMA in the program run for the third time such as DMA3.
From 3 explanations of above-mentioned accompanying drawing as can be seen, in the dma operation flow process, the transmitting-receiving buffer zone is used for the buffer memory swap data, must guarantee that in the flow process incipient stage receiving and dispatching buffer zone is in idle condition; The buffer state zone bit is set for busy, inserts the data that will send to available buffer zone; Start the DMA passage, begin to send data; After data are sent completely, the buffer flag position is set, withdraws from communication process for idle.In whole flow process, the transmitting-receiving buffer zone is finished from being set to busy condition to time dma operation, in the d/d process of buffer zone, be in busy state always, the hold time size of execution time of depending primarily on dma controller itself and each DMA transmitted data amount of this state, therefore for the dma operation of big data quantity, it is held time and will grow.
It can also be seen that in Fig. 2 under the not idle situation of buffer zone, new dma operation can postpone to wait for a period of time, and constantly detects buffer state, up to buffer zone can with and enter the DMA treatment scheme, reduced the possibility that data are dropped.The present invention has also fully taken into account the disposition of loss of data under the extreme case, carries out corresponding fault-tolerant processing when data peaks surpasses system processing power, and the assurance system can not collapse, and only can lose the partial data that exceeds capacity.
By Fig. 1 and Fig. 2, Fig. 3 more as can be seen, great advantage of the present invention is to guarantee that dma operation has idle buffer zone to utilize in most cases, avoided because the unavailable data-bag lost that causes of buffer zone, improved simultaneously the utilization factor of DMA passage greatly, communication efficiency is improved greatly.
Referring to Fig. 4, be that synoptic diagram is implemented in practical application of the present invention.
In actual the use, we adopt two integrated circuit boards: the CPCI of motorola producer (Compact PCI) integrated circuit board 5365, and CPU is P III; The PMC of interphase producer (PMC Mezzanine Cards) integrated circuit board 4532, CPU is PowerPC8260; Integrated circuit board connects with compact way by pci bus.
RS8250 is a framer, is used to send/receive 4532 data; GE is the gigabit Ethernet mouth.Every integrated circuit board has separate CPU, and internal memory is by PCI bridge swap data.By language programming, on the two boards card, respectively distribute two internal memories, every comprises the reception buffering and sends buffering; When data arrived, program will be passed through the dma operation flow process, and data are sent to the outer integrated circuit board of order, realized PCI communication.
Though described the present invention by examples of implementation, those of ordinary skills know, the present invention has many distortion and variation and do not break away from spirit of the present invention, wish that appended claim comprises these distortion and variation and do not break away from spirit of the present invention.
Claims (1)
1, a kind of method that improves PCI communication reliability and efficient, it is characterized in that: processor and internal memory are arranged respectively on the every integrated circuit board, on internal memory, distribute 2 or 3 independently, the identical region of memory of structure is as DMA data transmit-receive buffer zone, these 2 or 3 internal memories are taken turns flow operation, each region of memory is provided with a state flag bit, before region of memory being operated, detect the state of region of memory at every turn, determine whether this region of memory can carry out next operation, thereby effectively prevent data reentry maloperation.
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| CN 200610019993 CN1908925A (en) | 2006-08-15 | 2006-08-15 | Method for improving PCI communication credibility and efficiency |
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| CN 200610019993 CN1908925A (en) | 2006-08-15 | 2006-08-15 | Method for improving PCI communication credibility and efficiency |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101908984A (en) * | 2010-06-30 | 2010-12-08 | 杭州华三通信技术有限公司 | Method and single board for detecting faults of memory |
| CN103326464A (en) * | 2013-04-02 | 2013-09-25 | 国家电网公司 | Power quality continuous wave recording data transmission and storage method |
| CN103401879A (en) * | 2013-08-14 | 2013-11-20 | 青岛海信宽带多媒体技术有限公司 | Optical module and method for guaranteeing integrity of optical module protocol data |
| CN103441992A (en) * | 2013-08-14 | 2013-12-11 | 青岛海信宽带多媒体技术有限公司 | Method for guaranteeing optical module protocol data integrity |
| CN107534830A (en) * | 2015-02-15 | 2018-01-02 | 天工方案公司 | For monitoring circuit, the apparatus and method of universal serial bus |
| CN108595351A (en) * | 2018-05-11 | 2018-09-28 | 湖南华芯通网络科技有限公司 | A kind of DMA sending control methods of network-oriented forward process |
| CN111420277A (en) * | 2020-04-09 | 2020-07-17 | 北京品驰医疗设备有限公司 | Implantable neurostimulation device |
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2006
- 2006-08-15 CN CN 200610019993 patent/CN1908925A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101908984A (en) * | 2010-06-30 | 2010-12-08 | 杭州华三通信技术有限公司 | Method and single board for detecting faults of memory |
| CN103326464A (en) * | 2013-04-02 | 2013-09-25 | 国家电网公司 | Power quality continuous wave recording data transmission and storage method |
| CN103401879A (en) * | 2013-08-14 | 2013-11-20 | 青岛海信宽带多媒体技术有限公司 | Optical module and method for guaranteeing integrity of optical module protocol data |
| CN103441992A (en) * | 2013-08-14 | 2013-12-11 | 青岛海信宽带多媒体技术有限公司 | Method for guaranteeing optical module protocol data integrity |
| CN103441992B (en) * | 2013-08-14 | 2017-02-15 | 青岛海信宽带多媒体技术有限公司 | Method for guaranteeing optical module protocol data integrity |
| CN107534830A (en) * | 2015-02-15 | 2018-01-02 | 天工方案公司 | For monitoring circuit, the apparatus and method of universal serial bus |
| US10880764B2 (en) | 2015-02-15 | 2020-12-29 | Skyworks Solutions, Inc. | Circuits, devices, and methods for monitoring a serial bus |
| CN107534830B (en) * | 2015-02-15 | 2021-06-29 | 天工方案公司 | Circuit, device and method for monitoring a serial bus |
| US11729645B2 (en) | 2015-02-15 | 2023-08-15 | Skyworks Solutions, Inc. | Devices and methods for monitoring a serial bus |
| CN108595351A (en) * | 2018-05-11 | 2018-09-28 | 湖南华芯通网络科技有限公司 | A kind of DMA sending control methods of network-oriented forward process |
| CN111420277A (en) * | 2020-04-09 | 2020-07-17 | 北京品驰医疗设备有限公司 | Implantable neurostimulation device |
| CN111420277B (en) * | 2020-04-09 | 2024-10-01 | 北京品驰医疗设备股份有限公司 | Implantable neural stimulation device |
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