CN101046786A - DMA controller and transmission method of implementing high efficient DMA transmission - Google Patents
DMA controller and transmission method of implementing high efficient DMA transmission Download PDFInfo
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Abstract
The present invention discloses a DMA controller capable of implementing high-effective direct internal storage access DMA transmission and its transmission method. It is characterized by that the described DMA controller includes a DMA control module, said DMA control module is used for controlling DMA transmission between peripheral equipment and internal memory. Besides, said invention also provides the concrete operation steps for implementing said transmission method.
Description
Technical field
The present invention relates to DMA (Direct Memory Access Control, direct memory access) transmission, be specifically related to a kind of dma controller and transmission method of realizing the high efficient DMA transmission.
Background technology
In the system that contains central processing unit (CPU), in order to improve internal memory and CPU service efficiency, when a large amount of internal storage datas were clocklike operated, (Direct MemoryAccess Control, mode DMA) was operated data to adopt direct memory access usually.And the operation of DMA is that (DMA Controller DMAC) realizes by dma controller.Dma controller has selection type and multi-path type two classes, and the dma controller that relates to herein is a selection type, promptly physically is connected with a plurality of hardware, and only allows a hardware in logic, promptly can only be a hardware service in certain period.
In the prior art, the DMA transmission initiated of peripheral hardware is normally fetched data from the buffer memory of peripheral hardware and is put in the storer on the bus; As shown in Figure 1, such as need carry out DMA when transmission as peripheral hardware, after its buffer memory was filled data, it initiated the DMA transmission requests by the DMA request trigger to dma controller.CPU is with in the address register in the control information dispensing dma controllers such as address before this, and when dma controller was received the DMA transmission requests, it was initiated bus to CPU and takies request.CPU gives dma controller with bus control right usually after executing present instruction.This moment, control, the status register of dma controller changed, and showed to obtain bus control right, began to carry out the DMA transmission.With a counter data quantity transmitted is counted in the transmission, when counting reached peripheral hardware spatial cache size, dma controller was given back bus control right to CPU, finished this DMA transmission; An i.e. DMA transmission can only be finished the DMA transmission requests of a peripheral hardware.When peripheral hardware needs to carry out the DMA transmission once more, just initiate a DMA transmission again.Though spatial cache is bigger comparatively speaking in the internal memory, still can only transmit the data volume that is equivalent to peripheral hardware spatial cache size at every turn, can not make full use of the space of buffer memory in the internal memory.Because each DMA data quantity transmitted is subjected to the restriction of peripheral hardware spatial cache size, so when transferring large number of data, often need to initiate repeatedly the DMA transmission, and each DMA transmission all must waiting for CPU be given dma controller with bus control right, so transfer efficiency is low.In addition, whenever carry out a DMA transmission, will internally deposit into once visit of row.And the efficient of internal memory is determined by accessed number of times, visits frequently more, and memory efficient is low more, and system effectiveness is directly related with memory efficient, and such working method has reduced the work efficiency of system to a certain extent.
In addition, in existing DMA transmission, if peripheral hardware only has the buffer memory of byte type such as UART (UniversalAsynchronous Receiver/Transmitter UART Universal Asynchronous Receiver Transmitter) etc., then dma controller only transmits with the least-significant byte of bus, reduced the utilization factor of bus, and the DMA transfer efficiency is also lower.Data transmission between dma controller and peripheral hardware is shown in Fig. 2,3.
Summary of the invention
At above-mentioned deficiency, the technical problem to be solved in the present invention provides a kind of dma controller of realizing the high efficient DMA transmission, can improve each DMA data quantity transmitted, improves transfer efficiency.
The dma controller of described realization high efficient DMA transmission comprises the DMA control module, is used to control the DMA transmission between peripheral hardware and internal memory; It is characterized in that: when described DMA control module reaches peripheral hardware spatial cache size when the byte number that transmits between peripheral hardware and dma controller, finish the signal of the DMA transmission requests between this peripheral hardware and dma controller to peripheral hardware; When the byte number that transmits between dma controller and internal memory reaches memory cache space size, send passage to CPU and finish the transmission interrupt request.
Further, described dma controller also comprises:
Peripheral hardware cache size register is used to deposit the numerical value of the spatial cache size of peripheral hardware;
The memory cache sized registers is used for depositing the numerical value of internal memory spatial cache size;
First counter, the byte number that is used for transmitting between the transmission of the DMA between peripheral hardware and dma controller is to peripheral hardware and dma controller is counted;
Second counter, the byte number that is used for transmitting between a DMA transmission is to dma controller and internal memory is counted;
Whether the count value that described DMA control module is passed through to judge first counter judges whether the byte number that between peripheral hardware and dma controller transmit reach the size of peripheral hardware spatial cache less than the numerical value in the peripheral hardware cache size register; Whether count value by second counter relatively judges whether the byte number that between dma controller and internal memory transmit reach the size in memory cache space less than the numerical value in the memory cache sized registers.
Further, described dma controller also comprises:
Hardware requests enabled state register is used to deposit the numerical value of representing the hardware requests enabled state, comprises the value of expression " permission hardware requests " and " not allowing hardware requests "; When needing hardware to initiate the DMA transmission, be changed to the value of expression " permission hardware requests " by CPU;
The channel status register is used to deposit the numerical value of representing channel status, comprises the value of expression " passage is occupied " and the value of expression " passage can be used ";
Described DMA control module is used to control the DMA transmission between peripheral hardware and internal memory; When the numeric representation " permission hardware requests " of described hardware requests enabled state register, receive the DMA transmission requests of hardware, when " not allowing hardware requests ", its value representation do not continue to inquire after; And the byte number that transmits between dma controller and internal memory reaches memory cache space when size, and described hardware requests enabled state register is changed to the value that expression " does not allow hardware requests ".
Described DMA control module also is used to inquire after the value of described channel status register, if continue to inquire after during its value representation " passage is occupied ", carries out DMA during expression " passage can with " and transmits; And after beginning DMA transmission, the value of the channel status register of used transmission channel is changed to " passage is occupied "; After the transmission of the DMA on this passage is finished or stopped, the value of channel status register is changed to the value of expression " passage can be used ".
Further, described dma controller also comprises a plurality of passages; The each data quantity transmitted of each passage is corresponding to the bus interface that is connected; With each data quantity transmitted is that the passage of 32 bytes is called standard channel; Each data quantity transmitted is called non-standard passage less than the passage of 32 bytes; Each passage is connected on the different hardware by different bus interface respectively;
Described DMA control module the time starts described data and pieces together the form removal piece and the data of carrying out the DMA transmission at non-standard passage are spliced in described FIFO or splits carrying out DMA transmission between non-standard passage and the standard channel, and the buffer memory type with source, purpose hardware is consistent respectively to make the data volume that each reading and writing operate; And, when the splicing that receives data assembly form removal piece finishes message, the data that splicing is good among the FIFO are sent to purpose hardware; When the fractionation that receives data assembly form removal piece finished message, reading of data was put into FIFO from the hardware of source; When receiving the sent message of data assembly form removal piece, the data block of tearing open among the FIFO is sent to purpose hardware;
Described data piece together the form removal piece when the buffer memory type of source hardware than destination address hour, will splice from the data that source hardware arrives FIFO, when the data volume that arrives FIFO achieves the goal the buffer memory size of type of hardware, issue the DMA control module splicing message that finishes; When the buffer memory type of source hardware during than purpose hardware big, described data are pieced together the form removal piece and split out the data block that meets purpose hardware cache size of type in the data that arrive FIFO, whenever tear open once to issue one of DMA control module and can send message; Reach when the data volume that sends and issue the DMA control module after the buffer memory size of type of source hardware and split the message that finishes.
Further, described dma controller also comprises:
Source address variation pattern register is used for depositing the numerical value that the source address variation pattern is transmitted in expression;
Destination address variation pattern register is used for depositing the numerical value of expression transmission destination address variation pattern;
The 3rd counter is used to deposit the source address of DMA transmission;
Four-counter is used to deposit the destination address of DMA transmission;
Described DMA control module be used for according to the value of source address variation pattern register and destination address variation pattern register control the 3rd, the numerical value of the source/destination address of four-counter increases progressively or successively decrease or constant; And carry out DMA transmission according to the destination address of depositing in source address in the 3rd counter and the four-counter.
The another technical matters that the present invention will solve provides a kind of transmission method of realizing the high efficient DMA transmission, and described method comprises:
(a) receive the DMA transmission requests;
(b) carry out the DMA transmission; And to data quantity transmitted between peripheral hardware and dma controller, and dma controller and internal memory between data quantity transmitted count respectively;
The intact blocks of data of every transmission is carried out (c1);
(c1) judge whether data quantity transmitted reaches the peripheral hardware cache size between peripheral hardware and dma controller, if then carry out (c2), if otherwise return (b);
(c2) judge whether data quantity transmitted reaches cache size in the internal memory between dma controller and internal memory, if then carry out (d); If otherwise return (a);
(d) finish this DMA transmission.
Further, step (a) is preceding also exists:
(a1) initialization passage; The logical spatial cache size with peripheral hardware and internal memory of CPU is notified dma controller, and enables the hardware requests of passage;
Described step (d) also comprises: the hardware requests of closing passage enables.
Further, when the buffer memory Type-Inconsistencies of the buffer memory type of source hardware and purpose hardware, step (c) is specially:
Carry out DMA transmission, the data of carrying out the DMA transmission are spliced in described FIFO and split; The buffer memory type with source, purpose hardware is consistent respectively to make the data volume of each reading and writing operation.
After having adopted technical scheme of the present invention, each DMA data quantity transmitted is by spatial cache size decision in the internal memory, thereby can finish repeatedly the DMA transmission between peripheral hardware and dma controller in a DMA transmission, increase each DMA data quantity transmitted greatly, transfer efficiency significantly improves; And owing to reduced the number of times of access memory when transmission, the efficient of internal memory is improved; In addition, behind the employing prioritization scheme, can also further promote the efficient of DMA transmission.
Description of drawings
Fig. 1 is the principle of work synoptic diagram of dma controller in the prior art;
Fig. 2 is in the prior art, and dma controller receives the synoptic diagram of data;
Fig. 3 is in the prior art, and dma controller receives the synoptic diagram of data;
Fig. 4 be the present invention's transmission method of realizing high efficient DMA transmission concrete implementing procedure figure;
Fig. 5 is the synoptic diagram that dma controller of the present invention receives data;
Fig. 6 is the synoptic diagram that dma controller of the present invention receives data.
Embodiment
Below in conjunction with drawings and Examples technical scheme of the present invention is described in detail.
For convenience of description, at first explain the several notions that occur in the literary composition; In this article:
DMA transmission is meant from dma controller and initiates request and obtain bus control right to CPU, to the transmission of carrying out till dma controller sends interruption; In a DMA transmission, dma controller only need be visited internal memory one time, and institute's data quantity transmitted is the size of spatial cache in the internal memory.
DMA transmission between peripheral hardware and dma controller is meant that institute's data quantity transmitted is the spatial cache size of peripheral hardware from carrying out the transmission course of exchanges data between peripheral hardware and the dma controller; The size of the spatial cache integral multiple of peripheral hardware cache size normally in the internal memory; In the present invention, can comprise repeatedly the DMA transmission between peripheral hardware and dma controller in the DMA transmission.
The invention provides a kind of dma controller of realizing the high efficient DMA transmission, comprise DMA control module, data assembly form removal piece, FIFO (First In First Out first-in first-out register), registers group and counter.
Described registers group comprises:
Peripheral hardware cache size register is used to deposit the numerical value of the spatial cache size of peripheral hardware;
The memory cache sized registers is used for depositing the numerical value of internal memory spatial cache size;
Hardware requests enabled state register is used to deposit the numerical value of representing the hardware requests enabled state; Allow hardware requests such as 1 expression, other numeric representation does not allow hardware requests; When needing hardware to initiate the DMA transmission, be changed to the value of expression " permission hardware requests " by CPU;
The channel status register is used to deposit the numerical value of representing channel status; Occupied such as 1 expression passage, other numeric representation passage can be used;
Source address variation pattern register is used for depositing the numerical value that the source address variation pattern is transmitted in expression; Increase such as 1 expression, 2 expressions reduce, and other numeric representation is constant;
Destination address variation pattern register is used for depositing the numerical value of expression transmission destination address variation pattern; Increase such as 1 expression, 2 expressions reduce, and other numeric representation is constant;
Described counter comprises:
First counter, the byte number that is used for transmitting between the transmission of the DMA between peripheral hardware and dma controller is to peripheral hardware and dma controller is counted;
Second counter, the byte number that is used for transmitting between a DMA transmission is to dma controller and internal memory is counted;
The 3rd counter is used to deposit the source address of DMA transmission;
Four-counter is used to deposit the destination address of DMA transmission.
Described DMA control module is used to control the DMA transmission between peripheral hardware and internal memory; When the numeric representation " permission hardware requests " of described hardware requests enabled state register, receive the DMA transmission requests of hardware, when " not allowing hardware requests ", its value representation do not continue to inquire after; Also be used to inquire after the value of described channel status register,, carry out DMA during expression " passage can with " and transmit if continue to inquire after during its value representation " passage is occupied ".
Described DMA control module is used for carrying out between the DMA transmission period, controls described first, second counter and counts; And by judging that whether the count value of first counter is less than the numerical value in the peripheral hardware cache size register, judge whether the byte number that transmits between peripheral hardware and dma controller reaches the size of peripheral hardware spatial cache, finish the signal of the DMA transmission requests between this peripheral hardware and dma controller when reaching to peripheral hardware; Also be used for count value by second counter relatively whether less than the numerical value of memory cache sized registers, judge whether the byte number that transmits between dma controller and internal memory reaches the size in memory cache space, send passage to CPU when reaching and finish the transmission interrupt request, and the value of described hardware requests enabled state register is configured to " not allowing the value of hardware requests ".When receiving the data cached signal of handling of internal memory---when internal memory can receive again or send data, CPU can be configured to the value of described hardware requests enabled state register the value of " permission hardware requests "; To proceed the DMA transmission between peripheral hardware and internal memory.
Described DMA control module also is used for after beginning DMA transmission, and the value of the channel status register of used transmission channel is changed to " passage is occupied "; After the transmission of the DMA on this passage is finished or stopped, the value of channel status register is changed to the value of expression " passage can be used ".
In carrying out the process of DMA transmission, exist multiple demand for the variation of address.For example,, when depositing in a slice internal memory, just need source address constant, and destination address increase when needs are peeked from a FIFO; When peek is deposited among the FIFO from internal memory, then need source address to increase, destination address is constant.
Described source address variation pattern register and destination address variation pattern register are configured according to the actual transmissions needs by CPU, such as the number in the internal memory need be covered in a slice internal memory the time, then source address variation pattern register is changed to the value of expression " constant ", destination address variation pattern register is changed to the value of expression " increase ".
Described DMA control module also is used for judging according to the value of source address variation pattern register and destination address variation pattern register the variation pattern of source address and destination address, and the numerical value of expression source/destination address increases progressively or successively decreases or constant in the corresponding control the 3rd, four-counter; And carry out DMA transmission according to the destination address of depositing in source address in the 3rd counter and the four-counter; Three, the numerical value in the four-counter is initial source/destination address.
Such as when transmitting data to a FIFO from internal memory, destination address is fixed; The counter that an initial value is set is source address; The data of the each transmission of internal memory 8 bytes are given FIFO, and every transmission primaries just adds 8 with the value of counter, will be worth as new source address then.
In dma controller of the present invention, different hardware links to each other with the bus interface of respective volume (or size) according to the size of self buffer memory type, and each passage is according to the difference of the bus interface capacity that is connected, each data quantity transmitted is different, what have can transmit 32 bytes at every turn, such as with the passage that is used for linking to each other with the bus interface of internal memory swap data, be called standard channel; What have can only transmit 8 bytes at every turn, such as with the passage that is used for linking to each other with the bus interface of UART (Universal Asynchronous Receiver/Transmitter UART Universal Asynchronous Receiver Transmitter) swap data, be called non-standard passage.Therefore, different hardware is separately corresponding to different passages, and each passage is connected on the different hardware by different bus interface respectively in the dma controller in other words.
Described DMA control module is being carried out the DMA transmission of source hardware and purpose hardware cache Type-Inconsistencies, when transmitting such as the DMA between non-standard passage and the standard channel, start described data and piece together the form removal piece and the data of carrying out the DMA transmission at non-standard passage are spliced in described FIFO or splits, the buffer memory type with source, purpose hardware is consistent respectively to make the data volume that each reading and writing operate; And, when the splicing that receives data assembly form removal piece finishes message, the data that splicing is good among the FIFO are sent to purpose hardware; When the fractionation that receives data assembly form removal piece finished message, reading of data was put into FIFO from the hardware of source; When receiving the sent message of data assembly form removal piece, the data block of tearing open among the FIFO is sent to purpose hardware.
When purpose hardware is internal memory, the buffer memory type of explanation source hardware is littler than the destination address, described data were pieced together the form removal piece and will be spliced from the data that source hardware arrives FIFO this moment, issued the DMA control module splicing message that finishes when the data volume that arrives FIFO achieves the goal the buffer memory size of type of hardware; When source hardware is internal memory, the buffer memory type of explanation source hardware is bigger than purpose hardware, described data are pieced together the form removal piece and split out the data block that meets purpose hardware cache size of type in the data that arrive FIFO, whenever tear open once to issue one of DMA control module and can send message; Reach when the data volume that sends and issue the DMA control module after the buffer memory size of type of source hardware and split the message that finishes.
Described data are pieced together the form removal piece can also comprise a counter, is used for when splicing the data volume of arrival FIFO or the number of times of FIFO reception data being counted; The number of times that when splitting data volume or FIFO from the FIFO transmission is sent data is counted.
The present invention also provides a kind of method that realizes the high efficient DMA transmission, can finish repeatedly the transmission between peripheral hardware and dma controller in a DMA transmission, and as shown in Figure 4, described method comprises:
(a1) initialization passage;
CPU passes through configuration peripheral hardware cache size register with peripheral hardware spatial cache size notice dma controller, notifies dma controller by allocate memory cache size register with spatial cache size in the internal memory.
(a2) enable the hardware requests of passage by configure hardware request enabled state register;
(a3) the DMA transmission requests of wait hardware;
The DMA transmission requests here be outer if internal memory according to demand, after filling data when the peripheral hardware buffer memory, again or when preset time arrives, initiation DMA transmission requests.
Whether (b) can the DMA control module accept hardware requests by the value judgement passage of hardware requests enabled state register, and available by the value inquiry passage of channel status register;---used or last time transmission is not finished---if it is unavailable to accept hardware requests or passage then returning (b), the value that promptly continues to inquire after these two registers by other hardware such as passage; That is to say, when the transmission of a direction imperfect tense, can not begin the transmission of other direction; For example carrying out peripheral hardware when internal memory sends the DMA transmission of data, before not finishing, promptly buffer memory is less than preceding in the internal memory, and the DMA that can not initiate to fetch data from internal memory transmits.
Can use if can accept hardware requests and passage, then this moment, dma controller was just obtained bus control right; The value of first, second counter is set to 0, and the channel status register is changed to the value of expression " passage is occupied ", execution in step (c).
(c) begin to carry out the DMA transmission;
In transmission, first counter is that unit counts with the byte to data quantity transmitted between peripheral hardware and dma controller, and second counter is that unit counts with the byte to data quantity transmitted between dma controller and internal memory.
The intact blocks of data of every transmission is carried out (d1), and a blocks of data can be set to a kind of in a byte, nybble, Eight characters joint and 16 bytes usually, and the space size of buffer memory is the integral multiple of " piece ".
(d1) whether the counting of judging first counter reaches the numerical value in the peripheral hardware cache size register, if then dma controller is issued the signal that peripheral hardware is finished the DMA transmission between this peripheral hardware and dma controller, the channel status register is changed to the value of expression " passage can be used "; First counter is set to 0 back and carries out (d2); Otherwise carry out (c), promptly continue the DMA transmission.
(d2) whether the counting of judging second counter reaches the numerical value in the memory cache sized registers, if then carry out (e), can this moment second counter be set to 0, also can be set to 0 when the new DMA transmission of beginning; Otherwise return (a3).
(e) dma controller sends passage to CPU and finishes the transmission interrupt request, informs the transmission of finishing this section internal storage data, has promptly filled up the buffer memory of internal memory, finishes this DMA transmission; The hardware requests of meanwhile closing this passage enables; Till CPU reconfigures this passage.
Hence one can see that, after dma controller is obtained bus control right, can transmit the data volume that is equivalent to the memory cache size, and transfer efficiency improves greatly, and the access times of internal memory are also reduced thus.
Generally, the memory cache size is the integral multiple of hardware cache size, thus adopt in the present invention the first counter meter to after judge that again the mode of second counter operates; If in the practical application, the memory cache size having occurred is not the situation of the integral multiple of hardware cache size, just simultaneously the numerical value of first counter and second counter is all judged once behind the intact blocks of data of then every biography; And in this case, judgement and processing comparison first counter that should set second counter have higher priority level.
When the buffer memory Type-Inconsistencies of the buffer memory type of source hardware and purpose hardware, step (c) is specially: carry out the DMA transmission, according to the buffer memory type reading of data of transmission sources hardware in FIFO, in FIFO, splice or split, after making its buffer memory type consistent, it is transferred to purpose hardware with purpose hardware.
Here can be internal memory as transmission sources hardware, peripheral hardware is as purpose hardware; Also can be opposite.
Specify with an example below, buffer memory type such as the peripheral hardware of UART (Universal AsynchronousReceiver/Transmitter UART Universal Asynchronous Receiver Transmitter) and so on only has the byte type, and original dma controller at every turn can only be with the transmission of the least-significant byte in bus data.And in the present invention, when peripheral hardware fetches data, as shown in Figure 5, dma controller from the peripheral hardware buffer memory with byte form reading of data in FIFO, just whenever read once counting once, when counting reaches 4, with the form write memory of the data among the FIFO with word; And when peripheral hardware sends data, as shown in Figure 6, dma controller from internal memory with the form reading of data of word in FIFO, the form with byte sends the data to hardware from FIFO then, every transmission once just counting once, when counting reached 4, transmission finished.
Above-mentioned is optimum embodiment of the present invention, and all the other parts same as the prior art repeat no more.Under the situation that does not deviate from spirit of the present invention and essence thereof, those of ordinary skill in the art can make various corresponding distortion according to the present invention, but these corresponding distortion all should belong to the present invention.
Claims (8)
1, a kind of dma controller of realizing efficient direct memory access DMA transmission comprises the DMA control module, is used to control the DMA transmission between peripheral hardware and internal memory; It is characterized in that: when described DMA control module reaches peripheral hardware spatial cache size when the byte number that transmits between peripheral hardware and dma controller, finish the signal of the DMA transmission requests between this peripheral hardware and dma controller to peripheral hardware; When the byte number that transmits between dma controller and internal memory reaches memory cache space size, send passage to CPU and finish the transmission interrupt request.
2, dma controller as claimed in claim 1 is characterized in that, also comprises:
Peripheral hardware cache size register is used to deposit the numerical value of the spatial cache size of peripheral hardware;
The memory cache sized registers is used for depositing the numerical value of internal memory spatial cache size;
First counter, the byte number that is used for transmitting between the transmission of the DMA between peripheral hardware and dma controller is to peripheral hardware and dma controller is counted;
Second counter, the byte number that is used for transmitting between a DMA transmission is to dma controller and internal memory is counted;
Whether the count value that described DMA control module is passed through to judge first counter judges whether the byte number that between peripheral hardware and dma controller transmit reach the size of peripheral hardware spatial cache less than the numerical value in the peripheral hardware cache size register; Whether count value by second counter relatively judges whether the byte number that between dma controller and internal memory transmit reach the size in memory cache space less than the numerical value in the memory cache sized registers.
3, dma controller as claimed in claim 2 is characterized in that, also comprises:
Hardware requests enabled state register is used to deposit the numerical value of representing the hardware requests enabled state, comprises the value of expression " permission hardware requests " and " not allowing hardware requests "; When needing hardware to initiate the DMA transmission, be changed to the value of expression " permission hardware requests " by CPU;
The channel status register is used to deposit the numerical value of representing channel status, comprises the value of expression " passage is occupied " and the value of expression " passage can be used ";
Described DMA control module is used to control the DMA transmission between peripheral hardware and internal memory; When the numeric representation " permission hardware requests " of described hardware requests enabled state register, receive the DMA transmission requests of hardware, when " not allowing hardware requests ", its value representation do not continue to inquire after; And the byte number that transmits between dma controller and internal memory reaches memory cache space when size, and described hardware requests enabled state register is changed to the value that expression " does not allow hardware requests ".
Described DMA control module also is used to inquire after the value of described channel status register, if continue to inquire after during its value representation " passage is occupied ", carries out DMA during expression " passage can with " and transmits; And after beginning DMA transmission, the value of the channel status register of used transmission channel is changed to " passage is occupied "; After the transmission of the DMA on this passage is finished or stopped, the value of channel status register is changed to the value of expression " passage can be used ".
4, dma controller as claimed in claim 2 is characterized in that: also comprise a plurality of passages; The each data quantity transmitted of each passage is corresponding to the bus interface that is connected; With each data quantity transmitted is that the passage of 32 bytes is called standard channel; Each data quantity transmitted is called non-standard passage less than the passage of 32 bytes; Each passage is connected on the different hardware by different bus interface respectively;
Described DMA control module the time starts described data and pieces together the form removal piece and the data of carrying out the DMA transmission at non-standard passage are spliced in described FIFO or splits carrying out DMA transmission between non-standard passage and the standard channel, and the buffer memory type with source, purpose hardware is consistent respectively to make the data volume that each reading and writing operate; And, when the splicing that receives data assembly form removal piece finishes message, the data that splicing is good among the FIFO are sent to purpose hardware; When the fractionation that receives data assembly form removal piece finished message, reading of data was put into FIFO from the hardware of source; When receiving the sent message of data assembly form removal piece, the data block of tearing open among the FIFO is sent to purpose hardware;
Described data piece together the form removal piece when the buffer memory type of source hardware than destination address hour, will splice from the data that source hardware arrives FIFO, when the data volume that arrives FIFO achieves the goal the buffer memory size of type of hardware, issue the DMA control module splicing message that finishes; When the buffer memory type of source hardware during than purpose hardware big, described data are pieced together the form removal piece and split out the data block that meets purpose hardware cache size of type in the data that arrive FIF0, whenever tear open once to issue one of DMA control module and can send message; Reach when the data volume that sends and issue the DMA control module after the buffer memory size of type of source hardware and split the message that finishes.
5, dma controller as claimed in claim 1 is characterized in that, also comprises:
Source address variation pattern register is used for depositing the numerical value that the source address variation pattern is transmitted in expression;
Destination address variation pattern register is used for depositing the numerical value of expression transmission destination address variation pattern;
The 3rd counter is used to deposit the source address of DMA transmission;
Four-counter is used to deposit the destination address of DMA transmission;
Described DMA control module be used for according to the value of source address variation pattern register and destination address variation pattern register control the 3rd, the numerical value of the source/destination address of four-counter increases progressively or successively decrease or constant; And carry out DMA transmission according to the destination address of depositing in source address in the 3rd counter and the four-counter.
6, a kind of method that realizes the high efficient DMA transmission, described method comprises:
(a) receive the DMA transmission requests;
(b) carry out the DMA transmission; And to data quantity transmitted between peripheral hardware and dma controller, and dma controller and internal memory between data quantity transmitted count respectively;
The intact blocks of data of every transmission is carried out (c1);
(c1) judge whether data quantity transmitted reaches the peripheral hardware cache size between peripheral hardware and dma controller, if then carry out (c2), if otherwise return (b);
(c2) judge whether data quantity transmitted reaches cache size in the internal memory between dma controller and internal memory, if then carry out (d); If otherwise return (a);
(d) finish this DMA transmission.
7, method as claimed in claim 6 is characterized in that, step (a) is preceding also to be existed:
(a1) initialization passage; The logical spatial cache size with peripheral hardware and internal memory of CPU is notified dma controller, and enables the hardware requests of passage;
Described step (d) also comprises: the hardware requests of closing passage enables.
8, method as claimed in claim 6 is characterized in that: when the buffer memory Type-Inconsistencies of the buffer memory type of source hardware and purpose hardware, step (c) is specially:
Carry out DMA transmission, the data of carrying out the DMA transmission are spliced in described FIFO and split; The buffer memory type with source, purpose hardware is consistent respectively to make the data volume of each reading and writing operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100988321A CN100464318C (en) | 2007-04-27 | 2007-04-27 | DMA controller and transmission method of implementing high efficient DMA transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100988321A CN100464318C (en) | 2007-04-27 | 2007-04-27 | DMA controller and transmission method of implementing high efficient DMA transmission |
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| CN102290050A (en) * | 2010-06-18 | 2011-12-21 | 北京中星微电子有限公司 | Audio data transmission method and device |
| CN103714026A (en) * | 2014-01-14 | 2014-04-09 | 中国人民解放军国防科学技术大学 | Memorizer access method and device supporting original-address data exchange |
| CN104182264A (en) * | 2014-09-03 | 2014-12-03 | 福州瑞芯微电子有限公司 | eMMC (embedded multi-media card) starting optimization method and device thereof |
| CN105389156A (en) * | 2015-11-24 | 2016-03-09 | 珠海全志科技股份有限公司 | Method and system for reducing delay from sound input to sound output based on DMA technology |
| CN105786733A (en) * | 2014-12-26 | 2016-07-20 | 中兴通讯股份有限公司 | TCAM (Ternary Content Addressable Memory) entry writing method and apparatus |
| CN105955764A (en) * | 2016-04-22 | 2016-09-21 | 佛山市南海区欧谱曼迪科技有限责任公司 | Improvement method for STM32 single-chip microcomputer IAP serial program burning |
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| CN110046114A (en) * | 2019-03-06 | 2019-07-23 | 上海熠知电子科技有限公司 | Dma controller and DMA data transfer method based on PCIE agreement |
| CN110059042A (en) * | 2019-04-30 | 2019-07-26 | 成都启英泰伦科技有限公司 | A kind of data DMA transfer method of UART equipment |
| CN111110966A (en) * | 2019-12-02 | 2020-05-08 | 湖南明康中锦医疗科技发展有限公司 | Multi-module communication control method and respiratory support equipment |
| CN113868158A (en) * | 2021-08-27 | 2021-12-31 | 浪潮电子信息产业股份有限公司 | On-chip system, data comparison method, device, equipment and computer medium |
| CN114328318A (en) * | 2021-12-28 | 2022-04-12 | 湖南航天经济发展有限公司 | DMA controller for direct equipment interconnection for microcontroller and interconnection control method |
| CN114356813A (en) * | 2021-12-15 | 2022-04-15 | 中国航空工业集团公司成都飞机设计研究所 | Bus data efficient IO method based on message block DMA |
| CN114741345A (en) * | 2022-04-24 | 2022-07-12 | 苏州雄立科技有限公司 | USB DMA data transmission device and method |
| CN117667790A (en) * | 2022-08-24 | 2024-03-08 | 上海合见工业软件集团有限公司 | Discrete DMA data transmission system |
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| US6922741B2 (en) * | 2002-02-01 | 2005-07-26 | Intel Corporation | Method and system for monitoring DMA status |
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| CN102290050B (en) * | 2010-06-18 | 2014-07-30 | 北京中星微电子有限公司 | Audio data transmission method and device |
| CN102290050A (en) * | 2010-06-18 | 2011-12-21 | 北京中星微电子有限公司 | Audio data transmission method and device |
| CN103714026A (en) * | 2014-01-14 | 2014-04-09 | 中国人民解放军国防科学技术大学 | Memorizer access method and device supporting original-address data exchange |
| CN103714026B (en) * | 2014-01-14 | 2016-09-28 | 中国人民解放军国防科学技术大学 | A kind of memory access method supporting former address data exchange and device |
| CN104182264A (en) * | 2014-09-03 | 2014-12-03 | 福州瑞芯微电子有限公司 | eMMC (embedded multi-media card) starting optimization method and device thereof |
| CN104182264B (en) * | 2014-09-03 | 2017-07-11 | 福州瑞芯微电子股份有限公司 | The start optimization method and its device of a kind of eMMC |
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| CN105389156B (en) * | 2015-11-24 | 2018-12-11 | 珠海全志科技股份有限公司 | A kind of method and system reducing voice input to output delay based on DMA technology |
| CN105389156A (en) * | 2015-11-24 | 2016-03-09 | 珠海全志科技股份有限公司 | Method and system for reducing delay from sound input to sound output based on DMA technology |
| CN105955764A (en) * | 2016-04-22 | 2016-09-21 | 佛山市南海区欧谱曼迪科技有限责任公司 | Improvement method for STM32 single-chip microcomputer IAP serial program burning |
| CN107870879B (en) * | 2016-09-23 | 2020-04-03 | 中国移动通信有限公司研究院 | Data moving method, accelerator board card, host and data moving system |
| CN107870879A (en) * | 2016-09-23 | 2018-04-03 | 中国移动通信有限公司研究院 | A kind of data-moving method, accelerator board, main frame and data-moving system |
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| CN108388529B (en) * | 2018-01-26 | 2021-03-09 | 武汉中元华电电力设备有限公司 | Method for actively realizing data exchange between peripheral and CPU |
| CN110046114B (en) * | 2019-03-06 | 2020-08-14 | 上海熠知电子科技有限公司 | DMA controller based on PCIE protocol and DMA data transmission method |
| CN110046114A (en) * | 2019-03-06 | 2019-07-23 | 上海熠知电子科技有限公司 | Dma controller and DMA data transfer method based on PCIE agreement |
| CN110059042B (en) * | 2019-04-30 | 2023-02-07 | 成都启英泰伦科技有限公司 | Data DMA transmission method of UART equipment |
| CN110059042A (en) * | 2019-04-30 | 2019-07-26 | 成都启英泰伦科技有限公司 | A kind of data DMA transfer method of UART equipment |
| CN111110966A (en) * | 2019-12-02 | 2020-05-08 | 湖南明康中锦医疗科技发展有限公司 | Multi-module communication control method and respiratory support equipment |
| CN111110966B (en) * | 2019-12-02 | 2022-05-27 | 湖南明康中锦医疗科技发展有限公司 | Multi-module communication control method and respiratory support equipment |
| CN113868158A (en) * | 2021-08-27 | 2021-12-31 | 浪潮电子信息产业股份有限公司 | On-chip system, data comparison method, device, equipment and computer medium |
| CN113868158B (en) * | 2021-08-27 | 2024-02-23 | 浪潮电子信息产业股份有限公司 | System-on-chip and data comparison method, device, equipment and computer medium |
| CN114356813A (en) * | 2021-12-15 | 2022-04-15 | 中国航空工业集团公司成都飞机设计研究所 | Bus data efficient IO method based on message block DMA |
| CN114328318A (en) * | 2021-12-28 | 2022-04-12 | 湖南航天经济发展有限公司 | DMA controller for direct equipment interconnection for microcontroller and interconnection control method |
| CN114741345A (en) * | 2022-04-24 | 2022-07-12 | 苏州雄立科技有限公司 | USB DMA data transmission device and method |
| CN114741345B (en) * | 2022-04-24 | 2024-02-13 | 苏州雄立科技有限公司 | USB DMA data transmission device and method |
| CN117667790A (en) * | 2022-08-24 | 2024-03-08 | 上海合见工业软件集团有限公司 | Discrete DMA data transmission system |
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