CN110059042A - A kind of data DMA transfer method of UART equipment - Google Patents
A kind of data DMA transfer method of UART equipment Download PDFInfo
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- CN110059042A CN110059042A CN201910358026.6A CN201910358026A CN110059042A CN 110059042 A CN110059042 A CN 110059042A CN 201910358026 A CN201910358026 A CN 201910358026A CN 110059042 A CN110059042 A CN 110059042A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
A kind of data DMA transfer method of UART equipment, include the following steps: that S1. is initialized: initialization UART equipment is DMA operating mode, establishes DMA transfer channel；S2. setting caching chain；S3. application layer data is packaged: original outgoing data adds header packet information, and header packet information includes packet header sync mark；S4. link layer data is packaged；S5. whether system detection DMA is in idle condition, and is, issues DMA enable signal, starts to send data.S6. buffer area data volume, decoding data are calculated.The present invention passes through design DMA chain table cache, it data will be sent carries out link layer, application layer and be packaged twice, and DMA transfer data volume be detected by inquiry mode, and to the data cached progress partial data Packet analyzing of chained list, the efficiency and accuracy rate for improving data transmission, improve the utilization rate of MCU.
Description
Technical field
The invention belongs to software technology fields, are related to data transmission technology, and in particular to a kind of data DMA of UART equipment
Transmission method.
Background technique
Universal asynchronous receiving-transmitting transmitter is commonly referred to as UART(Universal Asynchronous Receiver/
Transmitter).The data that it will be transmitted is converted between serial communication and parallel communications.As parallel input
Signal changes into the chip of serial output signal, and UART equipment is usually integrated in the connection of other communication interfaces.The bus is double
To communication, full duplex transmission and reception may be implemented.In embedded design, UART equipment is logical for host and ancillary equipment
Letter.
Under normal conditions, data are transmitted or received to UART equipment in the form interrupted or inquired, and is controlled by MCU
The inside FIFO of UART processed is realized.However, always being occupied in transmission process to interrupt or in the form of inquiry
To the time of MCU.In this way, when such as audio data, firmware updating data, serial data packet is larger when transmitting big data quantity,
The transmission process of UART equipment can trigger a large amount of interruptions, and MCU is needed from source the document copying of each segment to buffer, so
They are written back to afterwards new place.In this time, MCU is not just available for others work, wherein
Most of time may be to wait data packet to be transmitted to influence the operating rate of system, and be also possible that data
It loses or mistake, the efficiency so as to cause data transmission is lower.
Summary of the invention
To overcome technological deficiency of the existing technology, the invention discloses a kind of data DMA transfer sides of UART equipment
Method.
It is of the present invention.
The present invention, in conjunction with dma controller, allows the hard of friction speed on the basis of conventional UART serial data communication
Part device is linked up, and a large amount of interrupt loads without depending on CPU, realization leads to UART serial data packet by DMA
It carries in road.
The present invention will be sent data and carry out link layer, application layer and be packaged twice by design DMA chain table cache, by looking into
Inquiry mode detects DMA transfer data volume, and to the data cached progress partial data Packet analyzing of chained list, improves the effect of data transmission
Rate and accuracy rate improve the utilization rate of MCU.
Detailed description of the invention
Fig. 1 is a kind of specific embodiment schematic diagram of data transmission flow in the present invention；
Fig. 2 is a kind of specific embodiment schematic diagram that data are packaged process in the present invention；
Fig. 3 is a kind of specific embodiment schematic diagram that data are packaged in step S3 of the present invention；CMD in Fig. 3 indicates life
Enable prompt；
Fig. 4 is a kind of specific embodiment schematic diagram of data receiver process of analysis in the present invention；.
Specific embodiment
With reference to the accompanying drawing, specific embodiments of the present invention will be described in further detail.
The data DMA transfer method of UART equipment of the present invention, specifically comprises the following steps:
Initialization UART equipment is DMA (Direct Memory Access, direct memory access) operating mode first；
The initialization procedure generally comprises to be operated in detail below: enabled UART clock is arranged UART baud rate, is arranged UART's
Depth is triggered, the transmitting and receiving that UART is arranged is dma mode；
Configure DMA relevant parameter, the data rate memory including DMA transfer, address data memory etc.；
DMA transfer data-interface is selected in UART equipment；Such as using the CI1006 voice recognition chip for opening Ying Tailun company,
CPU is ARM Cortex-M4F, chooses the data-interface that its port UART1 is DMA transfer channel；And simultaneous selection with
The UART 1 of the MTK7697 WIFI module of CI1006 connection is data-interface, establishes DMA transfer between two data-interfaces
Channel.
Chain table cache is defined in dma device, caching is divided into M equal-sized chained list cache blocks, and by these chains
Table cache block forms a Circular buffer chain, initializes chained list cache blocks；
Using in Circular buffer chain data source address and destination address as the data source address of DMA transfer, datum target address,
And using next chained list cache blocks of first chained list caching block chaining as its subsequent module, and so on all chained lists of setting
Cache blocks；
The data-triggered that every transmission K size in DMA transfer is arranged once is interrupted, and can calculate caching according to down trigger number
The size of data of block storage;The K can divide exactly L and be less than L, and the L is the storage size of chained list cache blocks.Here
Each down trigger indicates to complete once to carry, and the size of data of cache blocks storage can be calculated according to interruption times.
It is every to carry L/M data one chained list cache blocks of switching.
Before transmission, need to be packaged data；
Carry out application layer data packing first: original outgoing data adds header packet information, and header packet information usually should include that packet header is same
Step mark, data check and, the affiliated type of data, data original length, data version information, data filling information etc..
The packet header sync mark be for packet header is marked,
Application layer data biases toward the complete acquisition to data information, after the completion of application layer is packaged, carries out link layer data packing,
The purpose that link layer is packaged is preferably to carry out data transmission
Link layer data is packaged: application layer being packaged to the data completed and adds data beginning label in data header, at data end
Tail addition terminates label；
In step S4, escape, the escape can be carried out to data specifically: whether the data between detection packet header and packet tail have
Identical byte section is marked with the beginning label or end, it is primary if there is the byte section then to be replicated to extension automatically；
After the completion of link layer data is packaged, data length, that is, size of data after being packaged is returned.
After the completion of link layer is packaged, it is transmitted to UART coffret,
Whether subsequent system detection DMA is in idle condition, and state is periodically inquired if being not in idle state, if in passing
Defeated state then waits the data transmitted to be transmitted, and detects that data are transmitted, DMA channel be idle state after, by
Transmission process configures UART transmission interface, and the size of this data transmission is arranged according to the aforementioned data length returned after being packaged
And data address, DMA enable signal is issued, starts to send data.
Data receiver decoder module can periodically, such as every 10ms inquires whether data in a chained list cache blocks increase,
It detects that data have the data for increasing and then parsing in cache blocks, then extracts data when parsing a complete data packet, and discharge
The spatial cache that the data packet occupies in cache blocks；To emptying cache blocks, facilitates and subsequent continue to write to data.
By reading DMA register data and DMA down trigger number, current buffer area size of data can be calculated,
If data volume has increase than last time detection, data parsing is carried out.Wherein DMA register is for before temporarily storage is interrupted
Storing data, every to interrupt primary, data can be all stored in cache blocks
When carrying out data decoding, two pointer record buffer area data starting and ending positions are used respectively, whenever buffer area number
When according to increasing, the data volume between starting and ending position is calculated, data can be subjected to the link number of plies since start position
According to parsing, wherein start position can move backward a byte every time, until parsing a complete data packet or reaching knot
Stop moving back when beam position, after parsing complete data packet, then character in restoring data extracts data, and updates and release
Put buffer area.
If using Meaning transfer above-mentioned in step S4, corresponding decoding process in step S6 are as follows: remove beginning
Label is marked and terminates, detection remaining data, which whether there is to have, marks identical byte section with the beginning label or end, has
It then continues to test it and closes on byte with the presence or absence of having and the beginning label or terminating to mark identical byte section, have, remove one
A and described beginning label terminates to mark identical byte section.
Such as beginning label is A5, terminates to be labeled as A4, also there is an A5, such as data to be transmitted in data to be transmitted
For A5 12 34 56, increases beginning label and terminates after marking are as follows:
12 34 56 A4 of A5 A5, if detect beginning label and terminate label among occur an A5, by data after
It is continuous to be extended to
A5 A5 A5 12 34 56 A4;
In subsequent data resolving, after removing beginning label and terminating label, per one beginning label of discovery again,
Identical bytes are then continued to test forward and see whether remain as beginning label, are to remove one, are otherwise next data packet head.
Then 12 34 56 A4 of A5 A5 A5 removes beginning label first and terminates label,
Become A5 A5 12 34 56, continue thereafter with discovery beginning label A5, the front remains as A5, further removes one
A5 becomes A5 12 34 56；No longer occur identical label A5 before beginning label A5 at this time, then parses initial data.
Finally the data of extraction are carried out to extract data packet header information according to packet header sync mark with layer parsing verification,
Verified, verification mode can be specifically: calculate parsing after data verification and, in header packet information verification and compared with,
If the same data are effective, otherwise abandon data, send the data to related processing task depending on the type of valid data.
One more specific embodiment is as follows:
DMA transfer channel is set between CI1006 and 1 port UART of WIFI module MTK7697 WIFI, two modules
UART is configured to DMA operating mode, to adapt to monophonic voices sampling, uses baud rate for 961200bps, theoretical transmission speed
Degree is 112.5K/S, enough real-time Transmission 16K sample rate monophonic voices data.
The received data of UART interface are stored in chain table cache, it is 4K's by 20 sizes that chain table cache total size, which is 80K,
Data cache block link composition.Setting DMA carries every 1K data-triggered and once interrupts, and sets every transmission 4K data and switches a 4K
The data cache block of size.
Carry out application layer data packing: original outgoing data adds packet header, and head-coating structure includes packet header sync mark
0x5a5aa5a5, the verification of data and, the affiliated type of data, data length, data version information, data filling information.
Link layer data is packaged: the data that application layer is packaged add the data beginning label 0xA5 of a byte, in number
0xA4 is marked according to the end that a byte is added at end, whether the data detected between packet header and packet tail have and start over label
The identical data of 0xA5,0xA4 carry out escape if there is the data are then increased one automatically to distinguish and data packet head packet tail
Label, finally returns to packaged data length.
Application layer head-coating structure are as follows:
typedef struct uart_msg_header_t
{
unsigned int magic;
unsigned short checksum;
unsigned short type;
unsigned short len;
unsigned short version;
unsigned int fill_data;
}uart_msg_header;
Wherein magic is the synchronizing information of data packet head, is set as 0x5a5aa5a5, when detecting that Data Start is
Then it is considered that packet header marks when 0x5a5aa5a5, can extract header data；Checksum be data verification and, type is data
Affiliated type, len are data length, and version is data version information, and fill_data is reserved information position.
Data are sent, and packed data are delivered in data-transfer process, transmit the current DMA work shape of process detection
State, if in just in transmission state if wait the data transmitted to be transmitted, detect DMA be idle state after, by
Transmission process configures UART transmission interface, and the size and data address of the transmission of this data is arranged, and enables DMA and sends number
According to.
In DRP data reception process, the every 10ms of data processing process detects buffer area data more new state, is posted by reading DMA
Latch data and DMA down trigger number, can calculate current buffer area size of data, if data volume has than last time detection
Increase, then carries out data parsing.
Data parsing is specifically, using two pointer record buffer area data starts, whenever buffer area data increase
When, data volume between initial position is calculated, data are subjected to link layer data parsing since start position, wherein start position
A byte can be moved backward every time, stop moving back when parsing a complete data packet or reaching end position, when
After parsing complete data packet, then escape character in restoring data extracts data, updates buffer area data.It will finally mention
The data taken carry out extracting data packet header information according to packet header sync mark 0x5a5aa5a5 with layer parsing verification, calculate number
According to verification and, in packet header verification and compared with, if the same data are effective, and depending on the type of valid data by data
It is sent to related processing task.
The present invention, in conjunction with dma controller, allows the hard of friction speed on the basis of conventional UART serial data communication
Part device is linked up, and a large amount of interrupt loads without depending on CPU, realization leads to UART serial data packet by DMA
It carries in road.
The present invention will be sent data and carry out link layer, application layer and be packaged twice by design DMA chain table cache, by looking into
Inquiry mode detects DMA transfer data volume, and to the data cached progress partial data Packet analyzing of chained list, improves the effect of data transmission
Rate and accuracy rate improve the utilization rate of MCU.
Previously described is each preferred embodiment of the invention, if the preferred embodiment in each preferred embodiment
It is not obvious contradictory or premised on a certain preferred embodiment, each preferred embodiment can any stack combinations
Use, the design parameter in the embodiment and embodiment only for the purpose of clearly stating the inventor's invention verification process, and
It is non-to limit scope of patent protection of the invention, scope of patent protection of the invention is still subject to the claims, all
It is that similarly should be included in protection model of the invention with the variation of equivalent structure made by specification and accompanying drawing content of the invention
In enclosing.
Claims (6)
1. a kind of data DMA transfer method of UART equipment, which comprises the steps of:
S1. initialize: initialization UART equipment is DMA operating mode, establishes DMA transfer channel；
In the operating mode, the data-triggered that every transmission K size in DMA transfer is arranged once is interrupted, and the K can divide exactly L
And it is less than L, the L is the storage size of chained list cache blocks in S2；
S2. setting caching chain: caching is divided into M equal-sized chained list cache blocks by application spatial cache, and by these chained lists
Cache blocks form a Circular buffer chain, spatial cache are initialized, by the data source address and destination address in Circular buffer chain
Data source address, datum target address as DMA transfer,
S3. application layer data is packaged: original outgoing data adds header packet information, and header packet information includes packet header sync mark；
S4. link layer data is packaged: application layer being packaged to the data completed and adds data beginning label in data header, in number
Adding according to end terminates label；After the completion of link layer data is packaged, the data length after being packaged is returned to, data packet is transmitted to UART biography
It is defeated to use data-interface；
S5. whether system detection DMA is in idle condition, and is, issues DMA enable signal, starts to send data；
S6. data receiver calculates current buffer area data volume by reading DMA register data and DMA down trigger number
Size, and detection data amount changes, if data volume increases, carries out data decoding.
2. data DMA transfer method as described in claim 1, which is characterized in that the initialization procedure includes following operation:
Enabled UART clock, is arranged UART baud rate, the triggering depth of UART is arranged, and the transmitting and receiving that UART is arranged is dma mode.
3. data DMA transfer method as described in claim 1, which is characterized in that in step S4, can turn to data
Justice, the escape specifically: whether the data between detection packet header and packet tail have identical with the beginning label or end label
Byte section, it is primary if there is the byte section then to be replicated to extension automatically；
Corresponding decoding process in step S6 are as follows: remove beginning label and terminate label, detection remaining data with the presence or absence of having and
The beginning label terminates to mark identical byte section, has, and continues to test it and closes on byte with the presence or absence of having and the beginning
Label terminates to mark identical byte section, has, and removes one and marks identical byte section with the beginning label or end.
4. data DMA transfer method as described in claim 1, which is characterized in that in the step S6, before decoding data, also
Including the detection process transmitted for data, the detection process specifically:
Data receiver decoder module timing inquires whether data in a chained list cache blocks increase, and detects that data have increase then to solve
The data in cache blocks are analysed, then extract data when parsing a complete data packet, and discharge the data packet and account in cache blocks
According to spatial cache.
5. data DMA transfer method as claimed in claim 4, which is characterized in that the inquiry whether increased specific method of data
Are as follows: by reading DMA register data and DMA down trigger number, current buffer area size of data is calculated, if data volume
Than having increase when last time detection, then judge that data increase.
6. data DMA transfer method as described in claim 1, which is characterized in that include verification and institute in the header packet information
Stating further includes decoded verification step in step S6, the verification step are as follows: calculate parsing after data verification and, with packet header
Verification in information and compare, if the same data are effective, otherwise judge data invalid.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110597744A (en) * | 2019-08-30 | 2019-12-20 | 深圳震有科技股份有限公司 | Data synchronous transmission method, system and computer equipment |
| CN111026687A (en) * | 2019-10-30 | 2020-04-17 | 深圳震有科技股份有限公司 | Method, system and computer equipment for matching data transmission read-write rate |
| CN112002115A (en) * | 2020-08-05 | 2020-11-27 | 中车工业研究院有限公司 | Data acquisition method and data processor |
| CN112416839A (en) * | 2020-11-02 | 2021-02-26 | 光华临港工程应用技术研发(上海)有限公司 | System for realizing UART (universal asynchronous receiver transmitter) communication |
| CN112614247A (en) * | 2020-12-11 | 2021-04-06 | 北京小马智行科技有限公司 | Vehicle-mounted data recording device, data processing method and vehicle |
| WO2021109707A1 (en) * | 2019-12-02 | 2021-06-10 | 湖南明康中锦医疗科技发展有限公司 | Multi-module communication control method and respiratory support device |
| CN114785452A (en) * | 2022-03-16 | 2022-07-22 | 浙江万胜智能科技股份有限公司 | Multi-channel data transmission method fusing terminal USB |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110597744A (en) * | 2019-08-30 | 2019-12-20 | 深圳震有科技股份有限公司 | Data synchronous transmission method, system and computer equipment |
| CN111026687A (en) * | 2019-10-30 | 2020-04-17 | 深圳震有科技股份有限公司 | Method, system and computer equipment for matching data transmission read-write rate |
| CN111026687B (en) * | 2019-10-30 | 2023-08-01 | 深圳震有科技股份有限公司 | Method, system and computer equipment for data transmission read-write rate matching |
| WO2021109707A1 (en) * | 2019-12-02 | 2021-06-10 | 湖南明康中锦医疗科技发展有限公司 | Multi-module communication control method and respiratory support device |
| CN112002115A (en) * | 2020-08-05 | 2020-11-27 | 中车工业研究院有限公司 | Data acquisition method and data processor |
| CN112002115B (en) * | 2020-08-05 | 2021-04-23 | 中车工业研究院有限公司 | Data acquisition method and data processor |
| CN112416839A (en) * | 2020-11-02 | 2021-02-26 | 光华临港工程应用技术研发(上海)有限公司 | System for realizing UART (universal asynchronous receiver transmitter) communication |
| CN112614247A (en) * | 2020-12-11 | 2021-04-06 | 北京小马智行科技有限公司 | Vehicle-mounted data recording device, data processing method and vehicle |
| CN114785452A (en) * | 2022-03-16 | 2022-07-22 | 浙江万胜智能科技股份有限公司 | Multi-channel data transmission method fusing terminal USB |
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