CN112416839A - System for realizing UART (universal asynchronous receiver transmitter) communication - Google Patents
System for realizing UART (universal asynchronous receiver transmitter) communication Download PDFInfo
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Abstract
The invention discloses a system for realizing communication between UARTs. The system comprises: the first UART interface module comprises a first UART0 interface module and a first UART1 interface module, the first UART0 interface module is connected with a first terminal device, and the first UART1 interface module comprises a data receiving pin; a second UART interface module including a second UART1 interface module, the second UART1 interface module including a data transmitting pin, the data receiving pin of the first UART1 interface module being connected to the data transmitting pin of the second UART1 interface module, so that the first UART interface module receives data from the second UART interface module. According to the system for realizing the communication between the UARTs, the communication between the UARTs can be realized, the data verification is carried out at the processor (such as P) end, the communication between two acquisition terminals using the UARTs as interfaces is realized, and the data verification can be carried out through terminal equipment externally connected with the UARTs.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a system for realizing communication between UARTs.
Background
The UART interface is a general serial data bus used for asynchronous communications. In a conventional embedded design, a UART interface is used to communicate with a PC. However, at present, the UART interface and the PC often communicate by directly connecting a 4Pin bank, and the 4Pin bank includes a VCC Pin, a GND Pin, a data transmission Pin UART _ TX and a data reception Pin UART _ RX. Such a connection is prone to cause interference, causing the embedded system to enter an abnormal mode and causing the product to fail to operate properly.
A method for realizing communication between UART interface and PC is to use USB to UART communication module to realize UART interface to connect computer through USB, and to convert the signal sent by computer into UART communication format, then to convert the signal level into the level standard needed by communication object through a buffer device of adjustable level, or to convert the signal level sent by communication object into the level standard needed by USB to UART chip, to realize communication interaction between USB interface of computer and UART serial port of communication object. However, this method can only realize data transmission between the UART and the PC, and cannot perform communication between the UARTs.
In order to solve the problems in the prior art, the invention provides a system for realizing communication between UARTs.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to solve the problems in the prior art, the invention provides a system for realizing communication between UARTs, comprising:
the first UART interface module comprises a first UART0 interface module and a first UART1 interface module, the first UART0 interface module is connected with a first terminal device, and the first UART1 interface module comprises a data receiving pin;
a second UART interface module including a second UART1 interface module, the second UART1 interface module including a data transmitting pin, the data receiving pin of the first UART1 interface module being connected to the data transmitting pin of the second UART1 interface module, so that the first UART interface module receives data from the second UART interface module.
Illustratively, the first terminal device includes a verification module, which receives the data transmitted from the first UART0 interface module and processes the data to verify whether the data in the second UART interface module is consistent with the data received by the first UART interface module through the data receiving pin of the first UART1 interface module.
For example, the first UART interface module further includes a first data conversion module, the first data conversion module converts data received by the first UART interface module through the data receiving pin of the first UART1 interface module into converted data, and the verification module receives and processes the converted data transmitted by the first UART0 interface module to perform the verification.
Illustratively, the second UART interface module includes a second data conversion module, the second UART interface module converts data in the second UART interface module into converted data through the second data conversion module and transmits the converted data to a data receiving pin of the first UART1 interface module in the first UART interface module through the data transmitting pin of the second UART1 interface module in the second UART interface module, and the first UART0 interface module transmits the converted data to the authentication module.
Illustratively, the verification module includes a UART-to-USB interface conversion module and a processor, the UART-to-USB interface conversion module is connected between the first UART0 interface module of the first UART interface module and the processor for transmitting the converted data to the processor, and the processor processes the converted data to perform the verification.
Illustratively, the conversion data includes data corresponding to ASCII code, the verification module further includes a display, and the processing module converts the data corresponding to ASCII code into displayable display data for display on the display, the display being configured to display the display data.
Illustratively, the first UART interface module further includes a first identification module and a second control module, the first identification module is configured to identify an operating status of the first UART interface module, the operating status includes a busy status and an idle status, and the first control module is configured to control a data receiving pin in the first UART1 interface module to receive data according to the operating status of the first UART interface module.
Illustratively, the second UART interface module further includes a second identification module and a second control module, the second identification module is configured to identify an operating status of the second UART interface module, the operating status includes a busy status and an idle status, and the second control module is configured to control a data transmission pin of the second UART1 interface module to transmit data according to the operating status of the second UART interface module.
Illustratively, the second UART interface module further includes a second UART0 interface module, and the second UART0 interface module is configured to connect to a second terminal device.
Illustratively, the first terminal device and/or the second terminal device comprise a data acquisition device.
According to the system for realizing the communication between the UARTs, the communication between the UARTs can be realized, the data verification is carried out at the processor (such as P) end, the communication between two acquisition terminals using the UARTs as interfaces is realized, and the data verification can be carried out through terminal equipment externally connected with the UARTs.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 is a schematic diagram of a system for implementing UART-to-UART communication according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a data conversion process performed by a conversion module disposed in a second UART interface module for transmitting data to a first UART interface module in a system for implementing communication between UARTs according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a process of transmitting and displaying the converted data by the first UART interface module after receiving the converted data sent by the second UART interface module in the system for implementing communication between UARTs according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
In order to thoroughly understand the present invention, a detailed description will be provided in the following description to illustrate the system for implementing communication between UARTs according to the present invention. It is apparent that the implementation of the present invention is not limited to the specific details familiar to a person skilled in the art of communication technology. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same elements are denoted by the same reference numerals, and thus the description thereof will be omitted.
Example one
In order to solve the problems in the prior art, the invention provides a system for realizing communication between UARTs, comprising:
the first UART interface module comprises a first UART0 interface module and a first UART1 interface module, the first UART0 interface module is connected with a first terminal device, and the first UART1 interface module comprises a data receiving pin;
a second UART interface module including a second UART1 interface module, the second UART1 interface module including a data transmitting pin, the data receiving pin of the first UART1 interface module being connected to the data transmitting pin of the second UART1 interface module, so that the first UART interface module receives data from the second UART interface module.
A system for implementing communication between UARTs according to the present invention will be described with reference to fig. 1, 2 and 3. Fig. 1 is a schematic structural diagram of a system for implementing communications between UARTs according to an embodiment of the present invention; FIG. 2 is a schematic diagram illustrating a data conversion process performed by a conversion module disposed in a second UART interface module for transmitting data to a first UART interface module in a system for implementing communication between UARTs according to an embodiment of the present invention; fig. 3 is a schematic diagram illustrating a process of transmitting and displaying the converted data by the first UART interface module after receiving the converted data sent by the second UART interface module in the system for implementing communication between UARTs according to an embodiment of the present invention.
As shown in fig. 1, a system for implementing communication between UARTs according to the present invention includes a first UART interface module 1 and a second UART interface module 2.
The UART interface module is a universal serial bus and is used for asynchronous communication, bidirectional communication and full duplex transmission and reception. The UART converts parallel data into serial data to be sent out, and converts received serial data into parallel data.
In the UART, in the asynchronous communication mode, the data transmission format of the asynchronous serial communication is set such that the transmission interval between two data characters is arbitrary, so that a few digits are used as spare bits before and after each data character. In the asynchronous communication mode, the same frame format must be agreed between the transmitting and receiving parties, otherwise transmission errors may be caused. The sender only sends data frames without transmitting clocks, and both the sender and the receiver must agree on the same transmission rate. Of course, the actual working rates of the two parties cannot be absolutely equal, but as long as the error does not exceed a certain limit, transmission errors cannot be caused. Asynchronous transmission is in bytes. It sends each bit in the byte in order to send serially, and at the receiving end, another UART unit reassembles each bit received back to the original byte.
For example, the UART interface module may be configured as a UART interface configured on any terminal device or a UART interface of a peripheral device on the terminal device. The data acquisition terminal comprises any instrument and the like used for acquiring data, such as electric energy metering and acquiring equipment and gas consumption acquiring equipment. The terminal device may be a general purpose computer or the like. The UART interface is often formed in the form of a chip on a circuit board having a circuit structure.
In the present invention, as shown in fig. 1, the first UART interface module 1 includes a UART0 interface module and a UART1 interface module (i.e., a first UART0 interface module and a first UART1 interface module).
The UART0 interface module is used to connect to a terminal device. Illustratively, the terminal includes a data acquisition terminal and/or a data processing terminal.
Illustratively, the data acquisition terminal comprises a meter, a controller and the like for acquiring data, such as an electric energy metering and acquiring device and a gas consumption acquiring device.
Illustratively, a data processing terminal includes a terminal for processing data, such as a data processor, including but not limited to a computer or the like.
The UART1 interface module includes a data receiving pin 12 and a data transmitting pin 11, and the data receiving pin 12 is connected to a data transmitting pin 21 of a UART1 interface module in another UART interface module (second UART interface module 2), so that the second UART interface module 2 transmits data to the data receiving pin 12 of the first UART interface module 1 through the data transmitting pin 21.
Referring to fig. 1, like the first UART interface module 1, the second UART interface module 2 also includes a UART0 interface module and a UART1 interface module (i.e., a second UART0 interface module and a second UART1 interface module), wherein the UART0 interface module is used for connecting a terminal device. Illustratively, the terminal includes a data acquisition terminal and/or a data processing terminal. The UART1 interface module of the second UART interface module 2 includes a data reception pin 22 and a data transmission pin 21.
In one example of the present invention, the data receiving pin 12 in the UART1 interface module of the first UART interface module 1 is connected to the data transmitting pin 21 of the UART1 interface module of the second UART interface module 2; the data transmitting pin 11 in the UART1 interface module of the first UART interface module 1 is connected to the data receiving pin 22 of the UART1 interface module of the second UART interface module 2. Therefore, the bidirectional data transmission and reception of the two UART interfaces are realized.
According to the invention, two UART communication interface modules (a first UART interface module 1 and a second UART interface module 2) are connected through the pins of the UART1 to realize communication between the UART interfaces, so that communication between two acquisition terminal devices can be realized.
In this embodiment, the first UART interface module 1 and the second UART interface module 2 are set as modules for transmitting and receiving data, which are only exemplary, and those skilled in the art can know that the UART interface module may also be set as a module for inquiring that the transmission is busy, the inquiry is received, and the interrupt is cleared.
In one embodiment, the first UART0 interface module related registers (U0, 0X1F80-000X) and the first UART1 interface module related registers (U1, 0X1F80-080X) in the first UART interface module 1 are only slightly different in address, and the other functions are used the same. Similarly, the registers related to the second UART0 interface module and the second UART1 interface module in the second UART interface module 2 are only slightly different in address, and other functions are the same in usage
Since transmission between the first UART interface module 1 and the second UART interface module 2 tends to be disturbed, in order to verify data transmission between UART interfaces, in the system for implementing communication between UART interfaces according to the present invention, the terminal device connected to the UART0 of the first UART interface module includes a verification module that receives data transmitted from the first UART0 interface module and processes the data to verify whether data in the second UART interface module is identical to data received by the first UART interface module through the data reception pin connection of the first UART1 interface module.
An exemplary description will be given of an authentication process for data transmitted between UART interfaces according to the present invention.
In one example according to the present invention, the authentication module includes a UART-to-USB interface conversion module 4 and a processor 3. The UART-to-USB interface conversion module 4 transmits the data in the first UART interface module 1 to the processor terminal through the USB interface, so that the processor terminal directly processes the data for verification.
In one example according to the present invention, the first UART0 interface module of the first UART interface module 1 transmits data corresponding to ASCII code to the verification module to cause the UART-to-USB interface conversion module 4 to transmit the data corresponding to ASCII code to the processor. An exemplary processor is a computer that translates data corresponding to the ASCII code into display data that can be displayed on a display to cause the display to display the display data.
In the above verification method, there are two implementations to make the data sent by the first UART0 interface module to the verification module be data corresponding to ASCII code.
The first implementation mode comprises the following steps: the first UART interface module 1 includes a first data conversion module 13 therein, and the first data conversion module 13 converts data from the second UART interface module 2 received by the first UART interface module 1 through the data receiving pin 12 of the first UART1 interface module into conversion data, which is data corresponding to ASCII code.
The second implementation mode comprises the following steps: the second UART interface module 2 includes a second data conversion module 23 therein, the second UART interface module 23 converts the data in the second UART interface module 2 into conversion data through the second data conversion module 23 and transmits the conversion data to the data receiving pin 12 of the first UART1 interface module in the first UART interface module 1 through the data transmitting pin 21 of the second UART1 interface module in the second UART interface module 2, and the first UART0 interface module 1 transmits the conversion data to the verification module.
In the above two manners, a data conversion module is arranged in the first UART interface module 1 or the second UART interface module 2, and after or before the data in the second UART interface module 2 is sent through the data sending pin 21 of the second UART1 interface module in the second UART interface module 2, the data is converted into converted data, so as to implement the verification manner. The above two ways can achieve the verification of the data transmission between the UART1 interfaces, and are not limited herein.
For example, in one verification example of the present invention, the second UART interface module 2 is provided on an a board (a circuit board in which a circuit structure is arranged), the second UART0 interface module in the second UART interface module 2 is connected to the second computer terminal device 6 through the second UART-to-USB interface conversion module 5, the first UART interface module 1 is provided on a B board (a circuit board in which a circuit structure is arranged), the first UART0 interface module in the first UART interface module 1 is connected to the first computer terminal device 3 through the first UART-to-USB interface conversion module 4; the connection according to the invention is implemented between the first UART interface module 1 and the second UART interface module 2, namely: connecting the data receiving pin 12 in the UART1 interface module of the first UART interface module 1 to the data transmitting pin 21 of the UART1 interface module of the second UART interface module 2; the data transmitting pin 11 in the UART1 interface module of the first UART interface module 1 is connected to the data receiving pin 22 of the UART1 interface module of the second UART interface module 2.
By inputting data, for example, the character string "0 xA1B23C 4D", into the second computer terminal 6, the first computer terminal displays "A1B 23C 4D", so that the verification module (including the first UART-to-USB interface conversion module 4 and the first computer terminal 3) verifies that the data in the second UART interface module is consistent with the data received by the first UART interface module through the data receiving pin connection, thereby verifying that accurate transmission of data is achieved between the first UART interface module 1 and the second UART interface module 2.
It should be understood that the terminal device connected to the first UART0 interface module of the first UART interface module may also be specially configured to display the data received by the first UART interface module through the data receiving pin connection, and may also be in the form of the first UART-to-USB interface conversion module 4 and the first computer terminal device 3, and the application thereof is not limited herein.
Illustratively, in an embodiment of the present invention, the data conversion module converts the hexadecimal data in the second UART interface module 2 into ASCII code, and the exemplary conversion process is as follows:
when the hexadecimal number is less than 0xA,
the inputs 0x1-0x9 may be understood in decimal terms as: (1-9) +48 ═ 49-57, corresponding to hexadecimal: (0x1-0x9) +0x30 ═ 0x31-0x39, and (0x31-0x39) corresponds to ASCII code of (1-9);
② when the hexadecimal number is equal to or greater than 0xA,
the inputs 0xA-0xF may be understood in decimal terms as: (10-15) +55 (65-70), corresponding to hexadecimal scale: (0xA-0xF) +0x37 ═ 0x41-0x46, and (0x41-0x46) corresponds to ASCII code (a-F).
Referring to table 1, a corresponding list of hexadecimal and ASCII codes is shown.
TABLE 1 hexadecimal and ASCII codes
| Hexadecimal system | ASCII | Hexadecimal | ASCII |
| 0x30 | |||
| 0 | 0x38 | 8 | |
| |
1 | 0x39 | 9 |
| 0x32 | 2 | | A |
| 0x33 | |||
| 3 | 0x42 | B | |
| 0x34 | 4 | 0x43 | C |
| 0x35 | 5 | | D |
| 0x36 | |||
| 6 | 0x45 | E | |
| 0x37 | 7 | 0x46 | F |
For example, in this embodiment, the first URAT interface module and the second URAT interface module use MIPS general registers. Referring to table 2, a usage convention for MIPS general registers is shown.
TABLE 2 MIPS general register usage conventions
For example, in the case of using a 32-bit register, when the conversion module 23 is disposed in the second UART interface module 2, so that the data in the second UART interface module 2 needs to be transmitted in 8 times before being transmitted through the data transmission pin 21 of the second UART1 interface module in the second UART interface module 2. Because hexadecimal digits are input in a computer, only the corresponding ASCII code can be output. The ASCII code is single character, and only after 8 times of bit-by-bit transmission, the hexadecimal number input by each bit can be consistent with the printed ASCII code of the single character. The conversion is performed by first logically shifting the incoming data to the left (right) so that the single hexadecimal number to be transmitted is at the lowest bit of the register and all other bits of the register are zeros, and then comparing it to 0xA and converting it.
For example, in the case of using a 32-bit register, when a conversion module is disposed in the first UART interface module 1, so that the data in the second UART interface module 2 can be transmitted four times with the highest efficiency in the process of conversion after being transmitted through the data transmission pin 21 of the second UART1 interface module in the second UART interface module 2, the received data is two-bit hexadecimal numbers, each time the received character is logically shifted left (right), so that the single hexadecimal number to be output is located at the lowest bit of the register, and the other bits of the register are all zero, and then the received data is compared with 0xA and converted.
In the following, taking as an example the process of providing the conversion module 23 in the second UART interface module 2 to convert the data in the second UART interface module 2 before the data is transmitted through the data transmission pin 21 of the second UART1 interface module in the second UART interface module 2, the verification process of the invention will be further described in detail.
A conversion module 23 is disposed in the second UART interface module 2, as shown in fig. 2, which shows a schematic process diagram of performing data conversion by the conversion module. The hexadecimal digits written into the register are converted to be suitable for output, the data are sent through a second UART1 interface module in the second UART interface module 2, the characters received each time are subjected to logic left (right) shift, the single hexadecimal digit to be output is located at the lowest bit of the register, and other bits of the register are all zero, and then the hexadecimal digits are compared with 0xA and converted.
In some cases, the peripheral UART interface module often does not have a storage function such as a cache, and after the UART interface module receives the bytes, the bytes must be read in time to avoid loss; meanwhile, when a transmission/reception byte is required, it must be determined that the UART is not in a transmission/reception busy state.
Illustratively, the first UART interface module further includes a first identification module and a second control module, the first identification module is configured to identify an operating status of the first UART interface module, the operating status includes a busy status and an idle status, and the first control module is configured to control a data receiving pin in the first UART1 interface module to receive data according to the operating status of the first UART interface module.
For example, when the first UART interface module is in a busy state, the data receiving pin in the first UART1 interface module is controlled to suspend receiving data; when the first UART interface module is in the idle state, the data receiving pin in the first UART1 interface module is controlled to receive data.
Illustratively, the second UART interface module further includes a second identification module and a second control module, the second identification module is configured to identify an operating status of the second UART interface module, the operating status includes a busy status and an idle status, and the second control module is configured to control a data transmission pin of the second UART1 interface module to transmit data according to the operating status of the second UART interface module.
For example, when the second UART interface module is in a busy state, the data transmission pin in the second UART1 interface module is controlled to suspend transmitting data; when the second UART interface module is in the idle state, the data transmission pin in the second UART1 interface module is controlled to transmit data.
For example, the method for determining the working states of the first UART interface module and the second UART interface module is to determine through the value of a register:
when data is sent, firstly, whether a first UART interface module is ready for sending data is judged, and the value of a register (UART _ BUSY) reflects the using state of the UART interface module: if the value is 1, the data is sent, the second UART interface module is in a busy state, and data sending operation cannot be executed; if the value is 0, it indicates that the second UART interface module is in an idle state, the operation of transmitting data may be executed, and the transmitted data is written into a register [ UART _ WRITE ].
When receiving DATA, judging whether a first UART interface module is ready to receive the DATA, if the value of a register (UART _ DATA _ RDY) is 1, indicating that the DATA can be received, and if the value of a register for storing the DATA is (UART _ READ); if 0, no data acceptance operation is performed.
Referring to fig. 3, a schematic diagram of a process of displaying data received from the second UART interface module 2 on a display at the first UART interface module 1 is shown, wherein data is read from the data receiving pins 12 through the first UART1 interface module of the first UART interface module 1 and is transmitted to the PC side through the first UART0 interface module, and data to be printed is displayed on the PC side display.
Therefore, the character string 'A1B 23C 4D' is transmitted by the data transmitting pin of the second UART1 interface module of the second UART interface module and is received by the data receiving pin of the first UART1 interface module of the first UART interface module, and then the data is transmitted to the PC terminal display device for display by the first UART0 interface module of the first UART interface module, and the character string 'A1B 23C 4D' printed in a circulating way is obtained, so that the data transmission and verification among UART interfaces are realized.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another device, or some features may be omitted, or not executed.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the invention and aiding in the understanding of one or more of the various inventive aspects. However, the method of the present invention should not be construed to reflect the intent: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
The above description is only for the specific embodiment of the present invention or the description thereof, and the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the protection scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A system for implementing communication between UARTs, comprising:
the first UART interface module comprises a first UART0 interface module and a first UART1 interface module, the first UART0 interface module is connected with a first terminal device, and the first UART1 interface module comprises a data receiving pin;
a second UART interface module including a second UART1 interface module, the second UART1 interface module including a data transmitting pin, the data receiving pin of the first UART1 interface module being connected to the data transmitting pin of the second UART1 interface module, so that the first UART interface module receives data from the second UART interface module.
2. The system of claim 1, wherein the first terminal device comprises a verification module, and the verification module receives and processes the data transmitted from the first UART0 interface module to verify whether the data in the second UART interface module is consistent with the data received by the first UART interface module through the data receiving pin of the first UART1 interface module.
3. The system of claim 2, wherein the first UART interface module further comprises a first data conversion module, the first data conversion module converts data received by the first UART interface module through the data receiving pin of the first UART1 interface module into converted data, and the verification module receives and processes the converted data transmitted by the first UART0 interface module for the verification.
4. The system of claim 2, wherein the second UART interface module includes a second data conversion module, the second UART interface module converts the data in the second UART interface module into converted data through the second data conversion module and transmits the converted data to the data receiving pin of the first UART1 interface module in the first UART interface module through the data transmitting pin of the second UART1 interface module in the second UART interface module, and the first UART0 interface module transmits the converted data to the verification module.
5. The system of claim 3 or 4, wherein the validation module comprises a UART-to-USB interface conversion module and a processor, the UART-to-USB interface conversion module is connected between the first UART0 interface module of the first UART interface module and the processor for transmitting the converted data to the processor, and the processor processes the converted data for the validation.
6. The system of claim 5, wherein the converted data includes data corresponding to ASCII code, the verification module further comprises a display, and the processing module converts the data corresponding to ASCII code into displayable display data for displaying on the display, wherein the display is configured to display the display data.
7. The system of claim 1, wherein the first UART interface module further comprises a first identification module and a second control module, the first identification module is configured to identify an operating status of the first UART interface module, the operating status includes a busy status and an idle status, and the first control module is configured to control a data receiving pin of the first UART1 interface module to receive data according to the operating status of the first UART interface module.
8. The system of claim 1, wherein the second UART interface module further comprises a second identification module and a second control module, the second identification module is configured to identify an operating status of the second UART interface module, the operating status includes a busy status and an idle status, and the second control module is configured to control a data transmission pin of the second UART1 interface module to transmit data according to the operating status of the second UART interface module.
9. The system of claim 1, wherein the second UART interface module further comprises a second UART0 interface module, and the second UART0 interface module is configured to connect to a second terminal device.
10. The system of claim 9, wherein the first terminal device and/or the second terminal device comprises a data collection device.
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