CN114595182B - Bidirectional conversion circuit and method for multiple communication serial ports - Google Patents

Bidirectional conversion circuit and method for multiple communication serial ports Download PDF

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CN114595182B
CN114595182B CN202210207651.2A CN202210207651A CN114595182B CN 114595182 B CN114595182 B CN 114595182B CN 202210207651 A CN202210207651 A CN 202210207651A CN 114595182 B CN114595182 B CN 114595182B
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serial port
data
module
fifo
decoder
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CN114595182A (en
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渠晓辉
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Zhuhai Shengsheng Microelectronic Co ltd
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Zhuhai Shengsheng Microelectronic Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-communication serial port bidirectional conversion circuit and a method thereof are provided, the circuit comprises: the device comprises a selection controller module, an FIFO module, a first serial port compiling module, a second serial port compiling module and a decoder selection module; the selection controller module comprises an encoder selection module and an FIFO configuration selection module; the FIFO module consists of a plurality of FIFO units; the decoder selection module comprises a first decoder selection unit and a second decoder selection unit; the method comprises the following steps: setting communication requirements of software according to conversion requirements of serial port data, receiving serial data to be converted by a decoder selection module, automatically identifying a serial form, determining a conversion form and a transmission direction of the data by the decoder selection module in cooperation with an encoder selection module, and matching an encoder and a decoder for data conversion; the FIFO configuration selection module can set the allocation of data storage and transmission of the FIFO unit; and the automatic data conversion of three serial port forms of UART, I2C and SPI is realized.

Description

Bidirectional conversion circuit and method for multiple communication serial ports
Technical Field
The invention relates to the technical field of electronics, in particular to a multi-communication serial port bidirectional conversion circuit and a method.
Background
In the electronic field, UART, I2C and SPI are used as communication serial ports, and are generally applied to various MCU chips for data transmission due to their advantages such as stability and normalization, so to speak, they are an indispensable part of MCU chips; the FPGA verification is one of important verification means in the chip development process, and as the FPGA verification is closer to the real running environment of a chip, and is cheaper than other verification devices and more convenient to use, the qualification of each index of the chip can be ensured by means of the FPGA verification before Tape-out of most chip design companies;
in the process of FPGA verification, when data transmission needs to be carried out between the same chip or different chips, a chip design company may not simultaneously contain the three types of communication interface modules due to the consideration of the problem of chip development cost (area and power consumption), but data exchange needs to be carried out between different serial port modules under a certain specific verification condition, so that the problem of communication serial port non-adaptation is caused, at this time, a verifier usually uses a serial port tool and the chip to carry out data receiving and sending at a pc end for assisting verification, but because the verifier is not a real hardware environment and has certain ideality, the verification result is not reliable, so that the precision problem of design cannot be accurately verified, and the verification result may have certain deviation.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a multi-communication serial port bidirectional conversion circuit and a method, and aims to solve the problem of data conversion of three communication serial ports of UART, I2C and SPI.
In order to solve the problems, the technical scheme adopted by the invention is as follows:
a multi-communication serial port bidirectional conversion circuit comprises a selection controller module, an FIFO module, a first serial port compiling module, a second serial port compiling module and a decoder selection module; the selection controller module comprises an encoder selection module and an FIFO configuration selection module; the FIFO module consists of a plurality of FIFO units; the decoder selection module comprises a first decoder selection unit and a second decoder selection unit; the selection controller module is connected with the first serial port compiling module and the second serial port compiling module through the encoder selection module, and the selection controller module is connected with the FIFO units of the FIFO module through the FIFO configuration selection module.
Furthermore, the first serial port compiling module consists of a first SPI coder and decoder, a first I2C coder and decoder and a first UART coder and decoder; the second serial port compiling module consists of a second SPI coder and decoder, a second I2C coder and decoder and a second UART coder and decoder; the FIFO module is provided with three FIFO units, namely a first FIFO unit, a second FIFO unit and a third FIFO unit; the transmission data types among the encoding and decoding device of the first serial port compiling module, the encoding and decoding device of the second serial port compiling module, the three FIFO units of the FIFO module and the decoding device selecting module comprise SPI data, I2C data and UART data.
The first decoder selection unit is connected with the first chip through an MOSI/MOSO serial port, an SDA serial port, an RX serial port and a TX serial port; the second decoder selection unit is connected with the second chip through an MOSI/MOSO serial port, an SDA serial port, an RX serial port and a TX serial port; the first decoder selection unit is connected with a first SPI codec, a first I2C codec and a first UART codec of the first serial port codec module; and the second decoder selection unit is connected with a second SPI codec, a second I2C codec and a second UART codec of the second serial port codec module.
The FIFO module is connected with the first serial port compiling module and the second serial port compiling module; three units of a first FIFO unit, a second FIFO unit and a third FIFO unit of the FIFO module are all connected with a first SPI coder, a first SPI decoder, a first I2C coder, a first UART coder and a first UART decoder; and three units of a first FIFO unit, a second FIFO unit and a third FIFO unit of the FIFO module are all connected with a second SPI coder and decoder, a second I2C coder and decoder and a second UART coder and decoder.
A multi-communication serial port bidirectional conversion method, a multi-communication serial port bidirectional conversion circuit carries out mutual conversion transmission of three data of UART, I2C and SPI;
the serial port data of treating serial port form conversion is sent by first chip, and the circuit carries out serial port form conversion to serial port data, and the serial port data after the second chip receives the conversion, its step is:
a first decoder selecting unit of the decoder selecting module receives serial port data sent by a data serial port end of a first chip, identifies a serial port form of the serial port data, and automatically selects a serial port form corresponding to a first SPI, I2C and UART decoder; setting and selecting a conversion requirement of a serial port form of the controller module through software; the encoder selection module configures a second SPI, an I2C and a UART encoder according to conversion requirements and is matched with the decoder selection module to determine the transmission direction of data; the FIFO configuration selection module configures data storage and transmission of a plurality of FIFO units of the FIFO module according to the conversion requirement and the transmission direction of data;
the first SPI, I2C and UART decoder receives the serial port data sent by the first decoder selection module, converts the serial port data into uniform standard binary number data and sends the uniform standard binary number data to the FIFO module; the FIFO module stores the binary number data and sends the binary number data to the corresponding second SPI, I2C and UART encoders; the second SPI, I2C and UART encoder converts the system number data into corresponding serial port data and sends the serial port data to the second decoder selection unit; and the second decoder selection unit sends the serial port data to the second chip.
The second chip sends serial port data to be converted in serial port form, the circuit converts the serial port form of the serial port data, the first chip receives the converted serial port data, and the method comprises the following steps:
a second decoder selecting unit of the decoder selecting module receives serial port data sent by a data serial port of a second chip, identifies the serial port form of the serial port data, and automatically selects a serial port form corresponding to a second SPI, I2C and UART decoder; setting and selecting a conversion requirement of a serial port form of the controller module through software; the encoder selection module configures a first SPI, an I2C and a UART encoder according to conversion requirements and is matched with the decoder selection module to determine the transmission direction of data; the FIFO configuration selection module configures data storage and transmission of a plurality of FIFO units of the FIFO module according to the conversion requirement and the transmission direction of the data;
the second SPI, I2C and UART decoder receives the serial port data sent by the second decoder selection module, converts the serial port data into uniform standard binary number data and sends the uniform standard binary number data to the FIFO module; the FIFO module stores the binary number data and sends the binary number data to corresponding first SPI, I2C and UART encoders; the first SPI, I2C and UART coder converts the system number data into corresponding serial port data and sends the serial port data to the first decoder selecting unit; the first decoder selection unit sends serial port data to the first chip.
Further, the FIFO configuration selection module configures the binary numerical data to any one or more FIFO units in non-data transmission for data storage and transmission according to the conversion requirement and the transmission direction of the data and the storage depth and the transmission state of each FIFO unit of the FIFO module;
when the first FIFO unit/the second FIFO unit/the third FIFO unit carry out serial port form conversion of serial port data from the first chip to the second chip according to the configuration information of the FIFO configuration selection module, one or more FIFO units receive the data sent by the first SPI/I2C/UART compiler, store the data according to the storage depth of each FIFO unit, and send the stored data to the second SPI, I2C and UART compiler; when the second chip converts the serial port form of the serial port data to the first chip, one or more FIFO units receive the data sent by the second SPI, I2C and UART compiler, store the data according to the storage depth of each FIFO unit, and send the stored data to the first SPI, I2C and UART compiler.
Furthermore, in the FIFO configuration selection module, a user can configure the data input bit width, the storage depth, and the data output bit width of each FIFO unit in the FIFO module through software according to the size of the actual transmission data frame number and the bit width of the data.
Compared with the prior art, the invention has the beneficial effects that: the serial port form conversion of the serial port data is set through software, the encoder selection module automatically identifies the serial port form of the serial port data when receiving the serial port data, selects a corresponding decoder, matches the encoder corresponding to the serial port form conversion through the encoder selection module and determines the transmission direction of the data, and automatic decoding of the decoder and automatic encoding of the encoder are achieved; the FIFO configuration selection module can set the storage depth and the data bit width of each FIFO unit of the FIFO module through software according to the data volume of data transmission so as to be compatible with systems with different bit numbers such as 8 bits, 16 bits, 32 bits and the like; meanwhile, the FIFO configuration selection module can automatically configure one or more FIFO units in a non-transmission state for data storage and transmission according to the storage depth and the transmission state of each FIFO unit, and each FIFO unit can also independently transmit data, so that the data storage and transmission efficiency is greatly improved.
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required to be used in the embodiments will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a circuit structure of an embodiment of the present invention.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure of the present disclosure. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes in detail may be made without departing from the spirit of the disclosure, from various aspects and applications of the disclosure. It should be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
A multi-communication serial port bidirectional conversion circuit comprises a selection controller module, an FIFO module, a first serial port compiling module, a second serial port compiling module and a decoder selection module; the selection controller module comprises an encoder selection module and an FIFO configuration selection module; the FIFO module consists of a plurality of FIFO units; the decoder selection module comprises a first decoder selection unit and a second decoder selection unit; the first serial port compiling module consists of a first SPI coder and decoder, a first I2C coder and decoder and a first UART coder and decoder; the second serial port compiling module consists of a second SPI coder and decoder, a second I2C coder and decoder and a second UART coder and decoder; the FIFO module is provided with three FIFO units, namely a first FIFO unit, a second FIFO unit and a third FIFO unit;
the encoder selection module is connected with the first serial port compiling module and the second serial port compiling module; the FIFO configuration selection module is connected with the FIFO module;
the data types needing serial port form conversion between the first chip and the second chip can comprise SPI, I2C and UART; the transmission of SPI type data corresponds to MOSI/MISO serial ports of a first chip and a second chip, the transmission of I2C type data corresponds to SDA serial ports of the first chip and the second chip, and the transmission of UART type data corresponds to TX/RX serial ports of the first chip and the second chip;
the first decoder selection unit is connected with the first chip through an MOSI/MISO serial port, an SDA serial port, an RX serial port and a TX serial port; the second decoder selection unit is connected with the second chip through an MOSI/MISO serial port, an SDA serial port, an RX serial port and a TX serial port;
the first decoder selection unit is correspondingly connected with a decoder and an encoder of the first serial port compiling module according to a serial port form connected with the first chip; the first SPI coder and decoder is connected with the MOSI/MISO serial port of the first chip through a first decoder selection unit; the first I2C coder and decoder is connected with the SDA serial port of the first chip through the first decoder selection unit; the first UART coder and decoder is connected with the RX and TX serial ports of the first chip through a first decoder selection unit;
the second decoder selection unit is correspondingly connected with a decoder and an encoder of the second serial port compiling module according to the serial port form connected with the second chip; the second SPI coder and decoder is connected with the MOSI/MISO serial port of the second chip through a second decoder selection unit; the second I2C coder and decoder is connected with the SDA serial port of the second chip through a second decoder selection unit; the second UART coder and decoder is connected with the RX and TX serial ports of the second chip through a second decoder selection unit;
the FIFO module is connected with the first serial port compiling module and the second serial port compiling module; three units of a first FIFO unit, a second FIFO unit and a third FIFO unit of the FIFO module are all connected with a first SPI coder, a first SPI decoder, a first I2C coder, a first UART coder and a first UART decoder; and three units of a first FIFO unit, a second FIFO unit and a third FIFO unit of the FIFO module are all connected with a second SPI coder, a second SPI decoder, a second I2C coder, a second UART coder and a second UART decoder.
A multi-communication serial port bidirectional conversion method, a multi-communication serial port bidirectional conversion circuit carries out mutual conversion transmission of three data of UART, I2C and SPI;
the method comprises the steps that serial port data to be converted in a serial port form are sent by a first chip, wherein the serial port data in the SPI serial port form are sent by an MOSI/MISO serial port of the first chip, the serial port data in the I2C serial port form are sent by an SDA serial port of the first chip, and the serial port data in the UART serial port form are sent by a TX/RX serial port of the first chip; the circuit carries out serial port form conversion on serial port data, and the second chip receives the converted serial port data, and the method comprises the following steps:
the serial port data processing method comprises the steps that a first decoder selecting unit of a decoder selecting module receives serial port data sent by a data serial port end of a first chip and identifies serial port forms of the serial port data, the serial port forms comprise three types of SPI/I2C/UART, and the decoder selecting module automatically selects the serial port forms corresponding to first SPI, I2C and UART decoders;
setting and selecting a conversion requirement of a serial port form of the controller module through software; with SPI, I2C and UART's serial ports form two liang of conversions respectively, its conversion demand includes: six conversion requirements of converting SPI into I2C, converting SPI into UART, converting I2C into SPI, converting I2C into UART, converting UART into SPI and converting UART into I2C are provided; the encoder selection module configures a second SPI, I2C and UART encoder of a second serial port compiling module according to conversion requirements; the encoder selection control module is matched with the decoder selection module to determine the transmission direction of the data, namely, the decoder of the first serial port compiling module and the encoder of the second serial port compiling module are determined according to one of six conversion requirements, and then the conversion form and the transmission direction of the serial port data are determined;
the FIFO configuration selection module configures data storage and transmission of a plurality of FIFO units of the FIFO module according to one of the six conversion requirements and the transmission direction of data;
the first SPI, I2C and UART decoder receives the serial port data sent by the first decoder selection module and converts the serial port data into unified binary number data, wherein the unified standard binary number data comprise 8-bit, 16-bit, 32-bit and other common binary number data types; the first SPI, I2C and UART decoder transmits the converted binary number data to the FIFO module; the FIFO module stores the binary number data and sends the binary number data to corresponding second SPI, I2C and UART encoders; the second SPI, I2C and UART encoder converts the system number data into serial port data in a serial port form corresponding to the conversion requirement and sends the serial port data to the second decoder selecting unit; and the second decoder selection unit sends the serial port data to the second chip through the corresponding serial port.
The serial port data to be converted in the serial port form is sent by the second chip, wherein the serial port data in the SPI serial port form is sent by an MOSI/MISO serial port of the second chip, the serial port data in the I2C serial port form is sent by an SDA serial port of the second chip, and the serial port data in the UART serial port form is sent by a TX/RX serial port of the second chip; the circuit carries out serial port form conversion to serial port data, and first chip receives serial port data after the conversion, and its step is:
a second decoder selecting unit of the decoder selecting module receives serial port data sent by a data serial port of a second chip and identifies serial port forms of the serial port data, wherein the serial port forms comprise three types of SPI/I2C/UART, and the decoder selecting module automatically selects the serial port forms corresponding to second SPI, I2C and UART decoders;
setting and selecting a conversion requirement of a serial port form of the controller module through software; the serial port forms of the SPI, the I2C and the UART are converted pairwise respectively, and the conversion requirements comprise: six conversion requirements of converting SPI into I2C, converting SPI into UART, converting I2C into SPI, converting I2C into UART, converting UART into SPI and converting UART into I2C are provided; the encoder selection module configures a first SPI, I2C and UART encoder of the first serial port compiling module according to conversion requirements; the encoder selection control module is matched with the decoder selection module to determine the transmission direction of the data, namely, the decoder of the second serial port compiling module and the encoder of the first serial port compiling module are determined according to one of six conversion requirements, and then the conversion form and the transmission direction of the serial port data are determined;
the FIFO configuration selection module configures data storage and transmission of a plurality of FIFO units of the FIFO module according to one of the six conversion requirements and the transmission direction of data;
the second SPI, I2C and UART decoder receives the serial port data sent by the second decoder selection module and converts the serial port data into unified binary number data, wherein the unified standard binary number data comprise common binary number data types such as 8 bits, 16 bits, 32 bits and the like; the second SPI, I2C and UART decoder transmits the converted binary number data to the FIFO module; the FIFO module stores the binary number data and sends the binary number data to corresponding first SPI, I2C and UART encoders; the first SPI, I2C and UART encoder converts the system number data into serial port data in a serial port form corresponding to the conversion requirement and sends the serial port data to the first decoder selecting unit; and the first decoder selection unit sends the serial port data to the first chip through the corresponding serial port.
Specifically, in the encoding and decoding processes of the first serial port compiling module and the second serial port compiling module, the first SPI decoder converts serial port data of the MOSI serial port of the first chip into binary number data; the first SPI encoder sends the converted serial port data to the MISO serial port of the first chip; the first I2C decoder converts serial port data of an SDA serial port of the first chip into binary number data; the first I2C encoder sends the converted serial port data to an SDA serial port of the first chip; the first UART decoder converts serial port data of a TX serial port of the first chip into system number data; the first UART encoder sends the converted serial port data to an RX serial port of the first chip; the second SPI decoder converts serial port data of the MOSI serial port of the second chip into binary number data; the second SPI encoder sends the converted serial port data to the MISO serial port of the second chip; the second I2C decoder converts serial port data of the SDA serial port of the second chip into binary number data; the second I2C encoder sends the converted serial port data to an SDA serial port of a second chip; the second UART decoder converts serial port data of a TX serial port of the second chip into binary number data; and the second UART encoder transmits the converted serial port data to an RX serial port of a second chip.
And in the data transmission process from the second SPI, I2C and UART decoder of the second serial port compiling module to the first SPI, I2C and UART encoder of the first serial port compiling module, the first FIFO unit/the second FIFO unit/the third FIFO unit of the FIFO module stores data of the binary number.
Specifically, in the FIFO configuration selection module, a user can configure, by software, a data input bit width, a storage depth, and a data output bit width of each FIFO unit in the FIFO module according to the size of the actual transmission data frame number and the bit width of the data; meanwhile, the FIFO configuration selection module configures the binary numerical data to any one or more FIFO units in non-data transmission for data storage and transmission according to the conversion requirement set by software and the transmission direction of the data and the storage depth and the transmission state of each FIFO unit of the FIFO module;
the first FIFO unit, the second FIFO unit and the third FIFO unit are three independent data storage and transmission units, one FIFO unit can only receive one transmission data and send one transmission data at the same time, and meanwhile, the three FIFO units can simultaneously and independently transmit three groups of data.
The first/second/third FIFO elements select the configuration information of the module according to the FIFO configuration, such as: the method comprises the following steps that a first chip sends SPI serial port data, a second chip receives I2C serial port data as an example, the first chip sends the SPI serial port data to a first decoder selecting unit of a decoder selecting module through an MOSI serial port, the first decoder selecting unit automatically identifies the serial port form of the serial port data and sends the serial port data to a first SPI decoder of a first serial port compiling module, and meanwhile, an encoder selecting module is matched with the decoder selecting module to determine a second I2C encoder of the second serial port compiling module as a compiling end of the data and determine the transmission direction of the data; the FIFO configuration selection module automatically identifies that a first FIFO unit and a second FIFO unit of the FIFO module are in a non-data transmission transition state, and configures the first FIFO unit and the second FIFO unit as data storage units according to the data volume of transmission data and the storage depth of each FIFO unit; the first SPI decoder converts SPI serial data into 16-system numerical data, the first FIFO unit and the second FIFO unit receive the 16-system numerical data output by the first SPI decoder, sequentially store the 16-system numerical data according to the storage depth, and sequentially send the 16-system numerical data to the second I2C encoder according to the storage and transmission protocols of the FIFOs; the second I2C encoder receives the 16-system numerical data sent by the first FIFO unit and the second FIFO unit, converts the 16-system numerical data into I2C serial port data and sends the I2C serial port data to the second decoder selection unit; the second decoder selection unit identifies the serial port form of the serial port data according to the received I2C serial port data and sends the I2C serial port data to the SDA serial port of the second chip; the second chip receives I2C serial port data through the SDA serial port; and completing the serial port form conversion of the serial port data.
The invention provides a multi-communication serial port bidirectional conversion circuit and a method, serial port form conversion of serial port data is set through software, an encoder selection module automatically identifies the serial port form of the serial port data when receiving the serial port data, a corresponding decoder is selected, the encoder selection module is matched with an encoder corresponding to the serial port form conversion and the transmission direction of the data is determined, and automatic decoding of the decoder and automatic encoding of the encoder are realized; the FIFO configuration selection module can set the storage depth and the data bit width of each FIFO unit of the FIFO module through software according to the data volume of data transmission so as to be compatible with systems with different bit numbers such as 8 bits, 16 bits, 32 bits and the like; meanwhile, the FIFO configuration selection module can automatically configure one or more FIFO units in a non-transmission state for data storage and transmission according to the storage depth and the transmission state of each FIFO unit, and each FIFO unit can also independently transmit data, so that the data storage and transmission efficiency is greatly improved.
The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are within the protection scope of the present invention.

Claims (6)

1. The utility model provides a two-way converting circuit of many communication serial ports which characterized in that: the device comprises a selection controller module, an FIFO module, a first serial port compiling module, a second serial port compiling module and a decoder selection module; the selection controller module comprises an encoder selection module and an FIFO configuration selection module; the FIFO module consists of a plurality of FIFO units; the decoder selection module comprises a first decoder selection unit and a second decoder selection unit; the selection controller module is connected with the first serial port compiling module and the second serial port compiling module through the encoder selection module, and the selection controller module is connected with a plurality of FIFO units of the FIFO module through the FIFO configuration selection module;
the first serial port compiling module consists of a first SPI coder and decoder, a first I2C coder and decoder and a first UART coder and decoder; the second serial port compiling module consists of a second SPI coder and decoder, a second I2C coder and decoder and a second UART coder and decoder; the FIFO module is provided with three FIFO units, namely a first FIFO unit, a second FIFO unit and a third FIFO unit; the transmission data types among the encoding and decoding device of the first serial port compiling module, the encoding and decoding device of the second serial port compiling module, the three FIFO units of the FIFO module and the decoding device selecting module comprise SPI data, I2C data and UART data;
the first decoder selection unit is connected with the first chip through an MOSI/MOSO serial port, an SDA serial port, an RX serial port and a TX serial port; the second decoder selection unit is connected with the second chip through an MOSI/MOSO serial port, an SDA serial port and RX and TX serial ports; the first decoder selection unit is connected with a first SPI codec, a first I2C codec and a first UART codec of the first serial port codec module; and the second decoder selection unit is connected with a second SPI codec, a second I2C codec and a second UART codec of the second serial port codec module.
2. The multi-communication serial port bidirectional conversion circuit according to claim 1, characterized in that: the FIFO module is connected with the first serial port compiling module and the second serial port compiling module; three units of a first FIFO unit, a second FIFO unit and a third FIFO unit of the FIFO module are all connected with a first SPI coder, a first SPI decoder, a first I2C coder, a first UART coder and a first UART decoder; and three units of a first FIFO unit, a second FIFO unit and a third FIFO unit of the FIFO module are all connected with a second SPI coder, a second SPI decoder, a second I2C coder, a second UART coder and a second UART decoder.
3. A multi-communication serial port bidirectional conversion method is characterized in that: the multi-communication serial port bidirectional conversion method adopts the multi-communication serial port bidirectional conversion circuit of any one of claims 1 to 2: the multi-communication serial port bidirectional conversion circuit performs mutual conversion and transmission of three data, namely UART, I2C and SPI;
the serial port data of treating serial port form conversion is sent by first chip, and the circuit carries out serial port form conversion to serial port data, and the serial port data after the second chip receives the conversion, its step is:
a first decoder selecting unit of the decoder selecting module receives serial port data sent by a data serial port end of a first chip, identifies the serial port form of the serial port data, and automatically selects a serial port form corresponding to a first SPI, I2C and UART decoder;
setting and selecting a conversion requirement of a serial port form of the controller module through software; the encoder selection module configures a second SPI, an I2C and a UART encoder according to conversion requirements and is matched with the decoder selection module to determine the transmission direction of data;
the FIFO configuration selection module configures data storage and transmission of a plurality of FIFO units of the FIFO module according to the conversion requirement and the transmission direction of data;
the first SPI, I2C and UART decoder receives serial data sent by the first decoder selection module, converts the serial data into binary data with unified standard and sends the binary data to the FIFO module; the FIFO module stores the binary number data and sends the binary number data to corresponding second SPI, I2C and UART encoders; the second SPI, I2C and UART encoder converts the system number data into corresponding serial port data and sends the serial port data to the second decoder selection unit; and the second decoder selection unit sends the serial port data to the second chip.
4. The method of claim 3, wherein the method comprises the following steps:
the second chip sends serial port data to be converted in serial port form, the circuit converts the serial port form of the serial port data, the first chip receives the converted serial port data, and the method comprises the following steps:
a second decoder selecting unit of the decoder selecting module receives serial port data sent by a data serial port of a second chip, identifies the serial port form of the serial port data, and automatically selects a serial port form corresponding to a second SPI, I2C and UART decoder;
setting and selecting a conversion requirement of a serial port form of the controller module through software; the encoder selection module configures a first SPI, an I2C and a UART encoder according to conversion requirements and is matched with the decoder selection module to determine the transmission direction of data;
the FIFO configuration selection module configures data storage and transmission of a plurality of FIFO units of the FIFO module according to the conversion requirement and the transmission direction of the data;
the second SPI, I2C and UART decoder receives the serial port data sent by the second decoder selection module, converts the serial port data into uniform standard binary number data and sends the uniform standard binary number data to the FIFO module; the FIFO module stores the binary number data and sends the binary number data to corresponding first SPI, I2C and UART encoders; the first SPI, I2C and UART coder converts the system number data into corresponding serial port data and sends the serial port data to the first decoder selecting unit; the first decoder selection unit sends serial port data to the first chip.
5. The method of claim 3 or 4, wherein the method comprises the following steps: the FIFO configuration selection module configures the binary numerical data to any one or more FIFO units in non-data transmission for data storage and transmission according to the conversion requirement and the transmission direction of the data and the storage depth and the transmission state of each FIFO unit of the FIFO module;
when the first chip performs serial port form conversion of serial port data to the second chip according to configuration information of the FIFO configuration selection module by the first FIFO unit/the second FIFO unit/the third FIFO unit, one or more FIFO units receive data sent by the first SPI/I2C/UART compiler, perform data storage according to the storage depth of each FIFO unit, and send the stored data to the second SPI, I2C and UART compiler; when the second chip converts the serial port form of the serial port data to the first chip, one or more FIFO units receive the data sent by the second SPI, I2C and UART compiler, store the data according to the storage depth of each FIFO unit, and send the stored data to the first SPI, I2C and UART compiler.
6. The method of claim 5, wherein the method comprises the following steps: in the FIFO configuration selection module, a user can configure the data input bit width, the storage depth and the data output bit width of each FIFO unit in the FIFO module through software according to the frame number of actual transmission data and the bit width of the data.
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