CN101937412A - System on chip and access method thereof - Google Patents
System on chip and access method thereof Download PDFInfo
- Publication number
- CN101937412A CN101937412A CN 201010282508 CN201010282508A CN101937412A CN 101937412 A CN101937412 A CN 101937412A CN 201010282508 CN201010282508 CN 201010282508 CN 201010282508 A CN201010282508 A CN 201010282508A CN 101937412 A CN101937412 A CN 101937412A
- Authority
- CN
- China
- Prior art keywords
- access
- osb
- slave unit
- request
- main equipment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Bus Control (AREA)
Abstract
The invention provides a system on chip and an access method thereof. The system on chip comprises an OSB (Oriented Shaving Board) as well as a master device and a slave device which are connected on the OSB, wherein the master device is used for sending an access request for requesting accessing the slave device to the OSB; the OSB is used for sending the access request from the master device to the slave device and sending the results of relevant operations performed by the slave device according to the access request to the master device; and the slave device is used for performing relevant operations according to the access request and sending the results of the relevant operations to the OSB. The simultaneous working of sufficient different bus control modules is supported on same bus system by reducing the access efficiency of each bus control module, no conflict occurs, and no instantaneous bus efficiency reduction is produced; thus, the problems of complex bus structure and difficult realization existing in relevant technologies are solved.
Description
Technical field
The present invention relates to the communications field and chip design field, in particular to a kind of general SOC (system on a chip) and bus-structured realization wherein.
Background technology
Along with improving constantly of integrated circuit technology, make SOC (SOC (system on a chip)) become possibility.Control module (CPU) and functional module (coprocessor or accommodation function module) are present on the same chip in typical SOC (system on a chip), this solves interconnecting and data transfer problem, the i.e. design of on-chip bus of in SOC (system on a chip) control module and functional module with regard to needs.These question marks are similar in the computing machine and realize control and data transfer by pci bus.In bussing technique, the bus structure that different SOC (system on a chip) or embedded type CPU adopt all are not quite similar, this depend on CPU data structure, needs realization the data transmission handling capacity and to the requirement of real-time.For example, the AHB/APB bus system of ARM company definition is in order all to guarantee the work of bus, though the bus structure of its design and communication modes versatility are stronger under different system architectures and applicable cases, but it is very complicated, and very difficult compatible with other bus system.We find that complicated asic chip has equally to bus-structured demand simultaneously, but good without comparison application bus structure.
Asic chip generally has the functional module of one or more complexity, and control module generally is in outside the sheet, and it has the control between the disparate modules of SOC chip and the demand of data transmission equally.Therefore, can be by introducing bus system so that asic chip has the advantage of the modular design the same with the SOC chip, analysis, realization, finally make the construction cycle of asic chip shorten, chip can be realized modular design, checking, the reusability grow of module.
In addition, even in the SOC chip, it all is that inefficient key-course is used that most bus is used, and complicated bus system is not brought into play real effect, but makes development difficulty increase, and consumes more hardware resource.
To sum up, in realizing process of the present invention, the inventor finds to exist at least in the prior art following problem:
1, bus structure complexity is difficult for realizing;
2, only be adapted to the SOC chip, the waste that in asic chip, is difficult to realize and can produce hardware resource;
3, structuring, universalization are not strong, much can separate the module of design verification, because bus-structured restriction is difficult to independent design, checking;
4, owing to be to be the designed bus system of SOC chip, its to the number of main control module and the arbitration after competing complicated requirement is arranged, be unfavorable for the design of general chip;
5, the conflict of main control intermodule can cause the reduction of access efficiency, and may produce faulty operation.
Summary of the invention
The present invention aims to provide a kind of SOC (system on a chip) and access method thereof, can solve the bus structure complexity that exists in the correlation technique, is difficult for the problem that realizes.
According to an aspect of the present invention, provide a kind of SOC (system on a chip), having comprised: OSB and be connected main equipment and slave unit on the OSB, wherein: main equipment, be used for will the request access slave request of access be sent to OSB; OSB is used in the future that the request of access of autonomous device is sent to slave unit, and the result of the corresponding operating that slave unit is carried out according to request of access is sent to main equipment; Slave unit is used for carrying out corresponding operating according to request of access, and the result of corresponding operating is sent to OSB.
Further, in above-mentioned SOC (system on a chip), main equipment and slave unit are the relations of equity.
Further, in above-mentioned SOC (system on a chip), also comprise: the bridge unit, be connected between main equipment and the OSB, be used in the future that the protocol conversion of the request of access of autonomous device is the OSB agreement, and the request of access that will convert the OSB agreement to is sent to OSB.
Further, in above-mentioned SOC (system on a chip), main equipment and slave unit have a plurality of respectively.
Further, in above-mentioned SOC (system on a chip), also comprise: moderator is used to receive the request of access that main equipment sends by OSB, and request of access analysis is obtained the numbering of the slave unit that will visit entrained in the request of access; And set up data channel between main equipment and the indicated slave unit that will visit of numbering.
Further, in above-mentioned SOC (system on a chip), moderator comprises: the formation arbitration modules, be used for the request of access from a plurality of main equipments is lined up formation, and analyze the numbering of the slave unit that will visit that each request of access in the formation obtains carrying in each request of access successively; The channel allocation module is used for the numbering that analysis obtains according to the formation arbitration modules, sends instruction so that slave unit activates and carries out corresponding operating to the slave unit that will visit, and set up main equipment and the slave unit that will visit between data channel.
Further, in above-mentioned SOC (system on a chip), communicate by main equipment and OSB interface between main equipment and the OSB, and communicate by slave unit and OSB interface between slave unit and the OSB; Wherein, main equipment and OSB interface comprise following at least one: address port is used to indicate the numbering of slave unit and the addressing space of slave unit; The operating result receiving port, the result who is used to indicate the corresponding operating that slave unit returns is successfully or failure; Access port is used for the enable access request, and the indication visit is read operation and/or write operation; The first output function FPDP is used for the output function data to slave unit; And the second input operation data port, be used to receive the service data that slave unit sends;
Slave unit and OSB interface comprise following at least one: the enable port is used to indicate the slave unit that will enable; The addressing space port is used to indicate the addressing space of the slave unit that will visit, and the addressing space in itself and the address port is complementary; The read/write operation port is used to enable the read/write operation of slave unit; Operating result returns port, and being used for to the result that main equipment returns corresponding operating is successfully or failure; The second output function FPDP is used for the output function data to main equipment; And the second input operation data port, be used to receive the service data that main equipment sends.
According to a further aspect in the invention, also provide a kind of bus access method of SOC (system on a chip), may further comprise the steps: main equipment will be used to ask the request of access of access slave to be sent to open shared bus OSB; OSB is sent to slave unit with request of access; Slave unit carries out corresponding operating according to request of access, and the result of corresponding operating is sent to main equipment by OSB.
Further, the main equipment request of access that will be used for access slave is sent to open shared bus OSB and comprises: main equipment sends request of access to the bridge unit; The bridge unit is the OSB agreement with the protocol conversion of request of access, and the request of access that will be converted to the OSB agreement is sent to OSB.
Further, OSB is sent to slave unit with request of access and comprises: OSB is sent to moderator with request of access; Moderator is analyzed request of access, the numbering of the slave unit that will visit that obtains carrying in the request of access; Moderator is set up the data channel between the indicated slave unit that will visit of main equipment and numbering according to numbering.
Among the present invention, because considered the difference and the identical point of SOC and asic chip fully, by the optimal design of bus having been improved greatly the structure of chip, made bus system become the important step of raising the efficiency.By proposing a kind of universal bus structure of poor efficiency, the ability that it has enough control datas to transmit, make and on same bus system, to support abundant different bus control module to work simultaneously by the access efficiency that reduces each bus control module, and can not conflict and can not produce instantaneous bus efficiency decline yet, thereby solved the bus structure complexity that exists in the correlation technique, be difficult for the problem that realizes.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 shows the structural representation of SOC (system on a chip) according to an embodiment of the invention;
Fig. 2 shows the structural representation of the SOC (system on a chip) that contains moderator according to another embodiment of the present invention;
Fig. 3 shows the position mapping synoptic diagram according to the Osbm_op_addr port of the embodiment of the invention;
Fig. 4 shows the sequential synoptic diagram according to the main equipment read operation of the embodiment of the invention;
Fig. 5 is according to the sequential synoptic diagram of the main equipment write operation of the embodiment of the invention;
Fig. 6 shows the sequential synoptic diagram according to the slave unit write operation of the embodiment of the invention;
Fig. 7 shows the sequential synoptic diagram according to the slave unit read operation of the embodiment of the invention;
Fig. 8 shows the process flow diagram according to the bus access method of the SOC (system on a chip) of the embodiment of the invention.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.
Fig. 1 shows the structural representation of SOC (system on a chip) according to an embodiment of the invention, have bus structure in this SOC (system on a chip), it comprises: OSB (Open-Shared-Bus, open shared bus) 10 and be connected main equipment 20 and slave unit 30 on this OSB 10, wherein: main equipment 20 is used for the request of access of request access slave 30 is sent to OSB 10; OSB 10, are used in the future that the above-mentioned request of access of autonomous device 20 is sent to slave unit 30, and the result of the corresponding operating that slave unit 30 is carried out according to this request of access is sent to main equipment 20; Slave unit 30 is used for carrying out above-mentioned corresponding operating according to this request of access, and the result of this corresponding operating is sent to OSB 10.
In an embodiment, considered the difference and the identical point of SOC and asic chip fully, by the optimal design of bus having been improved greatly the structure of chip, made bus system become the important step of raising the efficiency.By proposing a kind of universal bus structure of poor efficiency, the ability that it has enough control datas to transmit, make and on same bus system, to support abundant different bus control module to work simultaneously by the access efficiency that reduces each bus control module, and can not conflict and can not produce instantaneous bus efficiency decline yet, thereby solved the bus structure complexity that exists in the correlation technique, be difficult for the problem that realizes.
In the SOC (system on a chip) of the foregoing description, main equipment 20 and slave unit 30 are relations of equity.That is to say that just the equipment of definition visit is main equipment and accessed equipment is slave unit, therefore, the main equipment of an obvious equipment and the role of slave unit can change at any time, perhaps also can have these two kinds of roles simultaneously.Wherein, it should be noted that here main equipment and slave unit can be the equipment of any type.
Because main equipment and slave unit are the relations of equity, therefore when modular design, separate the arbitrarily small module of independent design, thereby it is not strong to have solved the structuring, the universalization that exist in the correlation technique, the module that much can separate design verification, because bus-structured restriction is difficult to the problem of independent design, checking, and and then strengthened the universalization of the bus of SOC (system on a chip).In addition, main equipment and slave unit are peer-to-peers, and whom does not have is the problem of master control, therefore can solve bus system in the correlation technique to the number of main control module and the arbitration after competing complicated requirement is arranged, be unfavorable for the problem of the design of general chip.
As shown in Figure 1, when reality is implemented, above-mentioned SOC (system on a chip) can also comprise a bridge unit 40, it is connected (the corresponding bridge unit of main equipment) between main equipment 20 and the OSB 10, be used in the future that the protocol conversion of the request of access of autonomous device 20 is the OSB agreement, and the request of access that will convert the OSB agreement to is sent to OSB 10.Because main equipment can be an equipment of supporting variety of protocol, in order can normally to communicate, thereby need a bridge equipment carry out protocol conversion with OSB.
Obviously, as shown in Figure 1, in above-mentioned SOC (system on a chip), can comprise a plurality of main equipments 20 and a plurality of slave unit 30.Like this, when a plurality of main equipments 20 and a plurality of slave unit 30 were connected on the OSB 10, how OSB 10 can be correctly and is worked effectively and become the problem that needs solve.Therefore, in order to address this problem, between a plurality of main equipments that can be in SOC (system on a chip) and a plurality of slave unit moderator 50 (annexation of main equipment, bridge unit, moderator and slave unit as shown in Figure 2) is set, this moderator 50 is used to receive the request of access that main equipment 20 sends by OSB 10, and this request of access analysis is obtained the numbering of the slave unit that will visit entrained in this request of access; And set up to send the main equipment of this request of access and the slave unit that will visit that the numbering that obtains is indicated between data channel.
Because moderator may receive a plurality of request of access that a plurality of main equipments send, therefore, this moderator 50 can adopt the mode of poll as its arbitration mechanism.As shown in Figure 2, this moderator 50 specifically can comprise formation arbitration modules 502 and channel allocation module 504, wherein, formation arbitration modules 502, be used for and line up formation from the request of access of a plurality of main equipments 20, analyze the numbering of the slave unit that will visit that each request of access in the formation obtains carrying in each request of access successively; Channel allocation module 504, be used for analyzing the numbering that obtains according to formation arbitration modules 502, send instruction so that this slave unit activates and carries out corresponding operating to the slave unit that will visit, and set up this main equipment and the slave unit that will visit between data channel (being this request of access distribution bus resource).
Wherein, in Fig. 2, I2C_slave (I2C slave unit), AUX-CH and MCU all are main equipments.At first, the request of access of main equipment becomes the OSB agreement by the bridge cell translation, then, through the moderator arbitration, sends at last in the corresponding slave unit.
In the SOC (system on a chip) of the foregoing description, main equipment 20 needs wait-for-response (being the result of above-mentioned corresponding operating) to return until the indicator signal of success or failure.That is, slave unit 30 indicator signal that must return success or fail is to main equipment 20.That is to say that the OSB agreement is a non-destructive agreement.The structure (promptly not supporting the situation except that the indicator signal that returns success or fail) that OSB does not support to make an exception and exists.So, if the busy function that needs special use in the time of can not answering of slave unit is returned the indicator signal of failure.Therefore, the access conflict of intermodule can not take place in the SOC (system on a chip) of this embodiment, thereby the conflict that has solved the main control intermodule that exists in the correlation technique reduction of access efficiency can be caused, and the problem of faulty operation may be produced.
In order to realize having above-mentioned bus-structured SOC (system on a chip), communication interface between needs definition main equipment and the OSB and the communication interface between slave unit and the OSB, promptly, communicate by main equipment and OSB interface between main equipment 20 and the OSB 10, and communicate by slave unit and OSB interface between slave unit 30 and the OSB 10; Wherein,
As shown in table 1, this main equipment and OSB interface have comprised various ports, and for example: address port is used to indicate the numbering of slave unit and the addressing space of slave unit; The operating result receiving port, the result who is used to indicate the corresponding operating that slave unit returns is successfully or failure; Access port is used for the enable access request, and the indication visit is read operation and/or write operation; The first output function FPDP is used for the output function data to slave unit; And the second input operation data port, be used to receive the service data that slave unit sends.
Table 1
Table 1 is depicted as each port of the main equipment bridge interface that contains moderator.The bit wide of Osbm_op_addr port is 32 bits, and as shown in Figure 3, most-significant byte is wherein represented the numbering of slave unit, and back 24 bit representations are wanted the particular address of addressing space.
As shown in table 2, slave unit and OSB interface comprise following at least one: the enable port is used to indicate the slave unit that will enable; The addressing space port is used to indicate the addressing space of the slave unit that will visit, and the addressing space in itself and the address port is complementary; The read/write operation port is used to enable the read/write operation of slave unit; Operating result returns port, and being used for to the result that main equipment returns corresponding operating is successfully or failure; The second output function FPDP is used for the output function data to main equipment; And the second input operation data port, be used to receive the service data that main equipment sends.
Table 2
Table 2 is depicted as each port of the OSB slave unit bridge interface that contains moderator.The operation address port op_addr bit wide of slave unit side is 24, is used to mate the reference address of main equipment.Because the numbering bit wide of slave unit is 8 bits, so OSB can 256 slave units of the highest support.When read operation began, port Osbs_op_ok_n and port Osbs_n_rd_data should be changed to significance bit simultaneously.
If the data bit width of control register has only 8 bits, then need to use LSB (Least Significant Bit, least significant bit (LSB)) to go to mate the read/write data bus, other positions should be retained in IP or be vacant.
Here it should be noted that: the shared bit wide of each port in table 1 and the table 2 can be adjusted according to the demand of reality in actual applications.
In one embodiment of the invention, three slave units in DP RX IP, have been defined.Wherein two is initial I2C access register, and one is the DPCD register.
Fig. 4 shows the sequential synoptic diagram according to the main equipment read operation of the embodiment of the invention, and Fig. 5 is according to the sequential synoptic diagram of the main equipment write operation of the embodiment of the invention.When main equipment sent request, if the slave unit free time, write/read operation can be finished in two cycles.If slave unit is busy, moderator can not send request to slave unit up to the slave unit free time.In this case, request needs to wait for that the long period is until the slave unit free time.
Fig. 6 shows the sequential synoptic diagram according to the slave unit write operation of the embodiment of the invention, and Fig. 7 shows the sequential synoptic diagram according to the slave unit read operation of the embodiment of the invention.All request signals (being request of access) comprise osbs_slave_sel must arrive slave unit simultaneously.
In conjunction with the SOC (system on a chip) shown in 1, the bus access method of this SOC (system on a chip) may further comprise the steps as shown in Figure 8:
Step S802, main equipment will be used to ask the request of access of access slave to be sent to OSB (Open-Shared-Bus, open shared bus);
Step S804, OSB is sent to slave unit with this request of access;
Step S806, slave unit carries out corresponding operating according to this request of access, and the result that will operate is sent to main equipment by OSB.
Preferably, in said method, main equipment is sent to OSB with request of access and comprises: main equipment sends request of access to the bridge unit; The bridge unit is the OSB agreement with the protocol conversion of this request of access, and the request of access that will be converted to the OSB agreement is sent to OSB.
Preferably, in said method, OSB is sent to slave unit with request of access and comprises: OSB is sent to moderator with this request of access; Moderator is analyzed this request of access, the numbering of the slave unit that will visit that obtains carrying in this request of access; According to the numbering that obtains, set up the data channel between the indicated slave unit that will send of main equipment and this numbering.
As can be seen from the above description, the above embodiments of the present invention have realized following technique effect:
The difference and the identical point of SOC and asic chip have been considered fully, by the optimal design of bus having been improved greatly the structure of chip, made bus system become the important step of raising the efficiency.By proposing a kind of universal bus structure of poor efficiency, the ability that it has enough control datas to transmit, make and on same bus system, to support abundant different bus control module to work simultaneously by the access efficiency that reduces each bus control module, and can not conflict and can not produce instantaneous bus efficiency decline yet, thereby solved the bus structure complexity that exists in the correlation technique, be difficult for the problem that realizes.
Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with the general calculation device, they can concentrate on the single calculation element, perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element, carry out by calculation element thereby they can be stored in the memory storage, perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a SOC (system on a chip) is characterized in that, comprising: open shared bus OSB and be connected main equipment and slave unit on the described OSB, wherein:
Described main equipment is used for the request of access of the described slave unit of request visit is sent to described OSB;
Described OSB is used for the described request of access from described main equipment is sent to described slave unit, and the result of the corresponding operating that described slave unit is carried out according to described request of access is sent to described main equipment;
Described slave unit is used for carrying out described corresponding operating according to described request of access, and the result of described corresponding operating is sent to described OSB.
2. SOC (system on a chip) according to claim 1 is characterized in that, described main equipment and described slave unit are the relations of equity.
3. SOC (system on a chip) according to claim 1 is characterized in that, also comprises:
The bridge unit is connected between described main equipment and the described OSB, and being used for the protocol conversion from the described request of access of described main equipment is the OSB agreement, and the request of access that will convert described OSB agreement to is sent to described OSB.
4. SOC (system on a chip) according to claim 1 is characterized in that, described main equipment and described slave unit have a plurality of respectively.
5. SOC (system on a chip) according to claim 4 is characterized in that, also comprises:
Moderator is used to receive the described request of access that described main equipment sends by described OSB, and described request of access analysis is obtained the numbering of the slave unit that will visit entrained in the described request of access; And set up data channel between the indicated described slave unit that will visit of described main equipment and described numbering.
6. SOC (system on a chip) according to claim 5 is characterized in that, described moderator comprises:
The formation arbitration modules is used for the described request of access from a plurality of described main equipments is lined up formation, analyzes the numbering that each described request of access in the formation obtains the slave unit that will visit that carries in each described request of access successively;
The channel allocation module, be used for the described numbering that analysis obtains according to described formation arbitration modules, send instruction so that described slave unit activates and carries out described corresponding operating to the described slave unit that will visit, and set up the data channel between described main equipment and the described slave unit that will visit.
7. according to each described SOC (system on a chip) in the claim 1 to 6, it is characterized in that, communicate by main equipment and OSB interface between described main equipment and the described OSB, and communicate by slave unit and OSB interface between described slave unit and the described OSB; Wherein,
Described main equipment and OSB interface comprise following at least one: address port is used to indicate the numbering of described slave unit and the addressing space of described slave unit; The operating result receiving port, the result who is used to indicate the described corresponding operating that described slave unit returns is successfully or failure; Access port is used to enable described request of access, and to indicate described visit be read operation and/or write operation; The first output function FPDP is used for the output function data to described slave unit; And the second input operation data port, be used to receive the service data that described slave unit sends;
Described slave unit and OSB interface comprise following at least one: the enable port is used to indicate the slave unit that will enable; The addressing space port is used to indicate the addressing space of the described slave unit that will visit, and the described addressing space in itself and the described address port is complementary; The read/write operation port is used to enable the read/write operation of described slave unit; Operating result returns port, and being used for to the result that described main equipment returns described corresponding operating is successfully or failure; The second output function FPDP is used for the output function data to described main equipment; And the second input operation data port, be used to receive the service data that described main equipment sends.
8. the bus access method of a SOC (system on a chip) is characterized in that, may further comprise the steps:
Main equipment will be used to ask the request of access of access slave to be sent to open shared bus OSB;
Described OSB is sent to described slave unit with described request of access;
Described slave unit carries out corresponding operating according to described request of access, and the result of described corresponding operating is sent to described main equipment by described OSB.
9. method according to claim 8 is characterized in that, the request of access that main equipment will be used for access slave is sent to open shared bus OSB and comprises:
Described main equipment sends described request of access to the bridge unit;
Described bridge unit is the OSB agreement with the protocol conversion of described request of access, and the described request of access that will be converted to described OSB agreement is sent to described OSB.
10. method according to claim 8 is characterized in that, described OSB is sent to described slave unit with described request of access and comprises:
Described OSB is sent to moderator with described request of access;
Described moderator is analyzed described request of access, the numbering of the slave unit that will visit that obtains carrying in the described request of access;
Described moderator is set up the data channel between the indicated described slave unit that will visit of described main equipment and described numbering according to described numbering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010282508 CN101937412B (en) | 2010-09-14 | 2010-09-14 | System on chip and access method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010282508 CN101937412B (en) | 2010-09-14 | 2010-09-14 | System on chip and access method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101937412A true CN101937412A (en) | 2011-01-05 |
| CN101937412B CN101937412B (en) | 2013-03-20 |
Family
ID=43390748
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010282508 Active CN101937412B (en) | 2010-09-14 | 2010-09-14 | System on chip and access method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101937412B (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103092798A (en) * | 2012-12-28 | 2013-05-08 | 华为技术有限公司 | On-chip system and method for accessing to equipment under bus |
| CN103218337A (en) * | 2013-03-13 | 2013-07-24 | 北京安拓思科技有限责任公司 | SoC (System on Chip) and method for realizing communication between master modules and between slave modules based on wishbone bus |
| WO2016078307A1 (en) * | 2014-11-20 | 2016-05-26 | 深圳市中兴微电子技术有限公司 | Configurable on-chip interconnection system and method and apparatus for implementing same, and storage medium |
| CN106610906A (en) * | 2015-10-27 | 2017-05-03 | 深圳市中兴微电子技术有限公司 | Data access method and bus |
| CN107517167A (en) * | 2016-06-15 | 2017-12-26 | 华为技术有限公司 | A kind of data transfer control method, device and SoC chip |
| CN108121679A (en) * | 2017-08-07 | 2018-06-05 | 鸿秦（北京）科技有限公司 | A kind of embedded SoC system bus and its protocol conversion bridge-set |
| CN110532062A (en) * | 2019-08-13 | 2019-12-03 | 南京芯驰半导体科技有限公司 | A kind of virtualization SoC bus system and configuration method |
| CN110727636A (en) * | 2019-10-10 | 2020-01-24 | 天津飞腾信息技术有限公司 | System on chip and device isolation method thereof |
| CN112256426A (en) * | 2020-10-21 | 2021-01-22 | 广东高云半导体科技股份有限公司 | Master-slave communication system with bus arbiter and communication method |
| CN112949247A (en) * | 2021-02-01 | 2021-06-11 | 上海天数智芯半导体有限公司 | Phase-based on-chip bus scheduling device and method |
| CN114422290A (en) * | 2022-01-21 | 2022-04-29 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission device and communication system |
| CN115357926A (en) * | 2022-10-19 | 2022-11-18 | 南京芯驰半导体科技有限公司 | AXI bus protocol access authority control method and device based on SoC chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101281511A (en) * | 2007-04-02 | 2008-10-08 | 成都方程式电子有限公司 | On-chip bus system |
| US20100138577A1 (en) * | 2008-12-03 | 2010-06-03 | Samsung Electronics Co. Ltd. | Apparatus and method for writing bitwise data in system on chip |
-
2010
- 2010-09-14 CN CN 201010282508 patent/CN101937412B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101281511A (en) * | 2007-04-02 | 2008-10-08 | 成都方程式电子有限公司 | On-chip bus system |
| US20100138577A1 (en) * | 2008-12-03 | 2010-06-03 | Samsung Electronics Co. Ltd. | Apparatus and method for writing bitwise data in system on chip |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103092798B (en) * | 2012-12-28 | 2016-05-25 | 华为技术有限公司 | The method of the access means under SOC(system on a chip) and bus |
| US9489328B2 (en) | 2012-12-28 | 2016-11-08 | Huawei Technologies Co., Ltd. | System on chip and method for accessing device on bus |
| CN103092798A (en) * | 2012-12-28 | 2013-05-08 | 华为技术有限公司 | On-chip system and method for accessing to equipment under bus |
| CN103218337A (en) * | 2013-03-13 | 2013-07-24 | 北京安拓思科技有限责任公司 | SoC (System on Chip) and method for realizing communication between master modules and between slave modules based on wishbone bus |
| CN103218337B (en) * | 2013-03-13 | 2015-10-07 | 北京安拓思科技有限责任公司 | Based on wishbone bus realize main and master and slave with from the SOC (system on a chip) communicated and method |
| WO2016078307A1 (en) * | 2014-11-20 | 2016-05-26 | 深圳市中兴微电子技术有限公司 | Configurable on-chip interconnection system and method and apparatus for implementing same, and storage medium |
| US10198374B2 (en) | 2014-11-20 | 2019-02-05 | Sanechips Technology Co. Ltd. | Configurable on-chip interconnection system and method and apparatus for implementing same, and storage medium |
| CN106610906A (en) * | 2015-10-27 | 2017-05-03 | 深圳市中兴微电子技术有限公司 | Data access method and bus |
| CN107517167B (en) * | 2016-06-15 | 2020-04-14 | 华为技术有限公司 | Data transmission control method and device and SoC chip |
| CN107517167A (en) * | 2016-06-15 | 2017-12-26 | 华为技术有限公司 | A kind of data transfer control method, device and SoC chip |
| CN108121679A (en) * | 2017-08-07 | 2018-06-05 | 鸿秦（北京）科技有限公司 | A kind of embedded SoC system bus and its protocol conversion bridge-set |
| CN110532062A (en) * | 2019-08-13 | 2019-12-03 | 南京芯驰半导体科技有限公司 | A kind of virtualization SoC bus system and configuration method |
| CN110532062B (en) * | 2019-08-13 | 2022-05-20 | 南京芯驰半导体科技有限公司 | Virtual SoC bus system and configuration method |
| CN110727636A (en) * | 2019-10-10 | 2020-01-24 | 天津飞腾信息技术有限公司 | System on chip and device isolation method thereof |
| CN110727636B (en) * | 2019-10-10 | 2024-02-06 | 飞腾信息技术有限公司 | Equipment isolation method of system on chip |
| CN112256426A (en) * | 2020-10-21 | 2021-01-22 | 广东高云半导体科技股份有限公司 | Master-slave communication system with bus arbiter and communication method |
| CN112949247A (en) * | 2021-02-01 | 2021-06-11 | 上海天数智芯半导体有限公司 | Phase-based on-chip bus scheduling device and method |
| CN112949247B (en) * | 2021-02-01 | 2022-05-20 | 上海天数智芯半导体有限公司 | Phase-based on-chip bus scheduling device and method |
| CN114422290A (en) * | 2022-01-21 | 2022-04-29 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission device and communication system |
| CN115357926A (en) * | 2022-10-19 | 2022-11-18 | 南京芯驰半导体科技有限公司 | AXI bus protocol access authority control method and device based on SoC chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101937412B (en) | 2013-03-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101937412B (en) | System on chip and access method thereof | |
| CN1661583B (en) | Protocol conversion and arbitration circuit and system, and method for converting and arbitrating signals | |
| CN100499556C (en) | High-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor | |
| CN101477512B (en) | Processor system and its access method | |
| CN105051706A (en) | Device, method and system for operation of a low power PHY with a PCIe protocol stack | |
| CN104714907B (en) | A kind of pci bus is converted to ISA and APB bus design methods | |
| CN201583945U (en) | Serial communication system for multiple singlechips based on FPGA | |
| CN101770442A (en) | Data interaction system with a plurality of external interfaces and method | |
| CN104156333A (en) | FPGA-based UART multi-interface extension system and method | |
| CN202077061U (en) | Multi-port and multi-network protocol converter | |
| CN103218337A (en) | SoC (System on Chip) and method for realizing communication between master modules and between slave modules based on wishbone bus | |
| US10747699B2 (en) | Bus control circuit, semiconductor integrated circuit, circuit board, information processing device and bus control method | |
| CN101650701B (en) | Converting device from parallel bus to RapidIO high-speed serial bus | |
| CN202948447U (en) | Serial Rapid IO protocol controller based on peripheral component interconnect (PCI) bus | |
| CN101136754A (en) | Data transmission control system of ethernet chip | |
| CN114089649A (en) | Automatic test tool system and method | |
| US20090193225A1 (en) | System and method for application specific array processing | |
| CN102591817B (en) | Multi-bus bridge controller and implementing method thereof | |
| CN116401065A (en) | Server, heterogeneous equipment and data processing device thereof | |
| US20090177832A1 (en) | Parallel computer system and method for parallel processing of data | |
| CN113496108B (en) | CPU model applied to simulation | |
| CN109491949A (en) | Dynamic reconfigurable frame and method based on Zynq | |
| CN112557886B (en) | Protocol conversion bridge circuit and system-on-chip | |
| US7000148B2 (en) | Program-controlled unit | |
| CN103902767A (en) | QEMU and SystemC based multi-core simulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: System on chip and access method thereof Effective date of registration: 20180718 Granted publication date: 20130320 Pledgee: Zhongguancun Beijing technology financing Company limited by guarantee Pledgor: ANALOGIX (CHINA) SEMICONDUCTOR, Inc. Registration number: 2018990000570 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20220802 Granted publication date: 20130320 Pledgee: Zhongguancun Beijing technology financing Company limited by guarantee Pledgor: ANALOGIX (CHINA) SEMICONDUCTOR, Inc. Registration number: 2018990000570 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right |