CN112256426A - Master-slave communication system with bus arbiter and communication method - Google Patents
Master-slave communication system with bus arbiter and communication method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4031—Coupling between buses using bus bridges with arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Abstract
The invention relates to a master-slave communication system with a bus arbiter and a communication method. In the master-slave communication system, a bus arbiter obtains the initial address and the space size of each slave device mapped in a system memory by using a dynamic address allocation module realized based on FPGA, the initial address and the space size are dynamically adjustable based on the programmable characteristic of FPGA, the problem that the address space required by the slave device is not matched with the originally allocated address space can be effectively solved, the address utilization rate of the system memory space is improved, meanwhile, the bus arbiter is used for arbitrating the connection requests sent by more than two master devices to the same slave device, and the number of the slave devices can be flexibly expanded. The communication method adopts the master-slave communication system with the bus arbiter.
Description
Technical Field
The invention relates to the field of FPGA (field programmable gate array) application, in particular to a master-slave communication system with a bus arbiter and a communication method.
Background
The bus is a public communication trunk line for transmitting information among various functional components of the computer system, and is a public channel for transmitting information by the processor, the memory and the input/output equipment, all the components of the host are connected through the bus, and the external equipment is connected with the bus through the corresponding interface circuit.
In the field of MCU (Micro-Controller Unit), generally, external devices of an MCU core are divided into a master device and a slave device, and the master device can send a read command and a write command to the slave device. The master and slave devices may each be more than one. The plurality of master devices and the plurality of slave devices are connected to the bus system through a bus arbiter, wherein the memory address space of the MCU can be segmented by the bus arbiter and each segment of address is allocated to each slave device, and each slave device accessed through the bus system is distinguished by distinguishing the address space allocated to each slave device by address segmentation.
In the design of the existing bus arbiter, once the memory address space set for the slave device is designed, the memory address space is fixed, and the following problems are easy to occur in the practical application process: firstly, the address space required by the slave device is larger than the address space allocated by the bus arbiter, and the address mapping of the MCU storage space needs to be reconstructed; secondly, the address space required by the slave equipment is smaller than the address space allocated by the bus arbiter, so that the address of the MCU storage space is wasted; thirdly, because the address space allocated by each slave device is fixed, the number expansion of the slave devices can be restricted, and the address utilization rate of the MCU storage space is reduced.
Disclosure of Invention
To solve the above problems, the present invention provides a master-slave communication system having a bus arbiter. A communication method is also provided.
In one aspect, the present invention provides a master-slave communication system having a bus arbiter, where the master-slave communication system is configured to implement communication between a master device and a slave device, the number of the master device and the number of the slave device are both more than two, the bus arbiter includes a dynamic address allocation module implemented based on an FPGA (Field Programmable Gate Array), the dynamic address allocation module is configured to allocate a starting address and a space size of the slave device mapped in a system memory, where the starting address and the space size are dynamically adjustable, and the bus arbiter obtains the starting address and the space size of each slave device mapped in the system memory by using the dynamic address allocation module, and arbitrates connection requests sent by more than two master devices to the same slave device.
Optionally, the number of the slave devices is greater than or equal to the number of the master devices.
Optionally, the dynamic address allocation module is configured with a plurality of slave device start address registers and a plurality of slave device address space registers, where each slave device start address register is configured to register a start memory address corresponding to one slave device, and each slave device address space register is configured to register a memory address space corresponding to one slave device.
Optionally, corresponding to each master device, the dynamic address allocation module is configured with a slave device start address register and a slave device address space register related to the master device, and the number of the slave device start address register and the slave device address space register corresponding to each master device is dynamically adjustable.
Optionally, the bus arbiter further includes the following modules implemented based on the FPGA:
the master equipment analysis module is arranged in one-to-one correspondence with the master equipment, and is configured to analyze and latch a signal from the corresponding master equipment and also configured to feed back a response signal from the slave equipment to the corresponding master equipment;
the slave device address analysis module is arranged in one-to-one correspondence with the master device, configured to obtain memory address information of the slave device related to the corresponding master device from the dynamic address allocation module, and further configured to call a signal from the corresponding master device latched by the master device address analysis module, and select one to be communicated from a plurality of slave device output modules to establish a communication channel; and the number of the first and second groups,
and the slave equipment output module is arranged in one-to-one correspondence with the slave equipment and is configured to output a signal from the master equipment to the corresponding slave equipment and read a response signal fed back by the corresponding slave equipment.
Optionally, the bus arbiter further includes a master device contention module implemented based on the FPGA, where the master device contention module and the slave device output module are disposed between the slave device address resolution module and the slave device output module in a one-to-one correspondence, and each master device contention module is connected to each slave device address resolution module; when more than two slave device address resolution modules select the same slave device to communicate, the master device competition module corresponding to the slave device orders the slave device address resolution modules according to a priority rule, and sequentially enables the slave device address resolution modules to communicate with the slave device according to a priority order.
Optionally, the signals from the corresponding master device analyzed and latched by the master device analysis module include write data signals, read data signals, address signals, read-write control signals, and enable signals.
Optionally, the master-slave communication system is a system on chip configured based on an FPGA and an MCU core, the MCU core interacts with the dynamic address allocation module through a private bus, and an executable program of the MCU core is used to control the dynamic address allocation module to dynamically adjust an initial address and a space size of the slave device mapped in a system memory.
Optionally, the system on chip has a master bus and a slave bus, the master is connected to the bus arbiter via the corresponding master bus, and the slave is connected to the bus arbiter via the corresponding slave bus.
In one aspect, the present invention provides a communication method, which uses the above-mentioned master-slave communication system, and the communication method includes the following steps:
analyzing a signal from the master equipment, judging whether the master equipment sends a connection request aiming at the slave equipment, if so, executing downwards, and if not, returning to perform next judgment;
sending a signal from the master device to the bus arbiter, wherein the bus arbiter judges slave devices to be communicated, and selects the slave devices to be communicated and forms corresponding communication channels by using the memory address allocation information of the slave devices allocated by the dynamic address allocation module; and the number of the first and second groups,
the bus arbiter obtains a read-write control signal from a signal from the master device, judges whether the master device performs a read operation or a write operation on the slave device, sends a data signal of the slave device to the master device through the communication channel if the master device performs the read operation, and sends the data signal of the master device to the slave device through the communication channel if the master device performs the write operation.
The invention provides a master-slave communication system with a bus arbiter, wherein the bus arbiter comprises a dynamic address allocation module realized based on FPGA (field programmable gate array), the dynamic address allocation module is used for configuring the starting address and the space size of slave equipment mapped in a system memory, and the starting address and the space size are dynamically adjustable based on the programmable characteristic of the FPGA. The problem that the address space required by the slave equipment is not matched with the originally distributed address space can be effectively solved, the address utilization rate of the system memory space is improved, meanwhile, the bus arbiter is utilized to arbitrate the connection requests sent by more than two master equipment to the same slave equipment, the number of the slave equipment can be flexibly expanded, and the overall performance of the system is improved.
The communication method provided by the invention adopts the master-slave communication system with the bus arbiter, the memory address information of the slave equipment can be dynamically adjusted, and the communication between the master equipment and the slave equipment can be realized, so that the communication method has wide application prospect.
Drawings
Fig. 1 is a signal connection diagram of a master-slave communication system according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a bus arbiter in a master-slave communication system according to an embodiment of the present invention.
FIG. 3 is a block diagram of a dynamic address assignment module in a bus arbiter according to an embodiment of the present invention.
Fig. 4 is a flowchart illustrating a communication method according to an embodiment of the invention.
Description of reference numerals:
100-bus arbiter; 110-dynamic address assignment module; 120-master device parsing module; 130-slave address module; 140-slave device output module; 150-master race module.
Detailed Description
The master-slave communication system with a bus arbiter and the communication method of the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the MCU design, functional units are often connected to a bus system through a bus arbiter, and address and space sizes of slave devices in an MCU core are allocated by using address segments determined by the bus arbiter, so that when an operation is performed on any one slave device, the slave devices accessed by the bus system can be distinguished by using address segment information of the slave device. However, as described in the background art, the prior art is often prone to the problem that the address space actually required by the slave device does not match the address space allocated by the bus arbiter, the address utilization of the MCU memory space is reduced, and the number of slave devices is limited from expanding in the case where the address space allocated per slave device is fixed.
The invention provides a master-slave communication system with a bus arbiter and a communication method adopting the master-slave communication system based on the advantages of the FPGA (Field Programmable Gate Array), which can effectively avoid or improve the problems of the prior art, such as mismatching of an address space required by slave equipment and an address space distributed by the bus arbiter, waste caused by low address utilization rate of a storage space and poor quantity expandability of the slave equipment.
Based on the advantages of the MCU and the FPGA, the MCU, the memory, the external equipment and the like can be connected by utilizing the resources of the FPGA, so that a System-on-a-chip (SoC) which can fully meet the flexibility requirement in user design is formed, and the System-on-a-chip is a research hotspot in recent years. In the following embodiments, the master-slave communication system of the present invention is mainly described by using an on-chip system based on an MCU and an FPGA. However, it should be noted that the master-slave communication system of the present invention is not limited to the on-chip system based on the MCU and the FPGA, and the master-slave communication system of the present invention may also cover other on-chip systems or non-on-chip systems constructed by using the FPGA. In one embodiment, the master-slave communication system may also be a control device or a data transmission device.
The master-slave communication system is used for realizing communication between master equipment and slave equipment, the number of the master equipment and the number of the slave equipment are more than two, the number of the master equipment and the number of the slave equipment can be the same or different, the setting of the slave equipment is flexible, and the number of the slave equipment can be more than or equal to the number of the master equipment. The master-slave communication system according to the embodiment of the present invention will be described below by taking a case where two master devices and three slave devices are connected to each other as an example.
Fig. 1 is a signal connection diagram of a master-slave communication system according to an embodiment of the present invention. Referring to fig. 1, a master-slave communication system according to an embodiment of the present invention is used to implement communication between a master device, for example, two (master device (1) and master device (2)), and a slave device, for example, three (slave device (1), slave device (2), and slave device (3)). The master-slave communication system comprises an MCU core and an FPGA, the master-slave communication system is configured with a bus arbiter by utilizing the resources of the FPGA, and the MCU core and the bus arbiter are connected in a bus mode. The memory address space of the MCU kernel can be segmented by using the bus arbiter, and each segment of address is distributed to each slave device. The bus arbiter comprises a dynamic address allocation module implemented based on an FPGA, the dynamic address allocation module is configured to allocate a start address and a space size of each slave device mapped in a system memory (which may be referred to as an MCU memory), and the dynamic address allocation module may be controlled by the MCU core, for example, through software of the MCU core, to dynamically adjust the start address and the space size of each slave device mapped in the system memory.
Fig. 2 is a schematic diagram of a bus arbiter in a master-slave communication system according to an embodiment of the present invention. Referring to fig. 2, the master-slave communication system has a bus arbiter 100, and the bus arbiter 100 includes a dynamic address allocation module 110 implemented by a programmable resource based on an FPGA, where the dynamic address allocation module 110 is configured to configure the address and space size of each slave device connected to the master-slave communication system, which are mapped in the system memory, where the address and space size of the slave device mapped in the system memory are dynamically adjustable, and the bus arbiter 100 obtains the start address and space size of each slave device mapped in the system memory by using the dynamic address allocation module 110, and arbitrates connection requests sent by more than two master devices to the same slave device.
The master-slave communication system of the embodiment of the present invention utilizes the bus arbiter 100 to allocate the memory address of each slave device, and the bus arbiter 100 utilizes the programmable resource of the FPGA to implement the dynamic address allocation module 110, so as to configure the address and space size of each slave device mapped in the system memory. Therefore, the programming content of the dynamic address allocation module 110 can be adjusted according to the actual situations of the master device and the slave device, that is, the addresses and the space size of the slave device mapped in the system memory can be dynamically adjusted.
The above arrangement is useful for improving the functionality of the master-slave communication system of the embodiment of the present invention, as illustrated below. In an embodiment, if the required address space of any slave device connected to the bus arbiter is greater than the address space originally allocated by the bus arbiter 100, at this time, the dynamic address allocation module 110 may be controlled and adjusted, for example, an MCU kernel may execute a software program to control the dynamic address allocation module 110, so that the logical resource description of the FPGA corresponding to the dynamic address allocation module 110 changes, and thus the sizes of the address and space reflected by each slave device mapped in the system memory change, and after the dynamic address allocation module 110 is adjusted, the address space internally allocated to the slave device matches the requirement of the corresponding slave device. In an embodiment, if the address space required by a slave device is smaller than or even much smaller than the originally allocated address space of the bus arbiter, if the address space is directly used, a great waste of the system memory address space may be caused, at this time, by applying the bus arbiter 100, the dynamic address allocation module 110 may be controlled and adjusted (the adjustment method may refer to the previous embodiment), so that the address space allocated to the slave device after adjustment matches with the requirement thereof, which may save the address space of the system memory and improve the address utilization rate of the memory space. In an embodiment, if the number of the slave devices needs to be expanded and the existing allocation manner of the memory address space cannot be satisfied, the bus arbiter 100 may also be applied, and in use, the dynamic address allocation module 110 is adjusted according to the expansion requirement of the slave devices (the adjustment manner may be referred to in the above embodiment), so that after the adjustment, the address space allocated to each expanded slave device matches their requirements, which may improve the scalability and design flexibility of the system.
Referring to fig. 2, the number of the master devices and the number of the slave devices configured in the master-slave communication system are both more than two. The master-slave communication system may be a system on chip (SoC) configured based on an FPGA and an MCU core (not shown), and each of the master device and the slave device may be an on-chip external device or an off-chip external device of the MCU core. The system on chip has master buses (such as master bus (1) and master bus (2) in fig. 2) and slave buses (such as slave bus (1), slave bus (2), and slave bus (3) in fig. 2), and each of the master devices is connected to the bus arbiter 100 through a corresponding master bus and each of the slave devices is connected to the bus arbiter 100 through a corresponding slave bus. In addition, the master-slave communication system may further have an arbitration control bus, and the MCU core may control the above dynamic address allocation module 110 in the bus arbiter 100 through the arbitration control bus. Specifically, the arbitration control bus may be configured as a private bus of the MCU core, that is, the interaction between the MCU core and the dynamic address allocation module 100 is performed through the private bus. In an embodiment, the MCU core may control the dynamic address allocation module 110 by executing a corresponding executable program, so that the logic resource of the FPGA corresponding to the dynamic address allocation module 110 changes, and the size of the address and space mapped in the system memory by each slave device changes, where the executable program may be programmed and modified according to the configuration requirement of the slave device. The executable program can be written by C language and stored in the storage module of the master-slave communication system. The storage module can be an off-chip memory or can be arranged in a chip. Further, the storage module can also be realized by the resources of the FPGA.
FIG. 3 is a block diagram of a dynamic address assignment module in a bus arbiter according to an embodiment of the present invention. Referring to fig. 3, the dynamic address allocation module 110 may be configured with a plurality of slave device start address registers (such as the slave device (1) start address register, the slave device (2) start address register, and the slave device (3) start address register in fig. 3, the numbers of which are shown as examples only) and a plurality of slave device address space registers (such as the slave device (1) address space register, the slave device (2) address space register, and the slave device (3) address space register in fig. 3, the numbers of which are shown as examples only), each of the slave device start address registers is configured to store a start memory address corresponding to a slave device connected to the bus arbiter 100, and each of the slave device address space registers is configured to store a memory address space corresponding to a slave device connected to the bus arbiter 100. In addition, for each master device connected to the bus arbiter 100, the dynamic address allocation module 100 may be configured with a slave device start address register and a slave device address space register related to the master device (here, it means that there is a master-slave device interaction relationship) for the slave device address resolution module 130 corresponding to each master device one to call, such as two slave device address resolution modules 130 (slave device address resolution module (1) and slave device address resolution module (2)) in fig. 3 respectively call the start address and address space of each slave device from the respective corresponding register group. The number of slave device address resolution modules 130 in fig. 3 is merely an example. In an embodiment, the number of the slave device start address registers and the slave device address space registers corresponding to each master device (called by each slave device address resolution module 130) can be dynamically adjusted under the control of the MCU core, so as to improve the flexibility of design, improve the address utilization rate of the system memory space (such as the memory space in the MCU core), and improve the overall performance of the master-slave communication system.
Referring to fig. 2 and 3, in an embodiment, the bus arbiter 100 further includes a master device parsing module 120, a slave device address parsing module 130, and a slave device output module 140 implemented by using the resources of the FPGA. The various modules in the bus arbiter 100 may be connected by the connection line resources of the FPGA.
The master device parsing module 120 is arranged in one-to-one correspondence with the master devices connected to the bus arbiter 100. In fig. 2, the bus arbiter illustratively includes two master resolution modules 120 (master resolution module (1) and master resolution module (2) in fig. 2, respectively). The master parsing module 120 may be configured to parse and latch a signal from the corresponding master, and further configured to feed back a valid response signal (ACK) from the slave to the corresponding master. The master device parsing module 120 may be connected to the corresponding master device through a master device bus.
The slave device address resolution module 130 is arranged in one-to-one correspondence with the master device (i.e. arranged in one-to-one correspondence with the master device resolution module 120, the slave device address resolution module 130 in fig. 2 is a slave device address resolution module (1) and a slave device address resolution module (2), the slave device address resolution module 130 is connected with the corresponding master device resolution module 120. in one embodiment, the slave device address resolution module 130 is configured to obtain memory address information of the slave device related to the corresponding master device from the dynamic address allocation module 110, and is further configured to call a signal (including a connection request signal) from the corresponding master device latched by the master device resolution module 120, and select one of the connected slave device output modules to communicate with to establish a communication channel 120 to the master device to which it is connected. A slave device related to a master device refers to a slave device having a communication relationship with the master device.
The slave device output modules 140 (such as the exemplary slave device output module (1), the slave device output module (2), and the slave device output module (3) in fig. 2) are provided in one-to-one correspondence with the slave devices to which the bus arbiter 100 is connected. The slave output module 140 may be configured to output a signal (including a connection request signal) from the master device to a corresponding slave device and read a response signal (ACK) of the corresponding slave device.
In the communication process, when two or more slave device address resolution modules 130 all select the same slave device to perform communication, that is, when the bus arbiter 100 determines that two or more master devices all send connection requests to the same slave device, arbitration needs to be performed, so in an embodiment, the bus arbiter 100 may further include a master device competition module 150 (such as the master device competition module (1), the master device competition module (2), and the master device competition module (3) in fig. 2) implemented based on the FPGA, each master device competition module 150 and each slave device output module 140 are disposed between the slave device address resolution module 130 and the slave device output module 140 in a one-to-one correspondence, and each master device competition module 150 is connected to each slave device address resolution module 130. The master contention module 150 may be configured to: when two or more slave address resolution modules 130 select the same slave (the slave corresponding to the master competition module 150) for communication, the master competition module 150 corresponding to the slave sorts the slave address resolution modules 130 according to a priority rule, and sequentially communicates the slave address resolution modules 130 with the slave according to a priority order. In the priority rule, the slave address resolution module 130 located closer (or farther) than the master competition module 150 may be set to have higher priority, and correspondingly, the slave address resolution module 130 located farther (or closer) than the master competition module 150 may be set to have lower priority. The priority rules employed by the master contention module 150 may also be set according to the disclosed manner. The priority order may be from high to low, or from low to high, for example, when the priority order is from high to low, the slave device address resolution module 130 with the highest priority communicates with the slave device first.
The signals transmitted by the master-slave communication system according to the embodiment of the present invention may include a write data signal (WDATA), a read data signal (RDATA), an address signal (ADDR), an ENABLE signal (ENABLE), a read-write control signal (CTRL), and a response signal (ACK). The bus arbiter 100 may implement signaling between a master device and a slave device based on register operations. The functions of the above modules of the bus arbiter 100 in the communication process will be further described below by taking an MCU and FPGA-based system on chip as an example.
After the MCU core obtains the operation signal of the master device, the operation signal is sent to the master device parsing module 120 through the master device bus. The master device parsing module 120 may implement mapping of data between a master device bus and an internal register, so as to parse and latch signals from the corresponding master device, where the signals latched by the master device parsing module 120 include a write data signal (WDATA), a read data signal (RDATA), an address signal (ADDR), a read/write control signal (CTRL), and an ENABLE signal (ENABLE) sent by the MCU core through the master device bus. These signals may be invoked by a slave address resolution module 130 connected to the master device resolution module 120. In communication, after receiving the signal from the corresponding master device, the master device parsing module 120 may first feed back a level (e.g., a low level) to the corresponding master device through the master device bus to represent an initial response signal (ACK), and then the master device parsing module 120 monitors the response signal (ACK) fed back by the internal slave device address parsing module 130, and when the response signal (ACK) fed back by the slave device address parsing module 130 is opposite to the initial level (e.g., a high level), then feeds back the opposite level to the off-chip master device, which is equivalent to feeding back a valid response signal (ACK).
The slave address resolution module 130 may read the ADDR register (i.e., address register) in the corresponding master resolution module 120 through resolution, and select the master competition module 150 corresponding to the slave to be controlled, so as to form a communication channel between the master and the slave to be communicated. The slave device address resolution module 130 may first read the slave device start address register and the slave device address space register of the dynamic address allocation module 110 (fig. 3), and generate an address lookup table; then, according to the address lookup table, the slave host device parsing module 120 calls a write data signal (WDATA), a read data signal (RDATA), an address signal (ADDR), an ENABLE signal (ENABLE), and a read/write control signal (CTRL) to send to the corresponding master device competition module 150, and simultaneously reads a response signal (ACK) fed back from the corresponding master device competition module 150 and sends the response signal (ACK) to the master device parsing module 120, and the master device parsing module 120 feeds back the response signal (ACK) to the corresponding master device.
When two or more slave address resolution modules 130 select the same slave device to perform communication (that is, when two or more master devices send connection requests to the same slave device), the master device competition module 150 corresponding to the slave device first latches the write data signal (WDATA), the read data signal RADTA, the address signal (ADDR), the read/write control signal (CTRL), and the ENABLE signal (ENABLE) sent by each slave address resolution module 130 (for example, two channels, i.e., the slave address resolution module (1) and the slave address resolution module (2) in fig. 2), and may be specifically stored in corresponding registers. The master contention module 150 additionally monitors a response signal (ACK) of the corresponding slave output module 140, and if the signal is at a high level, feeds back the high level to the communication channel of the slave address resolution module 130 with the highest priority, and then sends signals of registers corresponding to the write data signal (WDATA), the read data signal RADTA, the address signal (ADDR), the read/write control signal (CTRL), and the ENABLE signal (ENABLE) of the communication channel with the corresponding slave output module 140 to complete communication; then, the response signal (ACK) of the corresponding slave device output module 140 is continuously monitored, if the response signal is high level, the high level is fed back to the communication channel of the slave device address resolution module 130 with lower priority, and the write data signal (WDATA), the read data signal RADTA, the address signal (ADDR), the read-write control signal (CTRL) and the ENABLE signal (ENABLE) of the communication channel with low priority are sent to the corresponding slave device output module 140, so that the communication is completed; and completing the communication between the same slave device and each slave device address resolution module 130 in the corresponding communication channel according to a similar sequence.
For the slave device output module 140, in obtaining the write data signal (WDATA), the read data signal (RDATA), the address signal (ADDR), the ENABLE signal (ENABLE), and the read/write control signal (CTRL) sent by the master device competition module 150 (i.e., the previous module) (for example, by calling a register of the master device competition module 150), a corresponding signal is output to the connected slave device, and at the same time, a response signal (ACK) fed back by the connected slave device is read and fed back to the master device competition module 150 connected thereto.
The embodiment of the invention also relates to a communication method, which adopts the master-slave communication system. The communication method comprises the following steps:
analyzing a signal from the master equipment, judging whether the master equipment sends a connection request aiming at the slave equipment, if so, executing downwards, and if not, returning to perform next judgment;
sending a signal from the master device to the bus arbiter, wherein the bus arbiter judges slave devices to be communicated, and selects the slave devices to be communicated and forms corresponding communication channels by using the memory address allocation information of the slave devices allocated by the dynamic address allocation module; and the number of the first and second groups,
the bus arbiter obtains a read-write control signal from a signal from the master device, judges whether the master device performs a read operation or a write operation on the slave device, sends a data signal of the slave device to the master device through the communication channel if the master device performs the read operation, and sends the data signal of the master device to the slave device through the communication channel if the master device performs the write operation.
Fig. 4 is a flowchart illustrating a communication method according to an embodiment of the invention. The communication method described above will be described below with reference to fig. 2 to 4, taking two masters (connected to two master buses in the figure) and three slaves (connected to three slave buses in the figure) as shown in fig. 2 as an example.
The communication method may include the processes of:
s1: the MCU core scans signals of each master device, and if a certain master device sends an operation signal of a connection request, the MCU core sends a signal to the bus arbiter 100 through a corresponding master device bus, where an ENABLE signal is, for example, a high level (ENABLE ═ 1);
s2: the bus arbiter 100 determines through which slave address resolution module 130 to perform address resolution and establish a communication channel according to the address signal, and latches the signal from the master device by the corresponding master address resolution module 120, in this embodiment, two slave address resolution modules 130 (such as the slave address resolution module (1) and the slave address resolution module (2) in fig. 2) interact with two master devices respectively and three slave devices respectively, so that after selecting one of the two slave address resolution modules 130 (such as the slave address resolution module (1) and the slave address resolution module (2) in fig. 2), the slave address resolution module 130 may obtain the slave device (such as the slave device (1), the slave device (2) and the slave device (3) in fig. 4) to be connected from the dynamic address allocation module 110, the slave device address resolution module 130 determines, according to the address signal, memory address information (including a start address and an address space size) corresponding to a slave device to be communicated, so as to establish a communication path with the slave device to be communicated for signal transmission, and specifically, the memory address information corresponding to the slave device obtained from the dynamic address allocation module 110 may be sent to the corresponding master device competition module 150, and the master device competition module 150 establishes a connection between the slave device address resolution module 130 and the slave device to be communicated according to a priority rule;
s3: after the communication path is established, signal transmission is performed through register operation, first, the master device parsing module 120 of the bus arbiter 100 determines whether a read operation or a write operation is to be performed according to the read-write control signal, according to the determination result, the slave device address parsing module 130 calls the read register or the write register in the master device parsing module 120 connected thereto, and transmits a signal to the master device competition module 150 connected to the selected slave device, the master device competition module 150 transmits the signal from the slave device address parsing module 130 to the corresponding slave device output module 140 according to the priority rule, the slave device output module 140 transmits the signal to the slave device connected thereto, and the slave device output module 140 reads a response signal fed back by the slave device and feeds back the response signal to the master device competition module 150, wherein the response signal further passes through the slave device address parsing module 130, The master device parsing module 120 feeds back to the MCU core and the master device, so that the communication is completed.
In the above communication method, the operation of analyzing the signal from the master device, the operation of transmitting the signal from the master device to the bus arbiter, and the control operation of the bus arbiter may be performed by an MCU core. The communication method may be stored in a memory in the form of a computer program which, when executed by a processor of the master-slave communication system, performs the communication method described above.
The master-slave communication system with the bus arbiter 100 described in the embodiment of the present invention can effectively solve the problem that the address space required by the slave device is not matched with the address space allocated by the bus arbiter, thereby improving the address utilization rate of the system memory space, and meanwhile, the bus arbiter is used to arbitrate the connection requests sent from more than two master devices to the same slave device, the number of the slave devices is not restricted by the solidified address, and the master-slave communication system can be flexibly expanded, thereby being beneficial to improving the overall performance of the system. The communication method described in the embodiment of the present invention adopts the master-slave communication system with the bus arbiter 100, in which the memory address information of the slave device can be dynamically adjusted according to the actual configuration of the slave device, and the communication between the master device and the slave device can be realized, thereby having a wide application prospect.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (10)
1. The bus arbiter is characterized by comprising a dynamic address allocation module realized based on an FPGA (field programmable gate array), wherein the dynamic address allocation module is used for allocating the starting address and the space size of the slave device mapped in a system memory, the starting address and the space size are dynamically adjustable, the bus arbiter obtains the starting address and the space size of each slave device mapped in the system memory by using the dynamic address allocation module, and arbitrates connection requests sent by more than two master devices to the same slave device.
2. The master-slave communication system of claim 1, wherein the number of slave devices is greater than or equal to the number of master devices.
3. The master-slave communication system of claim 1, wherein the dynamic address allocation module is configured with a plurality of slave device start address registers and a plurality of slave device address space registers, each of the slave device start address registers being configured to register a start memory address corresponding to one of the slave devices, each of the slave device address space registers being configured to register a memory address space corresponding to one of the slave devices.
4. A master-slave communications system according to claim 3, wherein for each of the masters the dynamic address allocation module is configured with slave start address registers and slave address space registers associated with the master and the number of slave start address registers and slave address space registers corresponding to each of the masters is dynamically adjustable.
5. The master-slave communication system of claim 1, wherein the bus arbiter further comprises the following modules implemented based on the FPGA:
the master equipment analysis module is arranged in one-to-one correspondence with the master equipment, and is configured to analyze and latch a signal from the corresponding master equipment and also configured to feed back a response signal from the slave equipment to the corresponding master equipment;
the slave device address analysis module is arranged in one-to-one correspondence with the master device, configured to obtain memory address information of the slave device related to the corresponding master device from the dynamic address allocation module, and further configured to call a signal from the corresponding master device latched by the master device address analysis module, and select one to be communicated from a plurality of slave device output modules to establish a communication channel; and the number of the first and second groups,
and the slave equipment output module is arranged in one-to-one correspondence with the slave equipment and is configured to output a signal from the master equipment to the corresponding slave equipment and read a response signal fed back by the corresponding slave equipment.
6. The master-slave communication system according to claim 5, wherein the bus arbiter further comprises a master contention module implemented based on the FPGA, the master contention module and the slave output module are disposed between the slave address resolution module and the slave output module in a one-to-one correspondence, and each master contention module is connected to each slave address resolution module;
when more than two slave device address resolution modules select the same slave device to communicate, the master device competition module corresponding to the slave device orders the slave device address resolution modules according to a priority rule, and sequentially enables the slave device address resolution modules to communicate with the slave device according to a priority order.
7. The master-slave communication system of claim 5, wherein the signals from the corresponding master device parsed and latched by the master device parsing module include write data signals, read data signals, address signals, read-write control signals, and enable signals.
8. The master-slave communication system according to any one of claims 1 to 7, wherein the master-slave communication system is a system on chip configured based on an FPGA and an MCU core, the MCU core interacts with the dynamic address allocation module through a private bus, and an executable program of the MCU core is used to control the dynamic address allocation module to dynamically adjust the starting address and the space size of the slave device mapped in the system memory.
9. The master-slave communication system of claim 8, wherein the system-on-chip has a master bus and a slave bus, the master being connected to the bus arbiter through a respective master bus and the slave being connected to the bus arbiter through a respective slave bus.
10. A communication method using the master-slave communication system according to any one of claims 1 to 9, the communication method comprising the steps of:
analyzing a signal from the master equipment, judging whether the master equipment sends a connection request aiming at the slave equipment, if so, executing downwards, and if not, returning to perform next judgment;
sending a signal from the master device to the bus arbiter, wherein the bus arbiter judges slave devices to be communicated, and selects the slave devices to be communicated and forms corresponding communication channels by using the memory address allocation information of the slave devices allocated by the dynamic address allocation module; and the number of the first and second groups,
the bus arbiter obtains a read-write control signal from a signal from the master device, judges whether the master device performs a read operation or a write operation on the slave device, sends a data signal of the slave device to the master device through the communication channel if the master device performs the read operation, and sends the data signal of the master device to the slave device through the communication channel if the master device performs the write operation.
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