CN106610906A - Data access method and bus - Google Patents
Data access method and bus Download PDFInfo
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- CN106610906A CN106610906A CN201510707927.3A CN201510707927A CN106610906A CN 106610906 A CN106610906 A CN 106610906A CN 201510707927 A CN201510707927 A CN 201510707927A CN 106610906 A CN106610906 A CN 106610906A
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- main frame
- slave
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- address
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
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Abstract
An embodiment of the invention discloses a data access method. The data access method comprises the steps of receiving an access request sent by at least one host, wherein the access request carries an access address corresponding to at least one host; determining a first host from the at least one host; determining whether the first host corresponds to a target slave or not in at least one slave according to an access address of the first host and an address range of the at least one preset slaves, wherein the access address of the first host is in the address range of the target slave; and when it is determined that the first host corresponds to the target slave, judging whether the access request of the first host to the target slave is legal or not, and judging whether the first host accesses data of the target slave or not. An embodiment of the invention furthermore provides a bus.
Description
Technical field
The present invention relates to the digital integrated electronic circuit IC designing techniques in the communications field, more particularly to a kind of visit of data
Ask method and bus.
Background technology
With the development of SOC(system on a chip) (SoC, System On Chip) technology, the work(of a core Embedded
Can module it is also more and more, and modules are for the visiting demand also more and more higher of memorizer, therefore, piece
Upper bus seems extremely important in chip architecture, and on-chip bus realize control of the main frame to each slave on piece
It is the indispensable part of SOC(system on a chip).At present many chips are designed with Advanced Microcontroller Bus system
Height in (AMBA, Advanced Microcontroller Bus Architecture) On-chip bus agreement
Level high performance bus (AHB, Advanced High Performance Bus) agreement or advanced peripheral bus
(APB, Advanced Peripheral Bus) agreement.
Prior art does not generally support the security function with slave, to realize to AHB or APB agreements
The management of slave, at present conventional method is to utilize NIC301/400, but this kind of bus matrix code is complicated,
It is not easy to search problem；By taking ahb bus as an example, as shown in figure 1, NIC301/400 can be by host side
Into bus protocol (AXI, Advanced eXtensible Interface), reconvert is into from generator terminal for protocol conversion
Agreement, through agreement transfer, the reduction of access efficiency can be caused, this is for the slave that many efficiency have high demands
For be a big bottleneck；And NIC301/400 inside has a GPV, for configuring related slave
Security attribute etc., will occupy the address space of 1M, and this is the waste to address space；Complicated agreement turns
Change and introduce more logics so that sequential is deteriorated.
The content of the invention
To solve above-mentioned technical problem, the embodiment of the present invention is expected to provide a kind of data access method and bus,
Bus matrix logic can be reduced, the efficiency of transmission of bus is improve, the complexity of bus system is reduced.
The technical scheme is that what is be achieved in that：
The embodiment of the present invention provides a kind of data access method, and methods described includes：
The access request of at least one main frame transmission is received, at least one main frame is carried in the access request
Reference address；
Determine the first main frame from least one main frame；
According to the reference address and the address realm of default at least one slave of the first main frame, from least one
The whether corresponding target slave of first main frame is determined in slave, the reference address of first main frame is described
In the address realm of target slave；
When it is determined that first main frame corresponds to the target slave, judge first main frame to the target
Whether the access request of slave is legal, and then judges whether first main frame is realized to the target slave
Data access.
In such scheme, the secure access state of the first main frame is also carried in the access request, described
The secure access state of one main frame includes：It is secure and non-secure；It is described to work as determination the first main frame correspondence institute
When stating target slave, judge whether first main frame is legal to the access request of the target slave, including：
When it is determined that first main frame corresponds to the target slave, and the secure access state of first main frame
For it is safe when, judge that first main frame is legal to the access request of the target slave；
When it is determined that first main frame corresponds to the target slave, and the secure access state of first main frame
For it is non-security when, obtain target slave secure address scope；When the reference address of first main frame does not exist
When in the range of the secure address of the target slave, access of first main frame to the target slave is judged
Request is legal；When the reference address of first main frame is in the range of the secure address of the target slave,
Judge that first main frame is illegal to the access request of the target slave.
In such scheme, it is described determine from least one slave first main frame whether corresponding target from
After machine, methods described also includes：
When it is determined that first main frame does not correspond to the target slave, judge first main frame to slave
Access request is illegal, interrupts data access of first main frame to the slave.
It is described to judge whether first main frame realizes that the data to the target slave are visited in such scheme
Ask, including：
When judging first main frame to the access request of the target slave for legal, transmission described first
Access data of the main frame to the target slave；
When judging first main frame to the access request of the target slave for illegal, interrupt described first
Data access of the main frame to the target slave.
In such scheme, also carry in the access request protocol type and the target of the first main frame from
The protocol type of machine；It is described to determine from least one main frame after the first main frame, it is described according to first
The address realm of the reference address of main frame and default at least one slave, determines institute from least one slave
Before stating the whether corresponding target slave of the first main frame, methods described also includes：
When the protocol type of first main frame is inconsistent with the protocol type of the target slave, will be described
The protocol type of the first main frame is converted to the protocol type of the target slave.
The embodiment of the present invention provides a kind of bus, and the bus includes：
Arbitration unit, for receiving the access request that at least one main frame sends, carries in the access request
The corresponding reference address of at least one main frame；And the first main frame is determined from least one main frame, and
The reference address of the first main frame is exported to address decoding unit；
The address decoding unit, for the reference address of the first main frame that received according to the arbitration unit and
The address realm of default at least one slave, determines whether first main frame is right from least one slave
Target slave, the reference address of first main frame is answered to export in the address realm of the target slave
Determine result to security managing unit；
The security managing unit, for when the determination result be first main frame correspondence target from
During machine, judge whether first main frame is legal to the access request of the target slave, and then judge described
Whether the first main frame realizes the data access to the target slave.
In above-mentioned bus, the peace of the first main frame is also carried in the access request that the arbitration unit is received
Full access state, the secure access state of first main frame includes：It is secure and non-secure；
The security managing unit, specifically for determining the first main frame correspondence when the address decoding unit
The target slave, and the secure access state of first main frame for it is safe when, judge first main frame
It is legal to the access request of the target slave；And when the address decoding unit determines first main frame
The correspondence target slave, and the secure access state of first main frame for it is non-security when, obtain target from
The secure address scope of machine, when the reference address of first main frame is not in the secure address of the target slave
In the range of when, judge that first main frame is legal to the access request of the target slave；As the described first master
When the reference address of machine is in the range of the secure address of the target slave, judge first main frame to described
The access request of target slave is illegal.
In above-mentioned bus, the security managing unit is additionally operable to described institute be determined from least one slave
After stating the whether corresponding target slave of the first main frame, when it is determined that first main frame does not correspond to the target slave
When, judge that first main frame is illegal to the access request of slave, interrupt first main frame to it is described from
The data access of machine.
In above-mentioned bus, the security managing unit judges first main frame to institute also particularly useful for working as
When the access request for stating target slave is legal, access number of first main frame to the target slave is transmitted
According to；When it is determined that first main frame to the access request of the target slave for it is illegal when, interrupt described first
Data access of the main frame to the target slave.
In above-mentioned bus, the bus also includes：Conversion unit of protocol；Also carry in the access request
The protocol type of the protocol type of the first main frame and the target slave；
The conversion unit of protocol, for the arbitration unit the first master is determined from least one main frame
After machine, the address decoding unit is according to the reference address of the first main frame and default at least one slave
Address realm, before the whether corresponding target slave of first main frame is determined from least one slave, works as institute
State the first main frame protocol type it is inconsistent with the protocol type of the target slave when, by first main frame
Protocol type be converted to the protocol type of the target slave.
A kind of data access method and bus are embodiments provided, bus is led by receiving at least one
The access request that machine sends, carries the corresponding reference address of at least one main frame in the access request；From at least
Determine the first main frame in one main frame；According to the reference address of the first main frame and default at least one slave
Address realm, determines the whether corresponding target slave of the first main frame from least one slave, first main frame
Reference address is in the address realm of the target slave；When it is determined that the first main frame corresponds to target slave, judge
Whether the first main frame is legal to the access request of target slave, and then judges whether the first main frame is realized to target
The data access of slave.Using above-mentioned technic relization scheme, due to being provided with safety management function in bus,
Support that quantity and protocol type that multigroup main frame accesses multigroup slave, main frame and slave can be carried out as needed
Configuration；Bus can voluntarily carry out safety management, it is not necessary to internal unnecessary protocol conversion and register cell,
Bus matrix logic can be reduced, the efficiency of transmission of bus is improve, the complexity of bus system is reduced.
Description of the drawings
Fig. 1 is the bus system block diagram of prior art；
Fig. 2 is a kind of flow chart one of data access method provided in an embodiment of the present invention；
Fig. 3 is the division schematic diagram of slave addresses scope provided in an embodiment of the present invention；
Fig. 4 is the logical circuitry of exemplary security managing unit provided in an embodiment of the present invention；
Fig. 5 is the generation figure of legal logical signal provided in an embodiment of the present invention；
Fig. 6 is the block diagram of bus access provided in an embodiment of the present invention；
Fig. 7 is a kind of flowchart 2 of data access method provided in an embodiment of the present invention；
Fig. 8 is a kind of flow chart 3 of data access method provided in an embodiment of the present invention；
Fig. 9 is a kind of structural representation one of bus provided in an embodiment of the present invention；
Figure 10 is a kind of structural representation two of bus provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, it is fully described by.
Embodiment one
The embodiment of the present invention provides a kind of data access method, as shown in Fig. 2 the method can include：
S101, bus receive the access request that at least one main frame sends, and at least one is carried in the access request
The corresponding reference address of individual main frame.
In embodiments of the present invention, the structure of Intrusion Detection based on host, bus and slave, carries out number of the main frame to slave
According to access.The embodiment of the present invention can be applied on matrix/bus bridge, specially at least one Master
Data access process between (main frame) and at least one Slave (slave), i.e. at least one main frame pass through
Bus, at least one slave data access is carried out.
Specifically, at least one main frame sends access request to bus, and bus determination selects which main frame is carried out
Access to slave.That is, bus receives the access request that at least one main frame sends, wherein, the access please
Seek the reference address of the slave desired access to including each main frame at least one main frame.
It should be noted that the arbitration unit in bus carries out the selection of the first main frame, specific selection course
Can realize that here is not described in detail by prior art.
S102, bus determine the first main frame from least one main frame.
Bus is received after the access request that at least one main frame sends, and the bus is selected from least one main frame
A main frame is selected as the first main frame to carry out access request of first main frame to slave.
Specifically, bus determines the secure access state of the first main frame and the first main frame from least one main frame.
Wherein, the arbitration unit of bus determines the first main frame from least one main frame, and then, first main frame is obtained
Obtain access right.
It should be noted that each main frame can have a safety signal to indicate that the transmission of respective hosts initiation is
Safe or non-security, safety signal in embodiments of the present invention indicates the secure access that can be main frame
State.
Further, the secure access state of a main frame can represent that exemplary, 0 can by 0 and 1
To represent safety, 1 can represent non-security.The safety of the secure access state of specific main frame with it is non-security
Representation, the embodiment of the present invention is not restricted.
Exemplary, 5 main frames will carry out data access to slave, therefore, 5 main frames send respectively access
Ask to bus, at this moment, the arbitration unit of the bus just selects one of them in 5 main frames by arbitration
Main frame (the first main frame) obtains the access right for accessing slave.
S103, bus according to the reference address of the first main frame and the address realm of default at least one slave,
The whether corresponding target slave of first main frame, the reference address of first main frame are determined from least one slave
In the address realm of the target slave.
It should be noted that each slave in the embodiment of the present invention has the address realm of slave, each from
What the address realm of machine was to determine, i.e., one slave one address realm of correspondence, in this address realm
Reference address all corresponds to said one slave.
Specifically, bus is according to the reference address of the first main frame and the address realm of default at least one slave,
The whether corresponding target slave of reference address of first main frame, first main frame are determined from least one slave
Reference address in the address realm of the target slave, i.e., the reference address of the first main frame can be with least one
The address realm correspondence of a slave in the address realm of individual slave, the corresponding slave is target slave.
The address decoding unit of bus is by the address of the reference address of the first main frame and default at least one slave
Scope is contrasted one by one, and the whether corresponding mesh of reference address of first main frame is determined from least one slave
Mark slave, specifically, the reference address of the first main frame can be with the address realm of at least one slave
The address realm of individual slave is target slave to corresponding slave during correspondence.
Further, when the first main frame reference address default at least one slave slave
It is the first main frame target slave to be accessed in the address realm of a slave when in address realm.When
The reference address of one main frame is not in the address realm of any one slave of default at least one slave
When (i.e. not in the address realm of any one slave), the reference address for characterizing the first main frame is address blank,
The reference address is not the address of slave.
Exemplary, when the reference address of the first main frame is 10, due to the address realm of at least one slave
Altogether include 15-50, then the reference address of the first main frame not in the address realm of this at least one slave, i.e.,
The reference address of the first main frame is sky.
S104, when it is determined that the first main frame correspondence the target slave when, bus judge the first main frame to target from
Whether the access request of machine is legal, and then judges whether first main frame realizes the data access to target slave.
Bus according to the reference address of the first main frame and the address realm of default at least one slave, from least
After the whether corresponding target slave of reference address of first main frame is determined in one slave, when it is determined that the first master
During the machine correspondence target slave, bus judges whether the first main frame is legal to the access request of target slave,
So as to judge whether first main frame realizes the data access to target slave.
Optionally, in embodiments of the present invention, each slave has single address realm and secure address
Scope, can individually limit the address realm and secure address scope of slave, slave can be configured to into whole
Several classes such as safety, all non-security, Partial security parts are non-security.Specifically, slave is configured safely
Location scope can be done by external system configuration module, and the secure address scope of a slave be it is adjustable,
The secure address scope of the slave i.e. in the address realm of a slave and the non-security address realm of slave
Division is variable, as shown in figure 3, for the division schematic diagram of slave addresses scope.
Optionally, in embodiments of the present invention, bus can be Advanced High-Performance Bus (AHB, Advanced
High Performance Bus), or peripheral bus (APB, Advanced Peripheral Bus).
Wherein, when bus is ahb bus, the address realm of the slave in the embodiment of the present invention can safely, entirely
A few class address realms such as portion is non-security, Partial security part is non-security；When bus is APB buses, the present invention
The address realm of the slave in embodiment can safely, whole a few class address realms such as non-security.
Secure access state due to also carrying the first main frame in above-mentioned access request, the safety of first main frame
Access state includes：It is secure and non-secure.Therefore, when it is determined that the first main frame corresponds to target slave, bus
Judge whether first main frame is legal specially to the access request of the target slave：When it is determined that the first main frame pair
Answer target slave, and the secure access state of first main frame for it is safe when, bus judges first main frame pair
The access request of the target slave is legal.
Or, when it is determined that the first main frame correspondence target slave, and the secure access state of first main frame is non-
When safe, bus obtains the secure address scope of target slave；When the reference address of the first main frame is not in the mesh
When in the range of the secure address of mark slave, bus judges that first main frame is closed to the access request of the target slave
Method；When the reference address of first main frame is in the range of the secure address of the target slave, bus judges should
First main frame is illegal to the access request of the target slave.
Further, the determination result of the main frame of above-mentioned determination first correspondence target slave can be by the address of bus
Decoding unit carrys out labelling in the form of the selection signal of slave, and the selection signal of specific slave can be by 0 He
1 represents, exemplary, and 0 represents the first main frame correspondence target slave, and the target slave is first main frame
The slave to be accessed；1 represents that the first main frame does not correspond to target slave, that is to say, that what the first main frame to be accessed
Reference address is not belonging to any one slave at least one slave, therefore, the reference address of the first main frame
It is address blank；Specifically, the representation of slave selection signal, the embodiment of the present invention is not restricted.
Further, bus judges whether first main frame is realized being specially the data access of target slave：
When judging the first main frame to the access request of target slave for legal, bus transfer first main frame is to the mesh
The access data of mark slave.When judging the first main frame to the access request of target slave for illegal, in bus
Break the data access of first main frame to the target slave.
It should be noted that the security managing unit of bus obtains the secure address scope of target slave, and root
According to the secure access state of the secure address scope, the reference address of the first main frame and the first main frame of target slave,
Determine whether the first main frame is legal to the access request of target slave, it is right so as to judge whether the first main frame is realized
The data access of target slave.Said process be bus security managing unit logic circuit realizing,
As shown in figure 4, for the logical circuitry of exemplary security managing unit, Addrlegal is safety management list
The logic circuit output signal of unit, Legal_reg is deposit feedback signal.
Specifically, generally speaking, by the generation figure of legal logical signal (legal) as shown in Figure 5,
Understand：(Trans_req is used to characterize the transmission of the first main frame in the case of current the first main frame transmission normally
Whether normal, represented by 0 and 1), legal logical signal be by target slave secure address scope, first
What the secure access state of the reference address of main frame and the first main frame was determined by logical operationss.Wherein, it is legal
Logical signal can be represented by 0 and 1, exemplary, when legal logical signal is 0, represent that first leads
Machine is legal to the access request of target slave；When legal logical signal is 1, represent the first main frame to target
The access request of slave is illegal.The representation of specific legal logical signal, the embodiment of the present invention is not limited
System.
It should be noted that overall, by the secure address scope of target slave, the first main frame
The secure access state of reference address and the first main frame determines that the true value of legal logical signal is closed by logical operationss
System is as follows：
(1), security host (the secure access state of main frame the is safety) access safety address (visit of main frame
Ask address in the range of the secure address of slave), legal logical signal is legal；
(2), security host accesses non-security address (non-security address model of the reference address of main frame in slave
In enclosing), legal logical signal is legal；
(3), non-security main frame (the secure access state of main frame is non-security) access safety address, legal
Logical signal is illegal；
(4), non-security main frame accesses non-security address, and legal logical signal is legal.
Wherein, the secure address scope that the address realm of slave deducts the slave is the non-security address of the slave
Scope.
Further, as shown in fig. 6, the security managing unit of bus exports legal logical signal, by figure
4 logic circuit realizes access of first main frame to target slave, and the first main frame is terminated by termination signal
Transmission to the data access of target slave, i.e., legal then the first main frame can pass through " trapezoidal " access target
Slave, non-rule by termination signal by idle signal be assigned to slave (terminate the first main frame access target from
Machine).
Further, after S103, as shown in fig. 7, a kind of data access side provided in an embodiment of the present invention
Method can also include：S105.It is specific as follows：
S105, when it is determined that the first main frame do not correspond to target slave when, bus judges first main frame to the target
The access request of slave is illegal, and the bus interrupts the data access of first main frame to the target slave.
When it is determined that the reference address of the first main frame does not correspond to target slave, i.e., when the selection signal of slave is 1,
Bus determines that first main frame is illegal to the access request of slave, and then, the bus interrupts first main frame
Data access to the slave.
Further, after S102, and before S103, as shown in figure 8, provided in an embodiment of the present invention
Data access method can also include：S106.It is specific as follows：
S106, when the protocol type of the first main frame and the inconsistent protocol type of target slave, bus is by
The protocol type of one main frame is converted to the protocol type of target slave.
It should be noted that when main frame carries out data access by bus and target slave, the protocol class of main frame
Type need it is consistent with the protocol type of the target slave for being accessed, therefore, when the first main frame protocol type and
When the protocol type of target slave is inconsistent, S106 is performed.If when the first main frame protocol type and target from
When the protocol type of machine is consistent, then without carrying out protocol conversion.
It is understood that each slave has single address and secure address model in the embodiment of the present invention
Enclose, can individually limit the address realm and secure address scope of slave, slave can be configured to whole peaces
Entirely, all non-security, Partial security part is non-security, and by security managing unit security attribute is configured, from
And significantly facilitate user use also cause route bus it is easier, reduce the area of chip, save into
This.
A kind of data access method that the embodiment of the present invention is provided, bus is sent out by receiving at least one main frame
The access request sent, carries the corresponding reference address of at least one main frame in the access request；From at least one
The first main frame is determined in main frame；Reference address and the address of default at least one slave according to the first main frame
Scope, determines the whether corresponding target slave of the first main frame, the access of first main frame from least one slave
Address is in the address realm of the target slave；When it is determined that the first main frame corresponds to target slave, first is judged
Whether main frame is legal to the access request of target slave, and then judges whether the first main frame is realized to target slave
Data access.Using above-mentioned technic relization scheme, due to being provided with safety management function in bus, support
Multigroup main frame accesses the quantity and protocol type of multigroup slave, main frame and slave and can be configured as needed；
Bus can voluntarily carry out safety management, it is not necessary to internal unnecessary protocol conversion and register cell, can
Bus matrix logic is reduced, the efficiency of transmission of bus is improve, the complexity of bus system is reduced.
Embodiment two
As shown in figure 9, the embodiment of the present invention provides a kind of bus 1, the bus 1 can include：
Arbitration unit 10, for receiving the access request that at least one main frame sends, takes in the access request
The corresponding reference address of at least one main frame of band；And determine the first main frame from least one main frame, with
And the reference address of the first main frame of output is to address decoding unit 11.
Shown address decoding unit 11, the access of the first main frame for being received according to the arbitration unit 10
Address and the address realm of default at least one slave, determine first main frame from least one slave
Whether corresponding target slave, the reference address of first main frame in the address realm of the target slave,
And determination result is exported to security managing unit 12.
The security managing unit 12, for determining that result is first main frame correspondence target when described
During slave, judge whether first main frame is legal to the access request of the target slave, and then judge institute
State the data access whether the first main frame is realized to the target slave.
Optionally, the safety visit of the first main frame is also carried in the access request that the arbitration unit 10 is received
State is asked, the secure access state of first main frame includes：It is secure and non-secure.
The security managing unit 12, specifically for determining first master when the address decoding unit 11
The machine correspondence target slave, and the secure access state of first main frame for it is safe when, judge described the
One main frame is legal to the access request of the target slave；And described in determining when the address decoding unit 11
The first main frame correspondence target slave, and the secure access state of first main frame for it is non-security when, obtain
The secure address scope of target slave is taken, when the reference address of first main frame is not in the target slave
When in the range of secure address, judge that first main frame is legal to the access request of the target slave；Work as institute
When stating the reference address of the first main frame in the range of the secure address of the target slave, first master is judged
Machine is illegal to the access request of the target slave.
Optionally, the security managing unit 12, is additionally operable to described described the be determined from least one slave
After the whether corresponding target slave of one main frame, when it is determined that first main frame does not correspond to the target slave,
Judge that first main frame is illegal to the access request of slave, interrupt first main frame to the slave
Data access.
Optionally, the security managing unit 12, judges first main frame to the mesh also particularly useful for working as
When the access request of mark slave is legal, access data of first main frame to the target slave are transmitted；
When it is determined that first main frame is illegal to the access request of the target slave, interrupting first main frame pair
The data access of the target slave.
Optionally, as shown in Figure 10, the bus 1 also includes：Conversion unit of protocol 13；The access
The protocol type of the first main frame and the protocol type of the target slave are also carried in request.
The conversion unit of protocol 13, determines for the arbitration unit 10 from least one main frame
After first main frame, reference address and default at least of the address decoding unit 11 according to the first main frame
The address realm of individual slave, determine from least one slave first main frame whether corresponding target slave it
Before, when the protocol type of first main frame is inconsistent with the protocol type of the target slave, will be described
The protocol type of the first main frame is converted to the protocol type of the target slave.
It should be noted that because when the protocol type of the first main frame is consistent with the protocol type of target slave,
The reference address of the first main frame could be sent to address decoding unit 11, therefore, when the agreement of the first main frame
When type is inconsistent with the protocol type of target slave, there is conversion unit of protocol 13, arbitration unit 10 leads to
Cross conversion unit of protocol 13 reference address of the first main frame to be sent to address decoding unit 11.If when first
When the protocol type of main frame is consistent with the protocol type of target slave, it is not necessary to there is conversion unit of protocol 13.
A kind of bus that the embodiment of the present invention is provided, bus is by receiving the access that at least one main frame sends
Request, carries the corresponding reference address of at least one main frame in the access request；From at least one main frame really
Fixed first main frame；According to the reference address and the address realm of default at least one slave of the first main frame, from
The whether corresponding target slave of the first main frame is determined at least one slave, the reference address of first main frame is at this
In the address realm of target slave；When it is determined that the first main frame corresponds to target slave, judge the first main frame to mesh
Whether the access request of mark slave is legal, and then judges whether the first main frame realizes that the data to target slave are visited
Ask.Using above-mentioned technic relization scheme, due to being provided with safety management function in bus, multigroup main frame is supported
Accessing the quantity and protocol type of multigroup slave, main frame and slave can be configured as needed；Bus can
Voluntarily to carry out safety management, it is not necessary to internal unnecessary protocol conversion and register cell, can reduce total
Wire matrix logic, improves the efficiency of transmission of bus, reduces the complexity of bus system.
Those skilled in the art are it should be appreciated that embodiments of the invention can be provided as method, system or meter
Calculation machine program product.Therefore, the present invention can using hardware embodiment, software implementation or with reference to software and
The form of the embodiment of hardware aspect.And, the present invention can be adopted and wherein include calculating at one or more
Machine usable program code, data, the computer-usable storage medium of the buffer status of function register (bag
Include but be not limited to disk memory and optical memory etc.) or function slave, such as UART, IIC etc. are outer
If depositor, the form of the computer program of upper enforcement.
The present invention is with reference to method according to embodiments of the present invention, equipment (system) and computer program
Flow chart and/or block diagram describing.It should be understood that can be by computer program instructions flowchart and/or side
The knot of each flow process and/or square frame and flow chart and/or the flow process in block diagram and/or square frame in block diagram
Close.Can provide these computer program instructions to general purpose computer, special-purpose computer, Embedded Processor or
The processor of other programmable data processing devices is producing a machine so that by computer or other can
The instruction of the computing device of programming data processing equipment is produced for realizing in one flow process or multiple of flow chart
The device of the function of specifying in one square frame of flow process and/or block diagram or multiple square frames.
These computer program instructions may be alternatively stored in can guide computer or other programmable data processing devices
In the computer-readable memory for working in a specific way so that in being stored in the computer-readable memory
Instruction produces the manufacture for including command device, and the command device is realized in one flow process of flow chart or multiple streams
The function of specifying in one square frame of journey and/or block diagram or multiple square frames.
These computer program instructions also can be loaded in computer or other programmable data processing devices, made
Obtain and series of operation steps performed on computer or other programmable devices to produce computer implemented process,
So as to the instruction performed on computer or other programmable devices is provided for realizing in one flow process of flow chart
Or specify in one square frame of multiple flow processs and/or block diagram or multiple square frames function the step of.
The above, only presently preferred embodiments of the present invention is not intended to limit the protection model of the present invention
Enclose.
Claims (10)
1. a kind of data access method, it is characterised in that methods described includes：
The access request of at least one main frame transmission is received, at least one main frame is carried in the access request
Reference address；
Determine the first main frame from least one main frame；
According to the reference address and the address realm of default at least one slave of the first main frame, from least one
The whether corresponding target slave of first main frame is determined in slave, the reference address of first main frame is described
In the address realm of target slave；
When it is determined that first main frame corresponds to the target slave, judge first main frame to the target
Whether the access request of slave is legal, and then judges whether first main frame is realized to the target slave
Data access.
2. method according to claim 1, it is characterised in that first is also carried in the access request
The secure access state of main frame, the secure access state of first main frame includes：It is secure and non-secure；Institute
State when it is determined that first main frame correspondence target slave when, judge first main frame to the target from
Whether the access request of machine is legal, including：
When it is determined that first main frame corresponds to the target slave, and the secure access state of first main frame
For it is safe when, judge that first main frame is legal to the access request of the target slave；
When it is determined that first main frame corresponds to the target slave, and the secure access state of first main frame
For it is non-security when, obtain target slave secure address scope；When the reference address of first main frame does not exist
When in the range of the secure address of the target slave, access of first main frame to the target slave is judged
Request is legal；When the reference address of first main frame is in the range of the secure address of the target slave,
Judge that first main frame is illegal to the access request of the target slave.
3. method according to claim 1, it is characterised in that described to determine from least one slave
After the whether corresponding target slave of first main frame, methods described also includes：
When it is determined that first main frame does not correspond to the target slave, judge first main frame to slave
Access request is illegal, interrupts data access of first main frame to the slave.
4. method according to claim 2, it is characterised in that described whether to judge first main frame
The data access to the target slave is realized, including：
When judging first main frame to the access request of the target slave for legal, transmission described first
Access data of the main frame to the target slave；
When judging first main frame to the access request of the target slave for illegal, interrupt described first
Data access of the main frame to the target slave.
5. the method according to any one of Claims 1-4, it is characterised in that in the access request
Also carry the protocol type of the first main frame and the protocol type of the target slave；It is described from described at least one
After the first main frame is determined in main frame, the reference address according to the first main frame and default at least one from
The address realm of machine, before the whether corresponding target slave of first main frame is determined from least one slave,
Methods described also includes：
When the protocol type of first main frame is inconsistent with the protocol type of the target slave, will be described
The protocol type of the first main frame is converted to the protocol type of the target slave.
6. a kind of bus, it is characterised in that the bus includes：
Arbitration unit, for receiving the access request that at least one main frame sends, carries in the access request
The corresponding reference address of at least one main frame；And the first main frame is determined from least one main frame, and
The reference address of the first main frame is exported to address decoding unit；
The address decoding unit, for the reference address of the first main frame that received according to the arbitration unit and
The address realm of default at least one slave, determines whether first main frame is right from least one slave
Target slave, the reference address of first main frame is answered to export in the address realm of the target slave
Determine result to security managing unit；
The security managing unit, for when the determination result be first main frame correspondence target from
During machine, judge whether first main frame is legal to the access request of the target slave, and then judge described
Whether the first main frame realizes the data access to the target slave.
7. bus according to claim 6, it is characterised in that the visit that the arbitration unit is received
The secure access state that the first main frame is also carried in request is asked, the secure access state of first main frame includes：
It is secure and non-secure；
The security managing unit, specifically for determining the first main frame correspondence when the address decoding unit
The target slave, and the secure access state of first main frame for it is safe when, judge first main frame
It is legal to the access request of the target slave；And when the address decoding unit determines first main frame
The correspondence target slave, and the secure access state of first main frame for it is non-security when, obtain target from
The secure address scope of machine, when the reference address of first main frame is not in the secure address of the target slave
In the range of when, judge that first main frame is legal to the access request of the target slave；As the described first master
When the reference address of machine is in the range of the secure address of the target slave, judge first main frame to described
The access request of target slave is illegal.
8. bus according to claim 6, it is characterised in that
The security managing unit, is additionally operable to described first main frame be determined from least one slave whether
After correspondence target slave, when it is determined that first main frame does not correspond to the target slave, described the is judged
One main frame is illegal to the access request of slave, interrupts data access of first main frame to the slave.
9. bus according to claim 7, it is characterised in that
The security managing unit, also particularly useful for working as visit of first main frame to the target slave is judged
Ask request for it is legal when, transmit the access data of first main frame to the target slave；When it is determined that described
First main frame is to when the access request of the target slave is illegal, interrupting first main frame to the target
The data access of slave.
10. the bus according to any one of claim 6 to 9, it is characterised in that the bus is also wrapped
Include：Conversion unit of protocol；Also carry in the access request protocol type and the target of the first main frame from
The protocol type of machine；
The conversion unit of protocol, for the arbitration unit the first master is determined from least one main frame
After machine, the address decoding unit is according to the reference address of the first main frame and default at least one slave
Address realm, before the whether corresponding target slave of first main frame is determined from least one slave, works as institute
State the first main frame protocol type it is inconsistent with the protocol type of the target slave when, by first main frame
Protocol type be converted to the protocol type of the target slave.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510707927.3A CN106610906A (en) | 2015-10-27 | 2015-10-27 | Data access method and bus |
| PCT/CN2016/099411 WO2017071429A1 (en) | 2015-10-27 | 2016-09-19 | Data access method and bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510707927.3A CN106610906A (en) | 2015-10-27 | 2015-10-27 | Data access method and bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106610906A true CN106610906A (en) | 2017-05-03 |
Family
ID=58615131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510707927.3A Withdrawn CN106610906A (en) | 2015-10-27 | 2015-10-27 | Data access method and bus |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106610906A (en) |
| WO (1) | WO2017071429A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109818980A (en) * | 2019-03-21 | 2019-05-28 | 中国铁塔股份有限公司 | A kind of communication means and device |
| CN113468098A (en) * | 2020-03-30 | 2021-10-01 | 芯海科技（深圳）股份有限公司 | Secure access method, integrated circuit and computer readable storage medium |
| CN116955265A (en) * | 2023-09-20 | 2023-10-27 | 合肥创发微电子有限公司 | I2C bus system communication method, device, equipment and medium |
| CN117171065A (en) * | 2023-11-02 | 2023-12-05 | 摩尔线程智能科技(北京)有限责任公司 | Address management method, address management device, electronic equipment and storage medium |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115408707B (en) * | 2022-11-03 | 2023-03-24 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method, device and system, electronic equipment and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101331469A (en) * | 2005-12-14 | 2008-12-24 | 汤姆森特许公司 | Method for accessing to a data transmission bus, corresponding device and system |
| CN101937412A (en) * | 2010-09-14 | 2011-01-05 | 硅谷数模半导体（北京）有限公司 | System on chip and access method thereof |
| CN102591824A (en) * | 2011-12-27 | 2012-07-18 | 深圳国微技术有限公司 | DMA (direct memory access) controller for controlling security data transfer in SOC (system on a chip) chip system |
| CN103546354A (en) * | 2013-10-22 | 2014-01-29 | 天津七一二通信广播有限公司 | Communicating method being based on Internet of Things electric temperature measurement equipment and enabling RS485 bus and CAN bus to be compatible |
| CN104899175A (en) * | 2014-03-04 | 2015-09-09 | 深圳市中兴微电子技术有限公司 | Safety access control method and device based on on-chip bus protocol |
-
2015
- 2015-10-27 CN CN201510707927.3A patent/CN106610906A/en not_active Withdrawn
-
2016
- 2016-09-19 WO PCT/CN2016/099411 patent/WO2017071429A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101331469A (en) * | 2005-12-14 | 2008-12-24 | 汤姆森特许公司 | Method for accessing to a data transmission bus, corresponding device and system |
| CN101937412A (en) * | 2010-09-14 | 2011-01-05 | 硅谷数模半导体（北京）有限公司 | System on chip and access method thereof |
| CN102591824A (en) * | 2011-12-27 | 2012-07-18 | 深圳国微技术有限公司 | DMA (direct memory access) controller for controlling security data transfer in SOC (system on a chip) chip system |
| CN103546354A (en) * | 2013-10-22 | 2014-01-29 | 天津七一二通信广播有限公司 | Communicating method being based on Internet of Things electric temperature measurement equipment and enabling RS485 bus and CAN bus to be compatible |
| CN104899175A (en) * | 2014-03-04 | 2015-09-09 | 深圳市中兴微电子技术有限公司 | Safety access control method and device based on on-chip bus protocol |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109818980A (en) * | 2019-03-21 | 2019-05-28 | 中国铁塔股份有限公司 | A kind of communication means and device |
| CN113468098A (en) * | 2020-03-30 | 2021-10-01 | 芯海科技（深圳）股份有限公司 | Secure access method, integrated circuit and computer readable storage medium |
| CN116955265A (en) * | 2023-09-20 | 2023-10-27 | 合肥创发微电子有限公司 | I2C bus system communication method, device, equipment and medium |
| CN116955265B (en) * | 2023-09-20 | 2023-12-05 | 合肥创发微电子有限公司 | I2C bus system communication method, device, equipment and medium |
| CN117171065A (en) * | 2023-11-02 | 2023-12-05 | 摩尔线程智能科技(北京)有限责任公司 | Address management method, address management device, electronic equipment and storage medium |
| CN117171065B (en) * | 2023-11-02 | 2024-03-01 | 摩尔线程智能科技(北京)有限责任公司 | Address management method, address management device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2017071429A1 (en) | 2017-05-04 |
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Application publication date: 20170503 |