CN203102265U - Solid state disk (SSD) control chip - Google Patents
Solid state disk (SSD) control chip Download PDFInfo
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- CN203102265U CN203102265U CN 201320026322 CN201320026322U CN203102265U CN 203102265 U CN203102265 U CN 203102265U CN 201320026322 CN201320026322 CN 201320026322 CN 201320026322 U CN201320026322 U CN 201320026322U CN 203102265 U CN203102265 U CN 203102265U
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Abstract
The utility model discloses a solid state disk (SSD) control chip. The SSD control chip comprises an SSD standard interface, a universal serial bus (USB) interface and a Flash memory controller. The SSD standard interface, the USB interface and the Flash memory controller are connected onto a bus and occupy the bus through a configured bus arbiter so as to be used for communication connection. Meanwhile, an SM1 cryptographic algorithm (SM1) encryption and decryption module connected onto the bus is configured so that devices used for the communication connection can be arbitrated and connected through the SM1 encryption and decryption module when an encryption and decryption function is utilized. The SSD control chip is high in data storage safety under the condition of high data transmission speeds.
Description
Technical field
The utility model relates to a kind of SSD(Solid State Disk, solid state hard disc) control chip.
Background technology
SSD, promptly the hard disk made with solid-state electronic storage chip array of solid state hard disc is made up of control module and storage unit (FLASH chip or dram chip).Identical with common hard disk on the interface specification of solid state hard disc and definition, function and the using method is also fully consistent with common hard disk on product design and size.
A kind of SSD adopts NandFlash(and non-flash memory) carry out data storage and a kind of technology that reads, broken through the performance bottleneck of traditional mechanical hard disk, have high memory property.This SSD is because its storage medium is NandFlash, so it has just had similar advantage to NandFlash: light, storage density is big, low in energy consumption, antidetonation and temperature adaptation wide ranges, is considered to following main flow storage medium.
The problem that must relate to secure user data in the storer as storage medium, in order to guarantee safety of user data in the Flash storer, configuration control corresponding chip, in these control chips, the employing soft encryption that has promptly encrypt by the microprocessor in the use chip, but this cipher mode speed is slow, limit the access speed of data, be not suitable for high speed storing.Though discrete device is adopted in the employing hardware encryption that has, and need build the communication that hardware circuit carries out chip chamber, same like this can underspeeding also can increase power consumption simultaneously.
Summary of the invention
For this reason, the purpose of this utility model is to provide a kind of SSD control chip based on SM1 encryption and decryption module, has under the situation of higher data transmission rate, has high data storage security.
The utility model is by the following technical solutions:
A kind of SSD control chip, comprise SSD standard interface, USB interface and Flash memory controller, the bus arbiter that described SSD standard interface, USB interface and Flash memory controller are hung on a bus and pass through to be disposed is obtained occupying of bus, communicates to connect being used to; Simultaneously, dispose the SM1 encryption and decryption module that is hung on described bus, with when using encryption and decryption functions, the equipment that arbitration is used to communicate to connect connects via this SM1 encryption and decryption module.
As can be seen from the above technical solutions, according to the utility model, when needs need not the ciphered data operation, the bus arbiter arbitration is set up with the Flash memory controller as the SSD standard interface and is communicated by letter, carry out the data carrying, when the needs encryption function, SM1 encryption and decryption module is as the node that establishes a communications link, with data from after the SM1 algorithm for encryption, moving Flash memory controller end as SSD standard interface end, thereby make data storage have high data storage security.Adopt total line traffic control little, can guarantee that data transmission has higher speed the influence of speed.
Above-mentioned SSD control chip, the DMA that described SM1 encryption and decryption module and USB interface are equipped with the composition data link nodes utilizes the direct memory access (DMA) technology, improves the speed of data transmission.
Above-mentioned SSD control chip, described USB interface is furnished with registers group, is used to dispose USB interface to determine whether to use SM1 encryption and decryption module, can the Fast transforms functional mode.
Further, in order to improve the speed of data carryings, above-mentioned SSD control chip, described USB interface is the USB3.0 interface, and adds that by the USB3.0 Physical layer USB3.0 device controller constitutes.
Further, in order to reduce peripheral chip, the cost of subject of a lecture embedded system, above-mentioned SSD control chip, described bus is an internal bus, and the equipment on this bus of hanging over adopts the IP module and by overall package.
Preferably, above-mentioned SSD control chip, this control chip is embedded with the risc processor that is connected in described bus.
Description of drawings
Fig. 1 is the structure principle chart according to a kind of SSD control chip of the present utility model.
Embodiment
At first, about national cryptographic algorithm SM1, full name is SM1 cryptographic algorithm, promptly discusss close No. 1 algorithm, also claims the SCB2 algorithm;
The SM1 algorithm is a kind of commercial cipher grouping standard symmetry algorithm by the establishment of national Password Management office.This algorithm is the SM1 block cipher that national Password Management department examines, block length and key length all are 128 bits, algorithm security encryption strength and relevant software and hardware realize that performance is suitable with AES, this algorithm is open, only the form with IP nuclear (Intellectual Property core, intellectual property core) is present in the chip.
SM1 encryption and decryption module as shown in Figure 1 is a stone.Should know that IP kernel is one section hardware description language program with particular electrical circuit function, this program and integrated circuit technology are irrelevant, can be transplanted to and go the production integrated circuit (IC) chip in the different semiconductor technologies.And stone provides design phase terminal stage product: mask.To provide through the net sheet form of placement-and-routing completely, this stone had both had predictable, can also or buy the merchant and carry out optimization on power consumption and the size at special process simultaneously.Although stone is portable poor owing to lack dirigibility, owing to need not provide register to shift level (RTL) file, thereby be easier to realize the IP protection.
Deviser's main task is to finish complicated design in the cycle at official hour.Call IP kernel and can avoid the duplication of labour, alleviate slip-stick artist's burden greatly, therefore using IP kernel is a development trend.The title of IP kernel is derived from the hardware description language program, and final flow becomes integrated circuit for stone, and the actual traditionally circuit unit for IP kernel of industry is also referred to as IP.
IP can regard black box as, only need pay close attention to outside connection attribute when using, and needn't consider its inner structure.The easier quilt of example of macroscopic view is understood, and as network adapter (being commonly called as network interface card), need not to pay close attention to him and disposes which hardware, software or firmware, and the funtion part that only need utilize his interface place in circuit to constitute this circuit gets final product.
With reference to Figure of description 1, a kind of SSD control chip, it comprises the interface of coupling, and other additional devices, carry storer ROM etc. as sheet, as shown in Figure 1, be provided with bus, hang fully the taking of bus by the bus arbiter control bus, realize that as the driving by external command or by certain sequential control institute hangs taking fully.In such structure, the structure of coupling SSD control chip configuration is provided with SM1 encryption and decryption module, thereby, by the foundation of SM1 encryption and decryption module and selected interface channel, carry out the data carrying, be used to guarantee the security of data carrying.
As shown in Figure 1, it is a relatively complete structure, it is furnished with 32 risc processors, USB3.0 Physical layer, USB3.0 device controller, SM1 encryption and decryption module, Flash memory controller, standard solid state hard disk slave interface, interruptable controller, clock generator, DMA (Direct Memory Access, direct memory access (DMA)) controller, MEM controller (Memory Controller Hub), above-mentioned module all integrates, and connects by bus.Obviously, those skilled in the art can simplify equipment component wherein in view of the above, as clock generator, obviously can introduce external clock.Do as a wholely, the inventor thinks and can adopt as shown in Figure 1 than entire arrangement.
USB3.0 hypervelocity interface (the USB3.0 Physical layer adds USB3.0 device controller composition), SM1 encryption and decryption module, standard solid state hard disk slave interface, Flash memory controller, interruptable controller, clock generator, dma controller, MEM controller link together by bus and 32 risc processors.
In said structure, the solid state hard disc interface that is divided into USB3.0 interface and standard with the data-interface of outside is SATA, mSATA, PCIe or other standard interfaces at the solid state hard disc design for example.
When adopting USB3.0 to link to each other with main frame, the USB3.0 Physical layer adds that the USB3.0 device controller has constituted complete USB3.0 hypervelocity interface.The USB3.0 device controller both can initiatively occupy bus, also can be passive on bus transmitting and receiving data.The user can select whether data are carried out encryption and decryption by configuration USB3.0 device controller register.
When not using encryption function, the DMA that carries by the USB3.0 device controller moves the Flash memory controller to the high-speed data on the External cable (under the current techniques condition, mxm. is 5Gbps).
When using encryption function, SM1 encryption and decryption module through SM1 algorithm for encryption after is moved Flash memory controller with data from the USB3.0 device controller by the DMA that carries, and decrypting process is opposite.
When the solid state hard disc interface of the standard of employing linked to each other with hard disk management, standard solid state hard-disk interface Physical layer added that standard solid state hard disk slave unit controller has constituted complete solid state hard disc system.The slave unit controller both can initiatively occupy bus, also can be passive on bus transmitting and receiving data.The user can select whether data are carried out encryption and decryption by configuration standard solid state hard disc interface slave unit controller register.
When not using encryption function, the DMA that carries by the slave unit controller moves the Flash memory controller to the high-speed data on the External cable.
When using encryption function, SM1 encryption and decryption module through SM1 algorithm for encryption after is moved Flash memory controller with data from standard solid state hard disk slave unit controller by the DMA that carries, and decrypting process is opposite.
32 risc processors play the effect of microprocessor here, by resource on guiding of operation firmware program and the allotment sheet.In ROM, solidified 32 RISC(Reduced Instruction Set Computing, reduced instruction set computer) boot of processor.I-RAM SRAM is the instruction memory headroom of firmware program operation.D-RAM SRAM is firmware program required datarams space of when operation.Clock generator produces the clock of the required different frequency of system.Interruptable controller is used to control the generation of look-at-me.Flash Implementing Memory Controllers data are reliably managed correcting data error.
According to a kind of hypervelocity interface SSD control chip of said structure, adopt SoC(System on Chip, SOC (system on a chip) so towards the SSD storer) framework, the demand that is primarily aimed at the SSD storer is customized.Have following useful effect compared with prior art:
(1) by SM1 encryption and decryption module, promptly can use the close algorithm SM1 of state that data are protected, improve SSD solid state hard disc secure user data;
(2) use the SoC framework to encapsulate, integrated a large amount of IP, each module that hangs on the bus as shown in Figure 1 all adopts IP, design difficulty ground, and can reduce peripheral chip effectively, reduce the embedded system cost;
(3) can use single interface protocol realization data to transmit fast, reduce system complexity, improve system reliability;
(4) SSD is because its storage medium is Nandflash.So it has just had similar advantage to NandFlash: light, storage density is big, low in energy consumption, antidetonation and temperature adaptation wide ranges.
Claims (6)
1. SSD control chip, comprise SSD standard interface, USB interface and Flash memory controller, it is characterized in that the bus arbiter that described SSD standard interface, USB interface and Flash memory controller are hung on a bus and pass through to be disposed is obtained occupying of bus, communicate to connect being used to; Simultaneously, dispose the SM1 encryption and decryption module that is hung on described bus, with when using encryption and decryption functions, the equipment that arbitration is used to communicate to connect connects via this SM1 encryption and decryption module.
2. SSD control chip according to claim 1 is characterized in that, described SM1 encryption and decryption module and USB interface are equipped with the DMA of composition data link nodes.
3. SSD control chip according to claim 1 and 2 is characterized in that described USB interface is furnished with registers group, is used to dispose USB interface to determine whether to use SM1 encryption and decryption module.
4. SSD control chip according to claim 1 and 2 is characterized in that, described USB interface is the USB3.0 interface, and adds that by the USB3.0 Physical layer USB3.0 device controller constitutes.
5. SSD control chip according to claim 1 is characterized in that described bus is an internal bus, and the equipment on this bus of hanging over adopts the IP module and by overall package.
6. SSD control chip according to claim 1 is characterized in that this control chip is embedded with the risc processor that is connected in described bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320026322 CN203102265U (en) | 2013-01-18 | 2013-01-18 | Solid state disk (SSD) control chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320026322 CN203102265U (en) | 2013-01-18 | 2013-01-18 | Solid state disk (SSD) control chip |
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| Publication Number | Publication Date |
|---|---|
| CN203102265U true CN203102265U (en) | 2013-07-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201320026322 Expired - Fee Related CN203102265U (en) | 2013-01-18 | 2013-01-18 | Solid state disk (SSD) control chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9575669B2 (en) | 2014-12-09 | 2017-02-21 | Western Digital Technologies, Inc. | Programmable solid state drive controller and method for scheduling commands utilizing a data structure |
| CN109947694A (en) * | 2019-04-04 | 2019-06-28 | 上海威固信息技术股份有限公司 | A kind of Reconfigurable Computation storage fusion flash memory control system |
-
2013
- 2013-01-18 CN CN 201320026322 patent/CN203102265U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9575669B2 (en) | 2014-12-09 | 2017-02-21 | Western Digital Technologies, Inc. | Programmable solid state drive controller and method for scheduling commands utilizing a data structure |
| CN109947694A (en) * | 2019-04-04 | 2019-06-28 | 上海威固信息技术股份有限公司 | A kind of Reconfigurable Computation storage fusion flash memory control system |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130731 Termination date: 20160118 |
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| EXPY | Termination of patent right or utility model |