CN112540951A

CN112540951A - Special main control chip suitable for electric power system control protection device

Info

Publication number: CN112540951A
Application number: CN202011383035.XA
Authority: CN
Inventors: 李鹏; 习伟; 李肖博; 姚浩; 于杨; 蔡田田; 陈军健
Original assignee: Southern Power Grid Digital Grid Research Institute Co Ltd
Current assignee: Southern Power Grid Digital Grid Research Institute Co Ltd
Priority date: 2020-12-01
Filing date: 2020-12-01
Publication date: 2021-03-23

Abstract

The application provides a special main control chip suitable for a control protection device of a power system, which comprises a power special subsystem, a multi-core service main system, a safety subsystem and a storage module; the special subsystem of electric power, multicore business main system, safety subsystem pass through system bus communication, and a plurality of function processing integration sets up on the chip, have simplified the hardware architecture of chip, have avoided the unstable problem of multichip hardware structure connection, have improved the reliability and the stability of relay protection system, carry out the communication interaction between each inside subsystem of realization chip through system bus, further improve the wholeness ability of chip.

Description

Special main control chip suitable for electric power system control protection device

Technical Field

The application relates to the technical field of electricity, in particular to a special main control chip suitable for a power system control protection device.

Background

Each element of the power system needs to be provided with a relay protection device, and when a specified area in the power system breaks down, the relay protection device can cut off fault equipment in a very short time, so that the normal operation of the rest parts is guaranteed, and the large-area power failure accident is avoided. With the increasingly mature digitalization technology, the chip is popularized and applied in the relay protection field of the power system, and the intelligence and intellectualization of the relay protection are promoted.

In the prior art, functional nodes for relay protection are generally distributed in different chips, data exchange between the chips is performed through a communication bus, and the interaction efficiency is low due to more data exchange links.

Disclosure of Invention

Therefore, it is necessary to provide a dedicated main control chip suitable for a power system control protection device to solve the technical problem of low data interaction efficiency of a relay protection system in the prior art.

A dedicated master control chip adapted for use in a power system control protection device, comprising: the system comprises a power special subsystem, a multi-core service main system, a safety subsystem and a storage module; the electric power special subsystem, the multi-core service main system and the safety subsystem are communicated through a system bus;

the power-dedicated subsystem comprises a power algorithm-dedicated module and a power-dedicated DSP instruction set; the power algorithm special module is used for acquiring service data through a peripheral interface of the system bus, processing the service data and sending the service data to the multi-core service main system; the power-dedicated DSP instruction set is used for connecting the multi-core service main system to perform data transmission;

the multi-core service main system is used for receiving the processed service data sent by the power algorithm special module and generating a corresponding control instruction after processing; invoking an instruction from the power specific DSP instruction set;

the safety subsystem is used for carrying out safety service operation on the data of the multi-core service main system according to the request of the multi-core service main system;

and the storage module is used for receiving and storing the data of the chip so as to access the power special subsystem, the multi-core service main system and the safety subsystem.

In one embodiment, the multi-core service host system includes: a functional core and a trusted core;

the functional core comprises a power consumption management unit and at least one processor core;

the trusted core comprises a plurality of hardware functional modules and a plurality of bus interfaces; the hardware functional module at least comprises a hardware floating point unit and a DSP accelerating unit; the plurality of bus interfaces support at least a system bus, an instruction bus, and a data bus configuration.

In one embodiment, the multi-core service host system further includes: a high-speed bus peripheral interface and a low-speed bus peripheral interface.

In one embodiment, the high-level extensible interface is used for communication connection between the power algorithm special module and the multi-core business main system;

the high-level high-performance bus is used for connecting equipment of the high-speed bus peripheral interface with the high-level expandable interface;

the high-level peripheral bus is used for connecting the equipment of the low-speed bus peripheral interface with the high-level expandable interface.

In one embodiment, the storage module comprises at least one of a local Cache and an SRAM, a system SRAM, and a DRAM.

In one embodiment, the power algorithm-specific module and the power-specific DSP instruction set are respectively connected to the multi-core service main system through an interrupt signal; the power specific DSP instruction set is also used to transfer data from the SRAM of the power specific DSP instruction set to the system SRAM.

In one embodiment, the security subsystem comprises a security kernel and a cryptographic security module; the safety core adopts an 16/32-bit mixed coded RISC instruction set; the cryptographic algorithm security module is used for carrying out security service operation.

In one embodiment, the multi-core service main system communicates with the security subsystem through the Mailbox to transmit the control command.

In one embodiment, the security subsystem is further configured to transmit the data of the multi-core service main system after the security service operation is performed to the multi-core service main system through a high-speed bus peripheral interface.

The special main control chip suitable for the power system control protection device comprises a power special subsystem, a multi-core service main system, a safety subsystem and a storage module; the special subsystem of electric power, multicore business main system, safety subsystem pass through system bus communication, and a plurality of function processing integration sets up on the chip, have simplified the hardware architecture of chip, have avoided the unstable problem of multichip hardware structure connection, have improved the reliability and the stability of relay protection system, carry out the communication interaction between each inside subsystem of realization chip through system bus, further improve the wholeness ability of chip.

Drawings

FIG. 1 is a block diagram of a dedicated main control chip suitable for use in a power system control protection device in one embodiment;

fig. 2 is a diagram of a multi-core service main system structure of a multi-core SoC chip in one embodiment;

FIG. 3 is a diagram of a power-specific subsystem architecture of a multi-core SoC chip in one embodiment;

FIG. 4 is a diagram of a security subsystem architecture of a multi-core SoC chip in one embodiment;

FIG. 5 is a diagram of a system bus structure of a multi-core SoC chip in one embodiment;

FIG. 6 is a schematic diagram illustrating interaction between a multi-core service host system and a power-dedicated subsystem, according to an embodiment;

FIG. 7 is a schematic diagram illustrating interaction between a multi-core service host system and a security subsystem, according to an embodiment;

fig. 8 is a structural diagram of a dedicated main control chip suitable for controlling the protection device in the power system in another embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The application provides a special main control chip suitable for electric power system control protection device can be an SoC chip integrated with a plurality of IP cores. Among them, SoC (System on Chip), also called System on Chip, means that it is a product, an integrated circuit with a special purpose, which contains the complete System and has the whole content of embedded software. An IP core (Intellectual Property) may be a pre-designed and verified reusable integrated circuit module.

In one embodiment, as shown in fig. 1, there is provided a dedicated master control chip adapted for controlling a protection device in an electric power system, the chip comprising: the system comprises a power special subsystem, a multi-core service main system, a safety subsystem and a storage module; the electric power special subsystem, the multi-core service main system and the safety subsystem are communicated through a system bus. Wherein:

a power-specific subsystem that may include a power algorithm-specific module and a power-specific DSP instruction set; the special module for the power algorithm can be used for acquiring service data through a peripheral interface of a system bus, processing the service data and sending the service data to the multi-core service main system, and can realize hardware acceleration of preposed data processing, network communication and data management algorithms by using an ASIC (application specific integrated circuit) logic circuit; the DSP instruction set special for electric power can be used for connecting the multi-core service main system to carry out data transmission and carrying out instruction customization aiming at an electric parameter calculation algorithm. The power-specific subsystem may provide efficient data parallel processing and high-performance data computation functions. The DSP can adopt a Harvard structure with separated programs and data, is provided with a special hardware multiplier, widely adopts pipeline operation, provides special DSP instructions, and can be used for quickly realizing various digital signal processing algorithms. An ASIC, i.e., an application specific integrated circuit, may be an integrated circuit designed and manufactured to meet the needs of a particular user and a particular electronic system.

The multi-core business main system can be used for receiving the processed business data sent by the power algorithm special module and generating a corresponding control instruction after processing; and calling the instruction from the power-dedicated DSP instruction set, which may include a plurality of processing cores, such as a functional core, a trusted core, and the like, to meet the requirements of protection service functions such as real-time control, management communication, and the like.

The safety subsystem can be used for carrying out safety service operation on data of the multi-core service main system according to the request of the multi-core service main system; the security subsystem can be embedded with a national secret algorithm security module, integrates a memory protection unit and a security protection component, provides security service operations such as data encryption and decryption, identity authentication and the like based on the anti-attack national secret algorithm hardware logic, and realizes functions such as information source encryption, channel encryption, chip security starting and the like according to the requirements of multiple application scenes.

The storage module may be configured to receive and store data of the chip to be accessed by the power-dedicated subsystem, the multi-core service main system, and the security subsystem, and may include a security core. The memory module may include a multi-level memory system, such as local Cache, SRAM, and system SRAM, and may also include an associated multi-channel off-chip memory DRAM. Among them, the SRAM (Static Random-Access Memory) is one of Random Access memories, and the SRAM can store data stored therein without a refresh circuit. DRAM (Dynamic Random Access Memory) is refreshed and charged once every certain period of time, otherwise, internal data will disappear. The local Cache may be a local Cache.

Above-mentioned special main control chip suitable for power system control protection device sets up a plurality of function processing integration on the chip, has simplified the hardware architecture of chip, has avoided the unstable problem of multichip hardware structural connection, has improved relay protection system's reliability and stability, realizes the communication interaction between each inside subsystem of chip through the system bus, further improves the wholeness ability of chip.

In one embodiment, the multi-core service host system may include a functional core and a trusted core. The functional core may include a power management unit and at least one processor core.

The functional core can be a 32-bit ultra-high performance embedded multi-core processor facing the SoC application field, and has excellent power consumption and performance. The RISC Instruction Set (Reduced Instruction Set computer) adopting 16/32 bit hybrid coding is mainly oriented to high-end embedded applications with strict performance requirements, such as artificial intelligence, machine vision, video monitoring, automatic driving, mobile intelligent terminals, high-performance communication, information security, and the like. The functional cores can adopt a homogeneous multi-core architecture and support 1-4 processor core configurations. Each core adopts an independently designed architecture and a micro-architecture, and optimizes the performance by aiming at the characteristics, and introduces a 3-emission 5-execution superscalar architecture, a strong vector operation acceleration engine, a multi-channel data pre-fetching and other high-performance technologies. In the aspect of system management, the functional core can integrate an on-chip power consumption management unit and support low-power consumption technology of multi-voltage and multi-clock management. The functional core can support real-time monitoring and turn off the internal idle functional module, and further reduces the dynamic power consumption of the processor.

A trusted core that may include a plurality of hardware functional modules and a plurality of bus interfaces; the hardware functional module at least comprises a hardware floating point unit and a DSP accelerating unit, and can also realize functions of on-chip cache, the DSP accelerating unit, a trusted protection technology, on-chip tightly-coupled IP and the like; the plurality of bus interfaces may support flexible configuration of at least a system bus, an instruction bus, and a data bus.

In one embodiment, the bus interface of the multi-core service main system may include a high-speed bus peripheral interface and a low-speed bus peripheral interface, where the high-speed bus peripheral interface mainly includes a high-speed ethernet controller GMAC network interface module, a DMAC module for carrying bulk data, a USB controller SDIO module, and a Mailbox module for inter-core communication transmission interruption and data; the low-speed peripheral interface mainly includes an SPI bus (high-speed synchronous serial port), an I2C bus, a UART bus (universal asynchronous serial port), and a GPIO interface (General-purpose input/output).

In one embodiment, the multi-core service host system may further include assorted hardware peripherals such as a timer, a watchdog, an interrupt controller, and a one-time programmable non-volatile memory.

In one embodiment, as shown in fig. 2, a block diagram of a multi-core service main system is provided, which may include a functional core, a trusted core, a cache and an on-chip SRAM, as well as a high-speed bus peripheral interface and a low-speed bus peripheral interface, and may further include a timer, a watchdog, an interrupt controller and a one-time programmable nonvolatile memory. The multi-core service main system has the characteristics of high expansibility and high power consumption efficiency, and the overall performance and the power consumption efficiency of the chip are improved by performing resource configuration on the functional core and the trusted core.

In one embodiment, as shown in fig. 3, the power-specific subsystem may include a power algorithm-specific module and a power-specific DSP instruction set, and a static memory, wherein the power algorithm-specific module may include a customized DSP instruction set, and the power algorithm-specific module may include a plurality of algorithm-specific IP cores for processing advanced data processing class, network communication class, and data management class algorithm hardware acceleration, so as to implement data parallel processing and improve data computation efficiency.

In one embodiment, the security subsystem may include a security kernel and a cryptographic security module; the safety core can adopt 16/32 bit mixed coded RISC instruction set, through the designed instruction system and pipeline hardware structure, the running efficiency and performance of 32 bit embedded CPU can be obtained with the cost of 8 bit CPU, and the safety core has the advantages of extremely low cost, extremely low power consumption, high code density and the like, and the 16 bit instruction set has the advantages of low cost and high code density; the advantages of the 32-bit instruction set are wide immediate and relative jump offsets, many operands, and high performance. In practice, the custom compiler will selectively choose a mix of 16-bit and 32-bit instructions based on the actual requirements of the compilation optimization. When a user uses assembly, assembly instructions with uniform formats can be written according to requirements, an assembler can select 16-bit or 32-bit instructions according to actual conditions, and the instruction width is transparent to the user; the security module of the national cryptographic algorithm can be used for encrypting and decrypting data, and the security performance is improved.

In one embodiment, as shown in fig. 4, the security subsystem may include a secure core, a cryptographic security module, a secure communication module, a static memory, a true random number generator, and a memory management module. The functions of information source encryption, channel encryption, chip safe starting and the like are realized according to the application scene, and the overall safety performance of the SoC chip is improved.

In an embodiment, a system Bus may be an Interface for interconnecting subsystems in an SoC chip, and a system Bus on chip design is crucial to overall performance of the chip, and in this application, the SoC chip may employ an AXI (Advanced eXtensible Interface), an AHB (Advanced High performance Bus) and an APB (Advanced Peripheral Bus) Bus protocol under an AMBA (Advanced processor Bus architecture) Bus frame. In specific use, the AXI can completely separate read and write operations of the bus, each group of operations consists of address, data and control signals, and supports out-of-order execution; the AHB and APB read-write share one channel, and can only be executed in sequence, and the read-write performance of each bus is as follows: AXI > AHB > APB.

In an embodiment, as shown in fig. 5, for a system bus design diagram of an SoC chip, an advanced extensible interface of the system bus may be used for communication connection between a power algorithm dedicated module and a multi-core service main system, and the multi-core service main system may employ a high-performance dual-core CK860 processor and has an AXI bus interface. Each CPU core of the SoC chip, such as a functional core and a trusted core, may be directly connected to an IP core of a power-dedicated subsystem having a standard AXI interface, and a system SRAM storage unit. Because the high-performance AXI bus is adopted to connect the CPU core, the storage unit and the ASIC (application specific integrated circuit), the safety and the transmission rate of the system far exceed the transmission scheme on a non-SoC board, the data bandwidth can reach the level of 3-5 Gbits/sec, the data bandwidth is improved by one order of magnitude compared with a processor and FPGA architecture, and the information communication among the cores can be realized by combining an interrupt mechanism.

The high-level high-performance bus can be used for connecting equipment of a high-speed bus peripheral interface with the high-level expandable interface. The AHB interface design-based GMAC, DMAC, SDIO, Mailbox and other modules can adopt an X2H module (AXI-AHB module) to realize the connection of an AXI bus and an AHB bus, and then an IP core of an AHB port is integrated to the AHB bus to realize the interconnection of a CPU core and each functional module.

And the high-level peripheral bus can be used for connecting equipment of the low-speed bus peripheral interface with the high-level expandable interface. The peripheral units such as SPI, UART, etc. usually work in a lower frequency environment, can be interconnected based on an APB bus with lower performance requirements, and implement transfer of signals to an AXI bus by using standard APB and AXI bridge modules, and connect to each CPU core.

In one embodiment, the CPU core of the SoC chip may employ a CK802 processor, a built-in AHB bus interface, and an AHB bus to connect the CPU core, the memory unit, and the security subsystem. Because the safety subsystem does not communicate with the outside of the chip, the safety subsystem does not need to be integrated and used with a peripheral unit, and an APB bus can not be designed.

In one embodiment, the storage module may include at least one of a local Cache and an SRAM, a system SRAM and a DRAM, and may also include a multi-channel off-chip storage DRAM to implement data caching, calling and transmission, avoid that a chip adopts complete external storage data, and guarantees data correctness by means of a timing sequence of hardware itself, resulting in an error that cannot be identified, and improve reliability of the chip.

In one embodiment, as shown in fig. 6, the multi-core service main system and the power-dedicated subsystem may establish an efficient transmission mechanism for satisfying the fast transmission of a large amount of data and the fast response of the control signal between the main system and the power-dedicated subsystem. The special module for the power algorithm can be directly connected with a CK860 kernel of the multi-core service main system through an interrupt signal, data are transmitted through a special AXI bus, the CK860 kernel of the multi-core service main system can also directly operate a special DSP instruction set for power through the AXI bus, the special DSP instruction set for power can be directly connected with the CK860 kernel of the multi-core service main system through the interrupt signal, and the data are transmitted to a system SRAM or an off-chip DRAMS from a local SRAM. The power patent subsystem can realize high-performance data calculation and interactive transmission in a chip.

In an embodiment, as shown in fig. 7, a secure transmission mechanism may be established between the multi-core service main system and the security subsystem, the security subsystem may be a data transmission initiator, the secure transmission mechanism is established between the multi-core service main system and the security subsystem, and the secure interaction between the multi-core service main system and the security subsystem is implemented through a one-way operation permission mechanism. The multi-core service main system and the safety subsystem can receive the interrupt signal through Mailbox communication to realize control command transmission. The security subsystem can encrypt, decrypt or verify the processed data by interrupting the core of the direct connection multi-core service main system CK860, and can transmit the data to the multi-core service main system through the security SRAM → AXI high-speed bus → system SRAM of the security subsystem. The safety of data processing is improved by establishing a safety transmission mechanism.

In one embodiment, as shown in fig. 8, there is provided a dedicated master control chip adapted for controlling a protection device in an electric power system, including: the system comprises a multi-core service main system, a power special subsystem, a safety subsystem and a storage module, and is used for communication of the power special subsystem, the multi-core service main system and the safety subsystem. The multi-core service main system can comprise at least one functional core, at least one credible core, a cache module, an on-chip SRAM module, a peripheral interface and other matched equipment; the power-specific subsystem may include a power algorithm-specific module, which may include at least one algorithm IP core for processing corresponding data, and a power-specific DSP instruction set, which may include a custom DSP instruction set, for transferring data from the local SRAM to the system SRAM, and a static memory; the security subsystem may include a security kernel, a cryptographic security module, and a static memory module. The system bus may include AXI, AHB, APB interfaces for connecting different subsystems for communication according to read-write performance requirements. The multi-core service main system is communicated with the special power subsystem and the safety subsystem through a system bus, and high-performance data processing and communication safety are achieved respectively.

The special main control chip suitable for the power system control protection device in the above embodiment may adopt a multi-core heterogeneous chip architecture of CPU + DSP + ASIC, integrate a plurality of functional processes on the chip, combine the advantages of various computing unit control, computation, and parallel processing, achieve optimal overall performance and power consumption, and be applicable to power multi-scenario application, and improve the overall performance of the chip through system bus design; by establishing an efficient transmission mechanism between the multi-core service main system and the special electric power subsystem and establishing a safe transmission mechanism between the multi-core service main system and the safe subsystem, the high efficiency, stability and robustness of multi-core cooperative work are ensured, and the operation stability and reliability of the relay protection system are further improved.

In order to more clearly illustrate the solutions provided by the present application, the application parameters of the dedicated main control chip adapted to the power system control protection device according to the above embodiments of the present application are described below, and it should be understood that this parameter information is only an example of the parameters of the SoC chip and should not be considered as a limitation to the above embodiments.

The SoC chip has the main functions of protection, measurement and control and communication. To meet these requirements, the chip is required to be capable of flexibly setting parameters, real-time system, fast response, integrating mature application layer control strategies, possessing strong communication management capability, supporting flexible software upgrading modes, and the like. Therefore, a plurality of IP function modules are required, and the following are IP function descriptions and main technical indexes in the SoC chip.

And the Timer realizes the function of the Timer. The technical indexes are as follows: the Timer comprises 2 32-bit advanced function timers (contained in a power special IP), 2 64-bit basic function timers, 6 x2 32-bit basic level function timers (supporting an external clock source, interrupting the CPU, simultaneously connecting the CPU to a PAD as an output, and supporting each counter to independently interrupt), and the timing length of the Timer is 20 seconds at most.

CAN belongs to bus type serial communication network, adopts a plurality of new technologies and unique design ideas, and compared with similar products, the CAN bus has the advantages of reliability, real time and flexibility in data communication. The technical indexes are as follows: 2, the baud rate is more than or equal to 1Mbps, and each CAN interface independently comprises more than or equal to 14 filters.

SPI, a high-speed, full-duplex, synchronous communication bus, supports full-duplex communication, is simple to communicate, and has a data transmission rate block. The technical indexes are as follows: 6, single data lines, 6 master ends, transmission speed more than or equal to 25Mbps, DMA is supported, FIFO depth is 64 bytes, and at least 2 bytes reach 100 bytes.

Compared with the SPI, the QSPI has the biggest structural characteristic that 80 bytes of RAM replaces a data transmitting register and a data receiving register of the SPI. Using this interface, a user can transmit a transmission queue containing up to 16 8-bit or 16-bit data at a time. The technical indexes are as follows: 3, the maximum interface clock IS 50MHz, and the interface IS compatible with various models such as 16M ISSI IS25LP128-JBLE, 32M ISSI IS25LP256D-JMLE, 64M magnesium light MT25QL512ABB and the like.

The special IP core for the power grid is added with an SV/GOOSE message processing function on the basis of a general Ethernet MAC, can be digitally sampled and delayed for measurement, and provides an original message after storm suppression, a B code, time synchronization, a complete RTC, a timing bus and frequency tracking. The technical indexes are as follows: power specific MACs, i.e., 8 hundred megabytes of network ports, 8 independent power specific MACs.

PWM is a very effective technique for controlling analog circuits using the digital output of a microprocessor. The technical indexes are as follows: 12 paths, the frequency is 1 Hz-50 KHz, and the duty ratio requires 1000 times of the maximum frequency (the pulse precision is 50 MHz).

GMAC, which belongs to the data link layer in the seven-layer ISO standard, controls and coordinates the channel between the logical link and the physical link, and can connect various different physical media, wherein the different physical media have different GMAC standards. GMAC is one of the conditions necessary to make a gigabit network. The technical indexes are as follows: 3, commercial standard gigabit MAC, GMAC standard bandwidth.

An SD (eMMC) controller for managing the SD card. The technical indexes are as follows: 2, rate 50MHz, compatible eMMC.

The USB controller is used for realizing operation interfaces such as chip reading and writing, and interface chip firmware is various bottom layer function functions of the USB controller. The technical indexes are as follows: 2 USB2.0, the rate is USB standard rate, the data bandwidth reaches 15MB/s, and host mode is supported.

And the LCD controller is mainly used for controlling the display of the liquid crystal display. The technical indexes are as follows: 1, the maximum frequency is 75MHz, the data bandwidth is 1.2Gbps, and the refresh rate reaches 50Hz when the 1280 × 800 resolution LCD screen is controlled.

The DSP adopts a Harvard structure with separated programs and data inside, is provided with a special hardware multiplier, widely adopts pipeline operation, provides special DSP instructions and can be used for quickly realizing various digital signal processing algorithms. The technical indexes are as follows: 2, the rate reaches 200 MHz.

ADCs, i.e., analog-to-digital converters, are a class of devices used to convert continuous signals in analog form to discrete signals in digital form. An analog to digital converter may provide the signal for measurement. The technical indexes are as follows: 1, 12bit, 10 channel, rate up to 1 MSPS.

ADCC for controlling the ADC module. The technical indexes are as follows: the device is integrated in the power special IP, is compatible with AD with the same control time sequence of AD7606 and AD7616, supports 2 paths of SPI and has 3 chip selections in each path.

General purpose I/O. The technical indexes are as follows: more than or equal to 96.

Technical indexes of other modules are as follows: HDLC two-way, Xtimer, Xcap, etc.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A special main control chip suitable for a power system control protection device is characterized by comprising: the system comprises a power special subsystem, a multi-core service main system, a safety subsystem and a storage module; the electric power special subsystem, the multi-core service main system and the safety subsystem are communicated through a system bus;

2. The chip according to claim 1, wherein the multi-core service host system includes: a functional core and a trusted core;

3. The chip according to claim 2, wherein the multi-core service host system further comprises: a high-speed bus peripheral interface and a low-speed bus peripheral interface.

4. The chip of claim 3, wherein the system bus comprises at least one of an advanced extensible interface, an advanced high performance bus, and an advanced peripheral bus.

5. The chip of claim 4,

the high-level expandable interface is used for communication connection between the power algorithm special module and the multi-core business main system;

6. The chip of claim 1, wherein the storage module comprises at least one of a local Cache and an SRAM, a system SRAM, and a DRAM.

7. The chip of claim 6, wherein the power algorithm specific module and the power specific DSP instruction set are respectively connected to the multi-core service host system via an interrupt signal; the power specific DSP instruction set is also used to transfer data from the SRAM of the power specific DSP instruction set to the system SRAM.

8. The chip of claim 1, wherein the secure subsystem comprises a secure kernel and a cryptographic security module; the safety core adopts an 16/32-bit mixed coded RISC instruction set; the cryptographic algorithm security module is used for carrying out security service operation.

9. The chip of claim 8, wherein the multi-core service main system communicates with the security subsystem through a Mailbox to transmit a control command.

10. The chip according to claim 8, wherein the security subsystem is further configured to transmit data of the multi-core service main system after performing the security service operation to the multi-core service main system through a high-speed bus peripheral interface.