WO2022252718A1

WO2022252718A1 - Power-chip-specific subsystem

Info

Publication number: WO2022252718A1
Application number: PCT/CN2022/078179
Authority: WO
Inventors: 李鹏; 习伟; 黄凯; 姚浩; 陈军健; 陶伟; 邓清唐; 李昱霆
Original assignee: 南方电网数字电网研究院有限公司
Priority date: 2021-06-02
Filing date: 2022-02-28
Publication date: 2022-12-08
Also published as: CN113067905B; JP2024513646A; CN113067905A

Abstract

The present application relates to a power-chip-specific subsystem and a power-system-specific chip. In the subsystem, a power-specific MAC module is used for processing a subscribed Ethernet data packet according to a first time stamp, which is provided by a time stamp management module, so as to obtain power service data; a signal conversion subsystem is used for performing sampling, transportation and storage processing on the power service data in the power-specific MAC module according to a second time stamp, which is provided by the time stamp management module; a data processing module comprises a power-specific digital signal processing array and a first memory, which is coupled to the power-specific digital signal processing array; and the power-specific digital signal processing array is used for performing data processing on the power service data in the signal conversion subsystem according to a specified algorithm, so as to obtain processed data that conforms to a preset format. By using the present system, on the basis of meeting a power data processing requirement, the system costs and power consumption can be reduced, and the system stability can be improved.

Description

Power Chip Dedicated Subsystem

technical field

The present application relates to the field of electrical technology, in particular to a power system dedicated chip and a power chip dedicated subsystem.

Background technique

At present, the smart grid realizes the rapid transmission of information within the system and between systems, as well as various more advanced applications, through the informatization of the power grid. Grid informatization integrates Ethernet technology into the grid to improve the real-time performance and reliability of grid communication. In the computer open system interconnection communication reference model, the control of the MAC layer is the guarantee of reliable and efficient communication of each device in the Ethernet.

At present, most power grid chips implement a single MAC function through a general-purpose MAC module. At the same time, multi-core heterogeneous technology has been widely used in fields such as ultra-large-scale computers. Customization requirements for consumption.

Contents of the invention

Based on this, it is necessary to address the above technical problems and provide a power chip dedicated subsystem and a power system dedicated chip that can reduce system cost, power consumption, and improve system stability on the basis of meeting power data processing requirements.

A dedicated subsystem for power chips, comprising: a real-time processing module, a data processing module, a signal conversion subsystem, a time-scale management module, and a power-specific MAC module; a real-time processing module, a data processing module, a signal conversion subsystem, and a time-scale management module It is interconnected with the power-specific MAC module through the system bus;

The real-time processing module is used to schedule the data processing module, signal conversion subsystem, time scale management module and power-specific MAC module;

The power dedicated MAC module is used to process the subscribed Ethernet data packets according to the first time stamp provided by the time stamp management module to obtain power service data;

The signal conversion subsystem is used to sample, transport and store the power service data in the power-specific MAC module according to the second time scale provided by the time scale management module;

The data processing module includes a power-specific digital signal processing array and a first memory coupled with the power-specific digital signal processing array; the power-specific digital signal processing array is used to process the power business data in the signal conversion subsystem according to a specified algorithm, and obtain Processing data conforming to a preset format; the first memory is used to store the processing data.

In one of the embodiments, the signal conversion subsystem includes: an embedded processor, a second memory and a serial peripheral interface module;

The embedded processor executes a specific embedded program according to the second time scale, controls the external signal conversion chip, and realizes sampling, handling and storage of the power business data in the power-specific MAC module; the signal conversion subsystem and signal The conversion chip communicates through the serial peripheral interface protocol provided by the serial peripheral interface module;

The second memory is used to store the embedded program and the power service data processed by the embedded processor.

In one of the embodiments, the signal conversion subsystem further includes a memory access module;

When it is detected that the data volume of the power service data in the power-specific MAC module is greater than the data volume threshold, the embedded processor executes a specific embedded program according to the second time scale, and controls the external signal conversion chip to realize power-specific The power service data in the MAC module is sampled and stored; the memory access module is used to carry and process the power service data in the power-specific MAC module.

In one embodiment, the protocol mode of the serial peripheral interface module includes at least one of a single-wire mode, a two-wire mode and a four-wire mode.

In one of the embodiments, the signal conversion subsystem is configured as an 8-way interface.

In one of the embodiments, the power-specific MAC module is equipped with a programmable message-specific processor implemented with a dedicated instruction set; the message-specific processor is used to pair the subscribed Ethernet Network data packets are filtered and storm suppression processed to obtain power business data.

In one embodiment, the system includes a slave interface and a host interface; the slave interface and the host interface are used to integrate the system into a power system dedicated chip.

In one of the embodiments, the real-time processing module includes a first real-time processor and a second real-time processor, the first real-time processor is used to schedule the signal conversion subsystem; the second real-time processor is used to schedule the power-specific MAC module .

In one of the embodiments, the first time scale includes time stamp information of Ethernet data packet processing; the second time scale includes sampling time interval information of power service data.

A special chip for a power system, on which the above-mentioned system is integrated.

The above-mentioned power chip dedicated subsystem and power system dedicated chip schedule the data processing module, signal conversion subsystem, time stamp management module and power dedicated MAC module through the real-time processing module in the power chip dedicated subsystem; the power dedicated MAC module manages The first time stamp provided by the module processes the subscribed Ethernet data packets to obtain power service data; the signal conversion subsystem is used to process the power service data in the power dedicated MAC module according to the second time stamp provided by the time stamp management module Sampling, handling and storage processing; the data processing module performs data processing on the power business data according to the specified algorithm, reduces the load of the real-time processor or the application processor in the power system dedicated chip, and improves the data processing efficiency and system performance at the same time. The cost is reduced and the stability of the system is improved.

Description of drawings

Fig. 1 is a structural block diagram of a power chip dedicated subsystem in an embodiment;

Fig. 2 is a structural block diagram schematic diagram of a power chip dedicated subsystem in an embodiment;

Fig. 3 is a structural block diagram of the signal conversion subsystem in an embodiment;

Fig. 4 is a structural block diagram of a power system dedicated chip in an embodiment;

Fig. 5 is an internal structure diagram of the electric device in one embodiment.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

The power chip dedicated subsystem provided by this application is suitable for power business data processing. The power chip dedicated subsystem is based on a multi-core heterogeneous architecture. The system is applied to the terminal for illustration. It can be understood that the power chip dedicated subsystem can also be It is applied to an application environment including a terminal and a server, and is implemented through interaction between the terminal and the server, and can also be applied to the server.

In one embodiment, as shown in Figure 1, a kind of power chip dedicated subsystem is provided, real-time processing module, data processing module, signal conversion subsystem, time scale management module and power special-purpose MAC module; Real-time processing module, data The processing module, signal conversion subsystem, time scale management module and power-specific MAC module are interconnected through the system bus. in:

The real-time processing module is used to schedule the data processing module, signal conversion subsystem, time scale management module and power-specific MAC module; that is, the real-time processing module is used to execute the application drivers of each module; the real-time processing module includes at least two Each real-time processor is driven by parallel execution applications. The real-time processor completes the resource scheduling, program scheduling and data flow control of the entire subsystem. Resource scheduling refers to transferring power business data from the power chip dedicated subsystem through the bus Interconnection, transportation to SRAM/DDR and other storage, or use by the processor itself. When the real-time processing module includes a first real-time processor and a second real-time processor, the first real-time processor is used to schedule the signal conversion subsystem; the second real-time processor is used to schedule the power-specific MAC module.

The power-specific MAC module is equipped with a message-specific processor implemented with a dedicated instruction set on the general-purpose MAC module, which can efficiently implement the function of subscribing to specific Ethernet messages through customized instructions; it is used to provide Process the subscribed Ethernet data packets at the first time scale to obtain power service data. The power service data includes analog quantities such as current and voltage in the power system.

The first time stamp includes the timestamp information of Ethernet packet processing, "first" and "second" are used to distinguish different time stamps, that is, the first time stamp can be the second time stamp, and the second time stamp can also be It is the first time scale. The time scale management module is used to provide the time scale for the signal conversion subsystem and the power dedicated MAC module in the power chip dedicated subsystem. The time scale is provided by the IRIG-B (InterRange Instrumentation Group-B, Class B serial clock code) and PPS (Precision Positioning System, Precision Positioning Service) format time scale is determined by any method.

Optionally, the power-specific MAC module is equipped with a programmable message-specific processor implemented with a dedicated instruction set; the message-specific processor is used to pair subscribed Ethernet data packets according to the first time stamp provided by the time stamp management module Perform filtering and storm suppression processing to obtain power service data and avoid data loss.

The signal conversion subsystem can be an ADC subsystem, which is used to sample, transport and store the power business data in the power dedicated MAC module according to the second time scale provided by the time scale management module; the signal conversion subsystem, namely the ADC subsystem The system, which is the control module of the ADC chip, communicates through the SPI (Serial Peripheral Interface, Serial Peripheral Interface) protocol.

The second time scale includes the sampling time interval information of the power business data, and the second time scale is used to trigger the signal conversion subsystem to collect the required power business data, and convert the collected power business data into data in a preset format; for example, according to The Ethernet message subscribed by the power dedicated MAC module obtains the power service data as an analog signal; according to the second time scale control signal conversion subsystem, the external ADC sampling chip samples the power service data to obtain the sampled power service data; The power service data is converted into digital signals to obtain power service data in the form of digital signals; the power service data in the form of digital signals is sent to the memory coupled with the signal conversion subsystem for storage, and the DMA module (Direct Memory Access) coupled with the signal conversion subsystem , direct memory access) for data transfer; when the ADC subsystem completes the task, it sends an interrupt signal to the real-time processor to complete the data sampling, transfer and storage.

The data processing module includes a power-specific digital signal processing array and a first memory coupled with the power-specific digital signal processing array; the power-specific digital signal processing array is used for the power business data in the signal conversion subsystem according to a specified algorithm (specified algorithm, That is, the digital signal processing algorithm applied in the power system; for example, discrete Fourier transform (DiscreteFourier Transform, DFT), fast Fourier transform (fast Fourier transform, FFT, etc.) The processed data (for example, use DFT to perform convolution operation on the obtained current or voltage to obtain the corresponding vector); the memory is used to store the processed data.

Among them, the power-specific digital signal processing array is a DSP array (Digital Signal Processing, digital signal processing chip), and the DSP array can execute various digital signal processing algorithms applied in the power system, relieve the data processing pressure of the application processor, and improve The data processing performance of the application processor; the first memory coupled to it is SRAM (Static Random-Access Memory, static random access memory), and the SRAM is used to store calculation data.

Optionally, the SRAM can be used to store intermediate data generated by other modules in the dedicated subsystem of the power chip, including data generated by DSP calculations, sampling data of the ADC subsystem, and the like.

Optionally, in one embodiment, the system includes a slave interface and a host interface; the slave interface and the host interface are used to integrate the system into a power system dedicated chip, which facilitates the integration of power chip dedicated subsystems into different types , function of the power system dedicated chip, reducing costs.

The processor starts ADC sampling through the configuration register. After the sampling is completed, the processor will receive an interrupt and start to receive data through the ADC chip interface. After the initial processing of the data, the data will be transferred to SRAM/DDR and other storage, and handed over to the real-time processor for processing. Subsequent data processing and calculations. In one embodiment, as shown in FIG. 2 , it is a schematic structural block diagram of a power chip dedicated subsystem, including a real-time processing module, a data processing module, a signal conversion subsystem, a time scale management module and a power-specific MAC module, wherein the real-time The processing module includes two real-time processors, one of which is used to schedule the ADC subsystem; the other real-time processor is used to schedule the power-specific MAC module, and the data processing module includes DSP and power-specific digital signal processing The array-coupled first memory SRAM, the ADC subsystem is configured as an 8-way interface, and the power-specific MAC is configured as an 8-way interface; through the slave machine interface, the slave machine interface and the host interface are used to integrate the system into a power system dedicated chip.

The power chip dedicated subsystem mentioned above schedules the data processing module, signal conversion subsystem, time scale management module and power-specific MAC module through the real-time processing module. The functions of each module are independent of each other and can be independently and flexibly configured; The first time stamp provided by the time stamp management module processes the subscribed Ethernet data packets to obtain power service data; the signal conversion subsystem is used to convert the power in the power-specific MAC module according to the second time stamp provided by the time stamp management module. Sampling, handling and storage of business data; configuring the time stamp management module through the real-time processor can provide time stamps for the ADC subsystem and the power-specific MAC module at the same time to support the timing of ADC sampling and the analysis of Ethernet packets at regular intervals, etc. Function; the data processing module performs data processing on the power business data according to the specified algorithm, reduces the load of the real-time processor or the application processor in the power system dedicated chip, and reduces the cost and improves the efficiency of the data processing and the high performance of the system. system stability.

In one embodiment, as shown in Figure 3, a signal conversion subsystem is provided, including: an embedded processor, a second memory, a serial peripheral interface module, and a memory access module; wherein:

The embedded processor executes a specific embedded program according to the second time scale, controls the external signal conversion chip, and realizes sampling, handling and storage of the power business data in the power-specific MAC module; the signal conversion subsystem and signal The conversion chip communicates through the serial peripheral interface protocol provided by the serial peripheral interface (SPI) module, that is to say, the SPI interface can allow the signal conversion subsystem to communicate with the ADC sampling chip through the SPI protocol, and the mode of the SPI protocol Configured as single-wire, double-wire, four-wire and other modes, it can be adapted to different types of ADC sampling chips and improve the versatility of the signal conversion subsystem.

The second memory is used to store the embedded program and the power service data processed by the embedded processor. The second memory can be SRAM, that is, the SRAM can be used as the program storage and data storage of the embedded processor at the same time. The size can be flexibly configured, and the size of the configuration can be determined according to different programs and data requirements.

The memory access module (i.e. DMA module), when detecting that the data volume of the power service data in the power-specific MAC module is greater than the data volume threshold, the embedded processor executes a specific embedded program according to the second time scale, and the external signal The conversion chip is controlled to realize the sampling and storage processing of the power business data in the power-specific MAC module; the memory access module is used to carry and process the power business data in the power-specific MAC module. That is, the DMA module is used for flexible data transfer, which can not occupy the embedded processor, but allows the embedded processor to handle other tasks, such as data processing of ADC sampling, etc., to improve the performance of the embedded processor. In the above signal conversion subsystem, the ADC subsystem first configures the embedded program into the SRAM through the external host, then starts the embedded processor, controls the external ADC sampling chip according to the obtained second time scale, starts sampling, and passes SPI Protocol to communicate, send or receive power business data; that is, the embedded processor can configure the DMA module before the sampling starts, after the sampling starts, the DMA can carry the SPI-compatible power business data by itself, and optionally move it to different In storage (for example, SRAM of DSP, SRAM of embedded processor, etc.); DMA and SPI module handshake through hardware handshake, and then carry out data transfer through bus interconnection. The embedded processor can perform some processing on the returned data first, and then send the data to other modules of the subsystem; that is, through flexible configuration, when processing power business data, it can reduce costs by configuring special function requirements.

In one embodiment, as shown in FIG. 4 , a power system dedicated chip (power SoC chip) is provided, on which a power chip dedicated subsystem, an application processor, other modules and a DDR controller are integrated. (Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory), power chip dedicated subsystems, application processors, other modules and DDR controllers are interconnected through communication buses. The DDR controller can access DDR storage, and for the storage of large amounts of data, it can be flexibly solved through DDR access.

Power chip dedicated subsystem, including: real-time processing module, data processing module, signal conversion subsystem, time-scale management module and power-specific MAC module; real-time processing module, data processing module, signal conversion subsystem, time-scale management module and power The dedicated MAC blocks are interconnected via the system bus.

The real-time processing module is used to schedule the data processing module, signal conversion subsystem, time scale management module and power-specific MAC module. The real-time processing module includes a first real-time processor and a second real-time processor. The first real-time processor is used for The signal conversion subsystem performs scheduling; the second real-time processor is used to schedule the power-specific MAC module.

The power dedicated MAC module is used to process the subscribed Ethernet data packets according to the first time stamp provided by the time stamp management module to obtain power service data. The first time stamp includes the timestamp information of the Ethernet data packet processing; that is, the power dedicated The MAC module is equipped with a programmable message-specific processor implemented with a dedicated instruction set; the message-specific processor is used to filter and suppress storms for subscribed Ethernet data packets according to the first time stamp provided by the time stamp management module , to get the power business data.

The signal conversion subsystem is used to sample, transport and store the power business data in the power-specific MAC module according to the second time scale provided by the time-scale management module; the data processing module includes a power-specific digital signal processing array and a power-specific The first memory coupled to the digital signal processing array; the power-specific digital signal processing array is used to process the power service data in the signal conversion subsystem according to the specified algorithm to obtain the processed data in accordance with the preset format; the memory is used to process the processed data storage.

Among them, the signal conversion subsystem includes: an embedded processor, a second memory and a serial peripheral interface module; the embedded processor executes a specific embedded program according to the second time scale, and controls the external signal conversion chip to realize Sampling, transporting and storing the power service data in the power-specific MAC module, the second time scale includes the sampling time interval information of the power service data; the signal conversion subsystem and the signal conversion chip provide the serial Communication with the peripheral interface protocol; the second memory is used to store the embedded program and the power service data processed by the embedded processor; the signal conversion subsystem is configured as an 8-way interface, and the protocol mode of the serial peripheral interface module includes single-wire At least one of mode, two-wire mode and four-wire mode.

When it is detected that the data volume of the power service data in the power-specific MAC module is greater than the data volume threshold, the embedded processor executes a specific embedded program according to the second time scale, and controls the external signal conversion chip to realize power-specific The power business data in the MAC module is sampled and stored; the power business data in the power-specific MAC module is transported and processed through the memory access module in the signal conversion subsystem.

Optionally, the system includes a slave interface and a host interface; the slave interface and the host interface are used to integrate the system into a power system dedicated chip.

Specifically, the application processor of the power system dedicated chip can configure all configurable options in the power chip dedicated subsystem through the bus, and at the same time, the power chip dedicated subsystem can also access DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) through the bus , double data rate synchronous dynamic random access memory (DDR for short) controller, the DDR controller can access DDR storage, and for the storage of large amounts of data, it can be flexibly solved through DDR access; the dedicated subsystem of the power chip in the power SoC only After being initialized by the application processor, it can work on its own without occupying other resources of the SoC. The application processor can perform other tasks at this time. When the assigned work of the power chip dedicated subsystem is completed, it will notify the application through an interrupt signal The processor, on the basis of meeting the power data processing requirements, reduces system cost, power consumption and improves system stability.

For specific limitations on power system dedicated chips, please refer to the above-mentioned limitations on power chip dedicated subsystems, which will not be repeated here. Each module in the above-mentioned power system dedicated chip can be fully or partially realized by software, hardware and a combination thereof.

In one embodiment, a power device is provided, the power device may be a terminal, and its internal structure may be as shown in FIG. 5 . The electrical device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Wherein, the processor of the power device is used to provide calculation and control capabilities. The memory of the electric device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and programs. The internal memory provides an environment for the operation of the operating system and programs in the non-volatile storage medium. The communication interface of the power device is used for wired or wireless communication with an external terminal, and the wireless mode can be realized through WIFI, operator network, NFC (Near Field Communication) or other technologies. When the device program is executed by the processor, it realizes a dedicated subsystem related to the power chip. The display screen of the electric device may be a liquid crystal display screen or an electronic ink display screen, and the input device of the electric device may be a touch layer covered on the display screen, or a button or a touch panel provided on the device.

Those skilled in the art can understand that the structure shown in Figure 5 is only a block diagram of a part of the structure related to the solution of this application, and does not constitute a limitation on the power equipment to which the solution of this application is applied. The specific power equipment can be More or fewer components than shown in the figures may be included, or some components may be combined, or have a different arrangement of components.

In one embodiment, a power device is also provided, including a memory and a processor, where a computer program is stored in the memory, and the processor implements the functions in the above system embodiments when executing the computer program.

In one embodiment, a readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the functions in the above system embodiments are realized.

Those of ordinary skill in the art can understand that all or part of the processes in the system of the above embodiments can be realized through computer programs to instruct related hardware, and the computer programs can be stored in a non-volatile readable storage medium. When the computer program (device program) is executed, it may include the processes of the embodiments of the above-mentioned systems. Wherein, any references to memory, storage, database or other media used in the various embodiments provided in the present application may include at least one of non-volatile memory and volatile memory. Non-volatile memory may include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the range described in this specification.

The above examples only express several implementation modes of the present application, and the description thereof is relatively specific and detailed, but should not be construed as limiting the scope of the patent for the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application should be based on the appended claims.

Claims

A power chip dedicated subsystem, characterized in that it includes: a real-time processing module, a data processing module, a signal conversion subsystem, a time scale management module, and a power-specific MAC module; the real-time processing module, the data processing module, and the signal conversion sub-system The system, time stamp management module and power-specific MAC module are interconnected through the system bus;

The real-time processing module is used to schedule the data processing module, signal conversion subsystem, time scale management module and power-specific MAC module;

The power-specific MAC module is used to process the subscribed Ethernet data packets according to the first time stamp provided by the time stamp management module to obtain power service data;

The signal conversion subsystem is used to sample, transport and store the power service data in the power-specific MAC module according to the second time scale provided by the time scale management module;

The data processing module includes a power-specific digital signal processing array and a first memory coupled to the power-specific digital signal processing array; the power-specific digital signal processing array is used for power service data in the signal conversion subsystem Data processing is performed according to a specified algorithm to obtain processed data conforming to a preset format; the first memory is used to store the processed data.
The system according to claim 1, wherein the signal conversion subsystem comprises: an embedded processor, a second memory and a serial peripheral interface module;

The embedded processor executes a specific embedded program according to the second time scale, controls the external signal conversion chip, and implements sampling, handling and storage processing of the power service data in the power-specific MAC module; The signal conversion subsystem and the signal conversion chip communicate through the serial peripheral interface protocol provided by the serial peripheral interface module;

The second memory is used to store the embedded program and the power service data processed by the embedded processor.
The system according to claim 2, wherein the signal conversion subsystem further comprises a memory access module;

When it is detected that the data volume of the power service data in the power-specific MAC module is greater than the data volume threshold, the embedded processor executes a specific embedded program according to the second time scale to perform an external signal conversion chip control, to implement sampling and storage processing of the power service data in the power-specific MAC module; the memory access module is used to carry and process the power service data in the power-specific MAC module.
The system according to claim 2, wherein the mode of the serial peripheral interface module includes at least one of a single-wire mode, a two-wire mode and a four-wire mode.
The system according to claim 1, wherein the signal conversion subsystem is configured as an 8-way interface.
The system according to claim 1, wherein said power-specific MAC module is equipped with a programmable message-specific processor implemented with a dedicated instruction set; said message-specific processor is used to The first time stamp provided by the management module performs filtering and storm suppression processing on subscribed Ethernet data packets to obtain power service data.
The system according to claim 1, characterized in that the system comprises a slave interface and a host interface; the slave interface and the host interface are used to integrate the system into a power system dedicated chip.
The system according to claim 1, wherein the real-time processing module includes a first real-time processor and a second real-time processor, and the first real-time processor is used to schedule the signal conversion subsystem; the second real-time processor Two real-time processors are used to schedule the power-specific MAC modules.
The system according to claim 1, wherein the first time scale includes time stamp information of Ethernet data packet processing; and the second time scale includes sampling time interval information of power service data.
A power system dedicated chip, characterized in that the system described in any one of claims 1 to 9 is integrated on the power system dedicated chip.