CN101136754A - Data transmission control system of ethernet chip - Google Patents
Data transmission control system of ethernet chip Download PDFInfo
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- CN101136754A CN101136754A CNA2006101522767A CN200610152276A CN101136754A CN 101136754 A CN101136754 A CN 101136754A CN A2006101522767 A CNA2006101522767 A CN A2006101522767A CN 200610152276 A CN200610152276 A CN 200610152276A CN 101136754 A CN101136754 A CN 101136754A
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Abstract
The data transmission control system includes CPU, memory module, piece of PCI bridge, hardware logic unit (HLU), multiple Ethernet chip, and E1/T1 chip. The system also includes direct accessible common storage area (CSA) by HLU. CSA is in use for saving data received from and transmitted to by Ethernet chip and E1/T1 chip. HLU includes following parts: Ethernet control module in use for controlling data transmission of Ethernet chip; E1/T1 control module in use for configuring address of data received from and transmitted to by E1/T1, and in use for staring data interchange between Ethernet chip and E1/T1 chip; CPU in use for mapping address of CSA to space of system address as well as setting up address for Ethernet chip to receive and transmit data and data descriptor to the mapped address.
Description
Technical Field
The present invention relates to a data transmission control system of an ethernet chip, and in particular, to a data transmission control system of an ethernet chip in a multi-ethernet chip environment.
Background
At present, embedded communication devices generally have multi-channel communication and multi-protocol exchange Processing capabilities, and in order to ensure real-time performance of communication and process huge data traffic, a Central Processing Unit (CPU) in the device is required to have higher Processing capability. How to realize the processing capability of the communication equipment by using the existing CPU with lower performance on the premise of reducing equipment cost and power consumption as much as possible is one of the key points of research of communication equipment manufacturers.
At present, a commonly used embedded multi-ethernet communication device generally comprises a CPU unit, a memory unit, an ethernet chip, a hardware logic unit, and other devices. In addition to the memory unit, other units communicate via a PCI (peripheral Component Interconnect) bus, as shown in fig. 1. Currently, the commonly used hardware Logic is FPGA (Field Programmable Gate array), EPLD (Erasable Programmable Logic Device), etc., and the hardware Logic can complete the physical signal and data processing capability by matching, and in some application occasions, can replace the CPU to complete the data processing work.
In a multi-ethernet communication device, we divide ethernet chips into two categories from the application point of view: one type of ethernet chip is used for debug control and signaling transmission, and the other type of ethernet chip is used for transmission of service data. For the first type of Ethernet chip, the CPU needs to participate in the control of data transmission so that the CPU can analyze the signaling and process the related protocol; for the second type of ethernet chip, the CPU can control data transmission, but the CPU does not perform signaling extraction, and only performs data transfer and transparent transmission, but consumes a part of CPU processing capacity, and for the CPU with lower performance, sometimes it is not possible to complete concurrent processing of multiple ethernet data, and thus the system requirements cannot be met.
Disclosure of Invention
The technical problem to be solved by the present invention is to overcome the defects of the ethernet chip data transmission control technology in the prior art, and to provide a data transmission control system of an ethernet chip in a multi-ethernet chip environment, so that a communication device of a CPU with lower performance can complete multi-ethernet chip data transmission.
In order to solve the above problems, the present invention provides a data transmission control system of ethernet chip, which comprises a CPU, a memory module, a PCI bridge, a hardware logic unit, a plurality of ethernet chips and an E1/T1 chip; wherein the Ethernet chip 3 is used for the transmission of the service data, the system also includes the shared memory area that can be visited directly by the hardware logic unit, is used for keeping Ethernet chip 3 and E1/T1 chip receive and send the data; wherein,
the hardware logic unit is connected with the Ethernet chip 3 through a local bus and a PCI bus, and is connected with the E1/T1 chip through a data and control interface; the hardware logic unit comprises: the Ethernet control module is used for carrying out data transmission control on the Ethernet chip 3; the E1/T1 control module is used for configuring the address of the E1/T1 chip for receiving and sending data and starting data exchange between the Ethernet chip 3 and the E1/T1 chip;
and the CPU is connected with the Ethernet chip 3 and the hardware logic unit through a PCI bus and is used for mapping the address of the shared memory area to a system address space and setting the addresses of the transmitting and receiving data and the transmitting and receiving data descriptor of the Ethernet chip 3 as the mapped addresses.
Furthermore, the shared memory area may be located within the hardware logic unit and may be directly accessible by the Ethernet control module and the E1/T1 control module.
In addition, the shared memory area can be located outside the hardware logic unit, and the hardware logic unit comprises a memory interface through which the Ethernet control module and the E1/T1 control module access the shared memory area.
In addition, the hardware logic unit may be an FPGA device.
Furthermore, when the shared memory area is located outside the hardware logic unit, the hardware logic unit may be a CPLD/EPLD device.
The invention uses hardware logic unit to replace CPU to complete part of Ethernet chip data transmission control work, reduces CPU processing load, and makes communication device have transmission control ability of multiple Ethernet chips under condition of low system using performance CPU, thereby achieving effect of reducing device cost and energy consumption.
Drawings
Fig. 1 is a system configuration diagram of a data transmission control system of an ethernet chip of the present invention;
fig. 2 is a system configuration diagram of another embodiment of a data transmission control system of an ethernet chip of the present invention.
Detailed Description
The basic idea of the invention is that in a multi-Ethernet communication environment, Ethernet chips are classified according to functions, and for the Ethernet chip mainly used for service data transmission, a hardware logic unit is used to replace a CPU to perform transmission control on the Ethernet chip service data.
The present invention will be further described with reference to the accompanying drawings by taking a multi-ethernet communication device including 3 ethernet chips as an example.
Fig. 1 is a system configuration diagram of a data transmission control system of an ethernet chip of the present invention.
As shown in fig. 1, the communication device includes a CPU, a memory module, a PCI bridge, an FPGA, 3 ethernet chips, and 1E 1/T1 chip. Wherein:
the Ethernet chip 1 is used for transmitting signaling;
the Ethernet chip 2 is used for transmitting the signaling between the main single board and the standby single board;
the Ethernet chip 3 is used for transmitting service data;
the FPGA is connected with each Ethernet chip through a local bus and a PCI bus, and is connected with the E1/T1 chip through a data and control interface: the FPGA comprises: the Ethernet control module is used for carrying out data transmission control on the Ethernet chip 3; the E1/T1 control module is used for configuring the address of the E1/T1 chip for receiving and sending data and starting data exchange between the Ethernet chip 3 and the E1/T1 chip; a shared memory area for storing the receiving and sending data of the Ethernet chip 3 and the E1/T1 chip;
the CPU is connected with the memory module through a memory bus and is connected with the Ethernet chip 1, the Ethernet chip 2, the Ethernet chip 3, the FPGA and other equipment through a PCI bus; the device is used for carrying out basic initialization operations such as chip reset, port rate setting, duplex mode setting, physical address configuration and the like on the Ethernet chip 3 in the power-on process; and the address of the shared memory area inside the FPGA is mapped to a system address space, the mapped address is used for configuring the FPGA, the addresses of the receiving and sending data and the receiving and sending data descriptors of the Ethernet chip 3 are set as the mapped address, and meanwhile, the CPU performs transmission control on the Ethernet chip 1 and the Ethernet chip 2.
Fig. 2 is a system configuration diagram of another embodiment of a data transmission control system of an ethernet chip of the present invention.
As shown in fig. 2, the present invention can also be implemented using memory external to the FPGA but directly accessible by the FPGA, but the implementation of hardware logic using this approach is more complex and less real-time.
When a memory outside the FPGA is used as a shared storage area, a memory interface module is arranged in the FPGA and used for performing read-write access with the shared storage area. In addition, the CPU needs to map the address of the memory to a system address space, and configure the ethernet chip and the FPGA using the mapped address, so that the ethernet chip and the FPGA can use the memory to perform data operations.
Although the data transmission control system of the Ethernet chip of the invention is adopted, the CPU gives the transmission control of the Ethernet chip to the hardware logic unit, the CPU can still inquire the working state and the information of the Ethernet chip through the PCI bus interface and is used for system detection and diagnosis processing.
Practical tests prove that when the Ethernet chips all adopt Intel ER82551 and E1/T1 processing chips adopt Dallas DS21455, the data transmission control system of the Ethernet chip of the invention is adopted to carry out transmission control on one Ethernet chip through FPGA, and the utilization rate of the CPU can be reduced by more than 30%.
The Ethernet chip data transmission control system is simple and practical, and has abundant and huge application potential along with the wide application of various real-time Ethernet communication devices in different fields.
Claims (5)
1. A data transmission control system of an Ethernet chip comprises a CPU, a memory module, a PCI bridge chip, a hardware logic unit, a plurality of Ethernet chips and an E1/T1 chip; wherein the Ethernet chip (3) is used for the transmission of traffic data,
the system also comprises a shared memory area directly accessible by the hardware logic unit for storing the received and transmitted data of the Ethernet chip (3) and the E1/T1 chip; wherein,
the hardware logic unit is connected with the Ethernet chip (3) through a local bus and a PCI bus, and is connected with the E1/T1 chip through a data and control interface; the hardware logic unit comprises: the Ethernet control module is used for carrying out data transmission control on the Ethernet chip (3); the E1/T1 control module is used for configuring the address of the E1/T1 chip for transmitting and receiving data and starting data exchange between the Ethernet chip (3) and the E1/T1 chip;
and the CPU is connected with the Ethernet chip (3) and the hardware logic unit through a PCI bus and is used for mapping the shared memory area address to a system address space and configuring the FPGA and the Ethernet chip (3) by using the mapped address.
2. The data transmission control system of an ethernet chip according to claim 1, wherein said shared memory area is located inside a hardware logic unit, directly accessed by the ethernet control module and the E1/T1 control module.
3. The data transmission control system of an ethernet chip according to claim 1, wherein said shared memory area is located outside a hardware logic unit, the hardware logic unit comprising a memory interface, the ethernet control module and the E1/T1 control module accessing the shared memory area through the memory interface.
4. The data transmission control system of an ethernet chip according to claim 1, 2 or 3, wherein said hardware logic unit is an FPGA device.
5. The data transmission control system of an ethernet chip according to claim 3, wherein said hardware logic unit is a CPLD/EPLD device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNA2006101522767A CN101136754A (en) | 2006-09-27 | 2006-09-27 | Data transmission control system of ethernet chip |
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| CNA2006101522767A CN101136754A (en) | 2006-09-27 | 2006-09-27 | Data transmission control system of ethernet chip |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101963948A (en) * | 2010-08-26 | 2011-02-02 | 北京航空航天大学 | BMCH protocol data transceiver module based on CPCI bus |
| CN102480426A (en) * | 2010-11-25 | 2012-05-30 | 迈普通信技术股份有限公司 | Communication method based on peripheral component interconnect-express (PCIE) switching bus and PCIE switching system |
| CN102495820A (en) * | 2011-11-24 | 2012-06-13 | 中国航空工业集团公司第六三一研究所 | Special aviation multi-interface maintenance method and special aviation multi-interface maintenance system |
| CN102647321A (en) * | 2012-05-16 | 2012-08-22 | 浙江中控研究院有限公司 | Data transmission device between Ethernet for plant automation (EPA) bus and controller area network (CAN) bus |
| CN102754397A (en) * | 2010-02-12 | 2012-10-24 | 株式会社日立制作所 | Information processing device, and method of processing information upon information processing device |
| CN101668233B (en) * | 2008-09-01 | 2013-01-16 | 中兴通讯股份有限公司 | Hardware device and method for assisting in processing dynamic bandwidth allocation algorithm |
| CN105743668A (en) * | 2014-12-09 | 2016-07-06 | 中兴通讯股份有限公司 | Method and device for achieving function of package transmitting and receiving |
| WO2019136983A1 (en) * | 2018-01-12 | 2019-07-18 | 江苏华存电子科技有限公司 | Low-delay instruction scheduler |
| CN111752895A (en) * | 2020-06-28 | 2020-10-09 | 北京经纬恒润科技有限公司 | Log storage method and device among multi-system-level chips |
-
2006
- 2006-09-27 CN CNA2006101522767A patent/CN101136754A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101668233B (en) * | 2008-09-01 | 2013-01-16 | 中兴通讯股份有限公司 | Hardware device and method for assisting in processing dynamic bandwidth allocation algorithm |
| CN102754397A (en) * | 2010-02-12 | 2012-10-24 | 株式会社日立制作所 | Information processing device, and method of processing information upon information processing device |
| CN101963948A (en) * | 2010-08-26 | 2011-02-02 | 北京航空航天大学 | BMCH protocol data transceiver module based on CPCI bus |
| CN101963948B (en) * | 2010-08-26 | 2012-10-24 | 北京航空航天大学 | BMCH protocol data transceiver module based on CPCI bus |
| CN102480426A (en) * | 2010-11-25 | 2012-05-30 | 迈普通信技术股份有限公司 | Communication method based on peripheral component interconnect-express (PCIE) switching bus and PCIE switching system |
| CN102480426B (en) * | 2010-11-25 | 2014-07-09 | 迈普通信技术股份有限公司 | Communication method based on peripheral component interconnect-express (PCIE) switching bus and PCIE switching system |
| CN102495820A (en) * | 2011-11-24 | 2012-06-13 | 中国航空工业集团公司第六三一研究所 | Special aviation multi-interface maintenance method and special aviation multi-interface maintenance system |
| CN102647321A (en) * | 2012-05-16 | 2012-08-22 | 浙江中控研究院有限公司 | Data transmission device between Ethernet for plant automation (EPA) bus and controller area network (CAN) bus |
| CN102647321B (en) * | 2012-05-16 | 2014-10-29 | 浙江中控研究院有限公司 | Data transmission device between Ethernet for plant automation (EPA) bus and controller area network (CAN) bus |
| CN105743668A (en) * | 2014-12-09 | 2016-07-06 | 中兴通讯股份有限公司 | Method and device for achieving function of package transmitting and receiving |
| WO2019136983A1 (en) * | 2018-01-12 | 2019-07-18 | 江苏华存电子科技有限公司 | Low-delay instruction scheduler |
| CN111752895A (en) * | 2020-06-28 | 2020-10-09 | 北京经纬恒润科技有限公司 | Log storage method and device among multi-system-level chips |
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