CN105426562B - The UART means of communication and device between a kind of more I/O modules and more communication modules - Google Patents
The UART means of communication and device between a kind of more I/O modules and more communication modules Download PDFInfo
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Abstract
The present invention relates to industrial communication fields, provide the UART means of communication between a kind of more I/O modules and more communication modules, communicate for m I/O module and the multi-to-multi of n communication module, wherein m and n is integer and 1≤m≤16,1≤n≤3；Clock frequency division module, receiving module, sending module, IO selecting module, communication selecting module and top-level module based on FPGA are set up between the m I/O module and n communication module, to realize that specific a certain communication module and the UART of I/O module are communicated between more I/O modules and more communication modules.The UART means of communication and device between more I/O modules of the invention and more communication modules, it realizes I/O module and communication module multi-to-multi communicates, improve the performance of system, it reduces costs simultaneously, improve the working efficiency of industrial automation equipment, practical value with higher and good application prospect.
Description
Technical field
The present invention relates to the UART communications between industrial communication field more particularly to a kind of more I/O modules and more communication modules
Method and device.
Background technique
Rapid development industrial communication technology with computer communication technology and the information processing technology has become a weight
Technology is wanted, is all widely used in industry and the communications field.Device network has become a common recognition, becomes inevitable
Trend.Serial communication is one of essential function for device network.The stabilization of serial communication is efficiently also meter
Calculation machine communicates the target pursued always.
Universal asynchronous receiver/transmitter (UART) UART (Universal Asynchronous Receiver and
Transmitter data) can be sent and received under serial mode, data mode only needs a pair of of route real
Existing remote data communication.The standard set of simple, long transmission distance, the features such as being easily achieved as various processors with its resource
At one of peripheral hardware.Especially tend to mature SOC (System On Chip System on Chip/SoC) skill in IC design field
For art using inner, UART has become one of indispensable peripheral hardware.In actual application design, multiple masters of UART are often used
Function is wanted, is often resulted in waste of resources with Special Interface Chip (NI8250 of such as IBM) and is improved with cost.
FPGA is the product further developed on the basis of the programming devices such as traditional PAL, GAL, and use is very clever
It is living, it can produce different circuit functions by different programming datas with a piece of FPGA.With advancing by leaps and bounds for FPGA technology,
It is obtained in various fields such as communication system, data processing, network communication, instrument and meter, Industry Control, military affairs and aerospaces
It is more and more widely used.
In order to improve the working efficiency of industrial automation equipment, control system need to use modular strategy, and I/O module connects
Field device and communication module are connect, the acquisition and communication for field data；Communication module link control module and I/O module are used
The transmission of valid data in control system；But I/O module and the one-to-one communication of communication module, cannot complete multitask and
The requirement of row processing, and higher cost.The performance of system can be improved using I/O module and the communication of communication module multi-to-multi, together
When can reduce cost.
Summary of the invention
The invention proposes the UART means of communication and device between a kind of more I/O modules and more communication modules, utilize FPGA
It is selected to solve the problems, such as that the UART of communication module and I/O module receives and dispatches port, to realize I/O module and communication module multi-to-multi
Communication.
Specifically, to solve the above-mentioned problems, present invention employs following technical solutions:
The UART means of communication between a kind of more I/O modules and more communication modules, for m I/O module and n communication module
Multi-to-multi communication, wherein m and n is integer and 1≤m≤16,1≤n≤3, the m I/O module and n communication module it
Between set up clock frequency division module based on FPGA, receiving module, sending module, IO selecting module, communication selecting module and top layer
Module；
The clock frequency division module is sampled using the clock of 16 haplotype data baud rates, and each data occupy 16 clocks
Sampling period, using the intermediate time of each data bit as sampled point, to guarantee that sampling will not slip or error code；
The receiving module is set as n, receives the data sent from communication module CPU, and constantly carry out Sequence Detection；
When detecting the data for making a reservation for unified communication format, exports two high level signals and be separately sent to the communication selection mould
Block and sending module；The signal for being sent to the communication selecting module represents the online situation of the communication module, high level epoch
Table module is online；The signal for being sent to the sending module is a transmission initial signal；
The sending module is set as n, and the Data Concurrent for receiving I/O module is sent in communication module；When receiving the hair
After sending initial signal, feedback information is sent to the CPU of communication module as responding, the feedback information is sent completely into idle
After state, mouth is sent according to the information selection of the communication selecting module is suitable, continues to send the number received from I/O module
According to arrive communication module；；
The IO selecting module successively gates the communication of the road m I/O module by 4 data that a cycle changes；
The communication selecting module carries out the voting of n communication module and its selection at communication receiving/transmission end, reads；When n
When the online situation of any one communication module in communication module is sent out into variation, online preferential is selected using redundant diagnostic mechanism
The highest communication module of grade is main communication module, communication module supplemented by remaining is online.
The top-level module selects the clock frequency division module, receiving module, sending module, IO selecting module, communication
The signal of module is connected to become an entirety, carries out internal coordination and communication.
Further, after the sending module receives transmission initial signal, the feedback information of transmission includes communication device
Module address, communication module online information and major-minor information.
Further, the quantity of the communication module is 3, i.e. n=3；3 communication modules are respectively equipped with independent
One group of sending and receiving end is additionally provided with one group of shared sending and receiving end.
Further, the quantity of the I/O module is 16, i.e. m=16；16 I/O modules are divided into most-significant byte and least-significant byte；When
When I/O module and communication module are received and sent messages, common transmit-receive end transmitting-receiving of the least-significant byte I/O module by 3 communication modules, most-significant byte IO
The independent sending and receiving end transmitting-receiving that module passes through 3 communication modules.
The present invention also provides a kind of UART means of communication using between above-mentioned more I/O modules and more communication modules
Communication device is communicated for m I/O module and the multi-to-multi of n communication module, wherein and m and n is integer and 1≤m≤16,1≤
N≤3, it is characterised in that: including a FPGA, the clock frequency division module is equipped with based on the FPGA, receiving module, sends mould
Block, IO selecting module, communication selecting module and top-level module.
Further, the quantity of the I/O module is 16, i.e. m=16, and the quantity of the communication module is 3, i.e. n=
3；Wherein, 16 I/O modules are divided into most-significant byte and least-significant byte, and 3 communication modules are respectively equipped with one group of sending and receiving end independent, also
Equipped with one group of shared sending and receiving end；When I/O module and communication module are received and sent messages, the data of least-significant byte I/O module are logical by 3
Interrogate the common transmit-receive end transmitting-receiving of module, the independent sending and receiving end transmitting-receiving that the data of most-significant byte I/O module pass through 3 communication modules.
The UART means of communication between more I/O modules of the invention and more communication modules, based on FPGA design clock division
Module, receiving module, sending module, IO selecting module, communication selecting module and top-level module, by the receipts for selecting communication module
Hair mouth realizes that the UART of specific a certain communication module and I/O module is communicated with the transmitting-receiving mouth of corresponding I/O module.Specifically,
The present invention is added to communication selecting module and IO selecting module in the existing UART means of communication, and passes through communication selection mould
Block selects online and highest priority communication module to be communicated in turn to detect the online situation of communication module；Pass through IO
Selecting module selects specific a certain I/O module to be communicated, to realize more using 4 data AD of a cycle variation
Specific a certain communication module and the UART of I/O module are communicated between I/O module and more communication modules.
UART communication device between more I/O modules of the invention and more communication modules, is devised using the above method and is based on
The clock frequency division module, receiving module, sending module, IO selecting module, communication selecting module and the top-level module of FPGA, it is real
I/O module is showed and communication module multi-to-multi communicates, improved the performance of system, reduce costs simultaneously, has improved industrial automatic
Change the working efficiency of equipment, practical value with higher and good application prospect.
Detailed description of the invention
The schematic diagram of UART communication device of the Fig. 1 between more I/O modules of the invention and more communication modules.
Specific embodiment
For a further understanding of the present invention, the preferred embodiment of the invention is described below with reference to embodiment, still
It should be appreciated that these descriptions are only further explanation the features and advantages of the present invention, rather than to the claims in the present invention
Limitation.
In conjunction with specific embodiment, invention is further explained.
The UART means of communication between more I/O modules proposed by the present invention and more communication modules contain 16 I/O modules with
The communication module of triple redundance, mainly by selecting the transmitting-receiving mouth of communication module and corresponding IO mould based on the particular module of FPGA
The transmitting-receiving mouth of block realizes that the UART of specific a certain communication module and I/O module is communicated.
The present invention is added to two modules in the existing UART means of communication to realize required function: first is that logical
Selecting module is interrogated, it can be by detecting the online situation of communication module to which selection is online and the communication mould of highest priority
Block is communicated；Second is that IO selecting module module, it selected by one four data specific a certain I/O module into
Row communication.
Specifically, the present invention is based on one top-level module of FPGA design and five submodules, respectively clock division mould
Block, receiving module, sending module, IO selecting module and communication selecting module, are described as follows:
1) clock frequency division module
Since UART is asynchronous transmission, synchronised clock is not transmitted.In order to can guarantee the correctness of data transmission, UART is adopted
It is sampled with the clock of 16 haplotype data baud rates.Each data occupy 16 clock sampling periods, will be in each data bit
Between the moment as sampled point, to guarantee that sampling will not slip or error code.The data bits of mono- frame of general UART is 8, accordingly even when
Each data have the error of a clock, and receiving end also can correctly sample data.Here common data baud rate is used
For 19200bps, then the frequency of required clock is 16 × 19200.System clock is 20MHz, then frequency division coefficient is 20000000/
(16 × 19200)=65.10, take 64 here.
2) sending module and receiving module
Since the means of communication between more I/O modules proposed by the present invention and more communication modules devise the communication of triple redundance
Module, therefore three identical sending modules and receiving module are contained in code top-level procedure altogether, only divide on hardware
Not Dui Ying three communication modules pin.Receiving module constantly receives the data sent from communication module CPU, and constantly carries out
Sequence Detection, whenever detecting the data of our unified communication formats, it can export two high level signals and send out respectively
It is sent to communication selecting module and sending module.The signal for being sent to communication selecting module represents the online situation of the module, high electricity
It is online usually to represent module；The signal for being sent to sending module is a transmission initial signal.Sending module can will receive
The data of I/O module are sent in communication module, and the high level for receiving receiving module every time will be cut after sending initial signal
It changes and send mouth, the module address of entire pedestal, the online information of communication module and major-minor information are sent back to the CPU of communication module
In, continue to send the data received from I/O module again after distributing these information.
3) IO selecting module
The module realizes the selection of 16 I/O modules in communication process.Specifically, pass through one group 4 binary numbers,
It each can represent this 16 modules, and this group of binary number is generated from the CPU of communication module, and can periodically be changed
So as to successively select this 16 I/O modules.In specific design, 16 I/O modules can be divided into most-significant byte and least-significant byte again.?
In communication device hardware design, three communication modules are shared in addition to there is one group of sending and receiving end independent respectively there are also one group
Sending and receiving end.In this 16 I/O modules, least-significant byte is received and dispatched by sharing serial ports, and most-significant byte is received and dispatched by independent serial ports.
4) selecting module is communicated
The module mainly carries out redundancy processing according to the online situation of communication module, selects communication module sending and receiving data,
And base address and offset address are sent to communication module.
Specifically, the module realizes the voting of three road communication modules and its selection at communication receiving/transmission end, reads.The present invention
The module address in communication device between the more I/O modules proposed and more communication modules is simultaneously sent to three communication modules respectively
Respective offset address.In voting mechanism, the priority of three road communication modules is all different, and is existed in any one communication module
When line situation hair is at variation, it will do it the selection of communication module in program, online highest priority selected according to priority
For main communication module, supplemented by remaining is online.In addition, module address is also dealt into sending module with offset address to send by it
Module receives every time can send these information into the CPU of communication module when sending initial signal.
In a specific embodiment, c_state be the online situation of communication module, c_main be redundancy treated letter
Breath, redundancy processing method such as table 1.
| c_state(c2_state,c1_state,c0_state) | c_main |
| 000 | 000 |
| 001 | 001 |
| 010 | 010 |
| 011 | 001 |
| 100 | 100 |
| 101 | 001 |
| 110 | 010 |
| 111 | 001 |
1 communication module online information of table and its redundancy processing
5) top-level module
The signal of above-mentioned each submodule is connected to become an entirety by a large amount of wire lines in top-level module.
Based on the above method, the present invention provides the UART communication devices between a kind of more I/O modules and more communication modules.
In one embodiment, including a FPGA, clock frequency division module, receiving module, sending module, IO choosing are equipped with based on the FPGA
Module, communication selecting module and top-level module are selected, is communicated for 16 I/O modules and the multi-to-multi of 3 communication modules, it is specific logical
News mode is shown in above method content.
The UART means of communication and device between more I/O modules of the invention and more communication modules realize I/O module and lead to
The communication of module multi-to-multi is interrogated, the performance of system is improved, reduces costs simultaneously, improves the work effect of industrial automation equipment
Rate, practical value with higher and good application prospect.
The explanation of upper embodiment is merely used to help understand method and its core concept of the invention.It should be pointed out that for
For those skilled in the art, without departing from the principle of the present invention, if can also be carried out to the present invention
Dry improvement and modification, these improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims (6)
1. the UART means of communication between a kind of more I/O modules and more communication modules, for m I/O module and n communication module
Multi-to-multi communication, wherein m and n is integer and 1≤m≤16,1≤n≤3, it is characterised in that:
Clock frequency division module, receiving module, transmission based on FPGA are set up between the m I/O module and n communication module
Module, IO selecting module, communication selecting module and top-level module；
The clock frequency division module is sampled using the clock of 16 haplotype data baud rates, and each data occupy 16 clock samplings
Period, using the intermediate time of each data bit as sampled point, to guarantee that sampling will not slip or error code；
The receiving module is set as n, receives the data sent from communication module CPU, and constantly carry out Sequence Detection；Work as inspection
When measuring the data for making a reservation for unified communication format, export two high level signals be separately sent to the communication selecting module and
Sending module；The signal for being sent to the communication selecting module represents the online situation of the communication module, and when high level represents mould
Block is online；The signal for being sent to the sending module is a transmission initial signal；
The sending module is set as n, and the Data Concurrent for receiving I/O module is sent in communication module；When receiving described send
After beginning signal, feedback information is sent to the CPU of communication module as responding, the feedback information is sent completely into idle state
Afterwards, send mouth according to the information selection of the communication selecting module is suitable, continue to send the data that are received from I/O module to
Communication module；
The IO selecting module successively gates the communication of the road m I/O module by 4 data that a cycle changes；
The communication selecting module carries out the voting of n communication module and its selection at communication receiving/transmission end, reads；It is communicated when n
When any one communication module in module happens variation online, online priority is selected most using redundant diagnostic mechanism
High communication module is main communication module, communication module supplemented by remaining is online；
The top-level module by the clock frequency division module, receiving module, sending module, IO selecting module, communication selecting module
Signal be connected to become an entirety, carry out internal coordination and communication.
2. the UART means of communication between more I/O modules as described in claim 1 and more communication modules, it is characterised in that: described
After sending module receives transmission initial signal, the feedback information of transmission includes the module address of communication device, communication module
Online information and major-minor information.
3. the UART means of communication between more I/O modules as described in claim 1 and more communication modules, it is characterised in that: described
The quantity of communication module is 3, i.e. n=3；3 communication modules are respectively equipped with one group of sending and receiving end independent, are additionally provided with one group
Shared sending and receiving end.
4. the UART means of communication between more I/O modules as claimed in claim 3 and more communication modules, it is characterised in that: described
The quantity of I/O module is 16, i.e. m=16；16 I/O modules are divided into most-significant byte and least-significant byte；When I/O module and communication module are received and dispatched
When information, least-significant byte I/O module is received and dispatched by the common transmit-receive end of 3 communication modules, and most-significant byte I/O module passes through 3 communication modules
Independent sending and receiving end transmitting-receiving.
5. a kind of UART means of communication using between more I/O modules according to any one of claims 1-4 and more communication modules
Communication device, it is characterised in that: including a FPGA, the clock frequency division module, receiving module, hair are equipped with based on the FPGA
Send module, IO selecting module, communication selecting module and top-level module.
6. communication device as claimed in claim 5, it is characterised in that: the quantity of the I/O module is 16, i.e. m=16, institute
The quantity for stating communication module is 3, i.e. n=3；Wherein, 16 I/O modules are divided into most-significant byte and least-significant byte, 3 communication module difference
Equipped with one group of sending and receiving end independent, it is additionally provided with one group of shared sending and receiving end；When I/O module and communication module are received and sent messages,
The data of least-significant byte I/O module are received and dispatched by the common transmit-receive end of 3 communication modules, and the data of most-significant byte I/O module pass through 3 communications
It receives and dispatches the independent sending and receiving end of module.
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| CN116760659B (en) * | 2023-08-11 | 2023-11-14 | 浙江国利信安科技有限公司 | Programmable logic controller and data communication method thereof |
| CN116996340B (en) * | 2023-09-25 | 2023-12-01 | 湖南宇诺辰电子科技有限公司 | CAN (controller area network) receiving and transmitting method and CAN receiving and transmitting system |
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Address after: No.6, Lingang Road, Renhe street, Yuhang District, Hangzhou City, Zhejiang Province Patentee after: HANGZHOU UWNTEK AUTOMATION SYSTEM Co.,Ltd. Address before: 310051, room 8, floor 33, Xincheng Road, Binjiang District, Zhejiang, Hangzhou 807, China Patentee before: HANGZHOU UWNTEK AUTOMATION SYSTEM Co.,Ltd. |