CN102882754A - Repeated interrupt mode 485 direction control method - Google Patents

Repeated interrupt mode 485 direction control method Download PDF

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Publication number
CN102882754A
CN102882754A CN201210372192XA CN201210372192A CN102882754A CN 102882754 A CN102882754 A CN 102882754A CN 201210372192X A CN201210372192X A CN 201210372192XA CN 201210372192 A CN201210372192 A CN 201210372192A CN 102882754 A CN102882754 A CN 102882754A
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chip
rts
max485
control
mode
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CN102882754B (en
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范三龙
张�林
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Nanjing Guodian Nanzi Railway Traffic Engineering Co Ltd
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Nanjing Guodian Nanzi Railway Traffic Engineering Co Ltd
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Abstract

The invention relates to a repeated interrupt mode RTS/485 direction control method. A 16550 UART (universal asynchronous receiver/transmitter) compatible control chip is a standard serial port controller of a PC (personal computer) and widely used in an embedded system, and RTS signals of the control chip can be used for 485 bus transceiving direction control, RTS pin signals are controlled by the interrupt generation mode, enabling signals transmitted by the 485 bus can be recovered in time, the purpose of accurate control of the 485 bus direction can be achieved without modifying hardware design, and the repeated interrupt mode 485 bus direction control method is applicable to communication of medium and high speed 485 buses. Besides, for low-speed 485 communication, time delay control mode can still be adopted.

Description

Repeated interruptions mode 485 direction-controlling methods
Technical field
The invention belongs to Industry Control and power system automation technology field, relate to a kind of repeated interruptions mode RTS/485 direction-controlling method.
Background technology
Development along with power system automation technology, a large amount of uses of smart machine in the transformer and distribution station, therefore exchanges data between smart machine and system seems more and more important, connects and the indispensable visual plant of managing data communication interface between each equipment and system and become the Automation of Electric Systems system.
The RS-485 serial line interface is Industry Control and power system automatic field low speed long haul communication interface commonly used.
RS-485 develops from RS-232, RS-422 basis.RS485 adopts the differential signal negative logic ,+2V~+ 6V represents " 0 " ,-6V~-2V represents " 1 ".RS485 has two-wire system and two kinds of wiring of four-wire system, four-wire system can only realize point-to-point communication mode, existing seldom employing, and many employings is the two-wire system mode of connection now, this mode of connection is the bus type topological structure, can articulate at most 32 nodes on same bus.General employing is the master-slave communication mode in the RS485 communication network, i.e. a plurality of slaves of main frame band.
RS-485 has 2 holding wires: sending and receiving all is A and B, adopts the differential level mode to transmit and allow and articulates a plurality of nodes at a communication bus.Because the receipts of RS-485 are to share two lines with sending out, each node of inevitable requirement independently control bus driver turn-offs or opens the normal communication that assurance can not have influence on other node, so can not receive simultaneously and send out the individual node on bus, the transmitting-receiving enable signal of control bus chip switches transmit-receive position accurately.
For 485 buses of bus-type, the control of the transmit-receive position of 485 control chips is the basic problem that needs solve.At present, the main method of 485 transmit-receive positions control has directly control, specialized hardware control, the automatic direction control of 485 bus transceiving chips etc. after the control of RTS signal lag, the TX/DI signal inversion.Wherein, be based on the common practice of 485 interface equipments of PC by the transmit-receive position of RTS signal lag control 485, produce the system timer control of usefulness in the traditional design, when sending aerial disconnected the arrival, set the timer of a byte time, after timer time arrives, regain the RTS signal.But the non-real time operating system that similar Windows is such, highest resolution of nuclear clock is exactly 1ms in it, the precision of timer is between 1-2ms, when 9600 baud rate, 1 byte time is about 1ms, the actual measurement timer can cause the transmission driver of MAX485 to open the above time of 1 byte more, can have problems when 485 terminal rooms are communicated by letter at a high speed.Because the restriction of the clock resolution of operating system, the precision of time-delay control is lower, can not meet the demands when 485 communication of high speed degree.
Summary of the invention
The objective of the invention is in order to solve in the existing design, during high speed 485 communication, the accurate control problem of the transmit-receive position of 485 control chips has proposed a kind of new control method.
Technical scheme of the present invention is:
1: adopt the compatible UART chip of 16C550
Adopted the compatible UART chip of 16C550 in a large amount of ripe designs, such as ST16C554.Have following characteristics: technical grade, 5V or 3.3V power supply, the acceptance of 16 bytes and transmission FIFO support the highest 1.5Mbps speed.The register set of 16C550 compatibility, 4 tunnel independence UART passages are supported MODEM control.
2: adopt MAX485 bus transceiving chip.
3: adopt the FIFO interrupt mode to send.
Each transmission can write 16 bytes to 16C554 at most, during reception, according to setting, produces when receiving 1,2,4 or 14 byte continuously and interrupts, and perhaps produces after the byte stream that receives stops approximately 5 byte times and interrupts.
4: enable 485 transmissions after adopting the RTS signal inversion, realize the control of 485 transmit-receive positions.
Every road UART has independently the MODEM such as RTS, DTR control pin, and wherein the RTS pin is usually used in the control of 485 transmit-receive positions after anti-phase.Before each frame serial data sends, enable RTS, and then open the transmission driver of MAX485 chip.Then begin process of transmitting.Regain the RTS signal after sending end, close the transmission driver of MAX485 chip, MAX485 enters accepting state.
5: when sending disconnected arrival in the air, repeat to enable to send aerial breaking, and detect the TSR(shift register) sky sign, after TSR sky sign produces, withdrawal RTS signal.
Because the compatible UART controller of 16C550 does not have automatic RTS control, and does not produce interruption when TSR is empty, bring very large difficulty for program control RTS.And use the repeated interruptions mode, or similar real time polling mode, by initiatively checking the sky sign of TSR, regain the RTS signal, reach the purpose of accurate control.
Preferred version of the present invention is, the A chip is the ST16C554D chip, ST16C554D is the UART control chip of a 16C550, WINDOWS operating system compatibility, 4 tunnel serial ports passages are independently arranged, each paths only uses TX, RX, RTS signal in the line side, these 3 signals are after isolating through optocoupler T1-T3, DI, the DE and the RD pin that connect the MAX485 chip, wherein pass through inverter U4 between RTS and the DE, the DE of MAX485 chip and/RE signal and connecing, MAX485 is operated in semiduplex mode.
Preferred version of the present invention is, the bus transceiving chip among the B is that MAX481 or MAX483 or MAX485 or MAX487 – MAX491 are the low-power consumption RS-485/RS-422 bus transceivers of commonly using, and has and independently receives and dispatches the loop, supports half-duplex and full-duplex operation.
The invention has the beneficial effects as follows:
1, the present invention has utilized the transmission of the compatible UART chip of ST16C554D to interrupt enabling characteristic, by the mode of repeatedly interrupting, poll TSR(shift register) the sky sign.Because the real-time of interrupt processing, the present invention can accurately control transmission, the accepting state switching time of RTS signal, MAX485.
2, the present invention is applicable to above middle and high fast 485 communications of 9600 baud rates, can on the basis that does not change the existing hardware design, improve control precision.
3, adopt current hardware scheme, need not to change existing hardware, only need on drive software, slightly make an amendment, can realize that 485 control chip transmit-receive positions accurately control.The present invention tries out in WTX-65A/U series communicator, has obtained good effect, has certain applicability and application prospect.
Description of drawings
Fig. 1 is the electrical schematic diagram of the general RS-485 serial communication interface of the embodiment of the invention.
Fig. 2 is the interruption process chart of the embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is further elaborated.
A kind of repeated interruptions mode 485 direction-controlling methods comprise following structure and step, and A, chip adopt the compatible UART chip of 16C550, B, employing bus transceiving chip,
C, employing FIFO interrupt mode send, each transmission can write 16 bytes to 16C554 at most, during reception, according to setting, when continuously receiving 1,2,4 or 14 byte, produce and interrupt, perhaps after the byte stream that receives stops approximately 5 byte times, produce and interrupt;
D, adopt and to enable 485 after the RTS signal inversion and send, realize the control of 485 transmit-receive positions, every road UART has the independently MODEM such as RTS, DTR control pin, and wherein the RTS pin is usually used in the control of 485 transmit-receive positions after anti-phase.Enable RTS before each frame serial data sends, and then open the transmission driver of MAX485 chip, then begin process of transmitting, regain the RTS signal after sending end, close the transmission driver of MAX485 chip, MAX485 enters accepting state;
E, when sending aerial disconnected the arrival, repeat to enable to send aerial disconnected, and detect the TSR(shift register) the sky sign, after the empty sign of TSR produces, regain the RTS signal.
Among Fig. 1, ST16C554D is the UART control chip of a 16C550, WINDOWS operating system compatibility, and 4 tunnel serial ports passages are independently arranged.In industry and power automatic system communications applications, each paths only uses TX, RX, RTS signal in the line side.These 3 signals connect DI, DE and the RD pin of MAX485 chip after isolating through optocoupler T1-T3, wherein process inverter U4 between RTS and the DE.The DE of MAX485 chip and/RE signal and connecing, close receiving loop when enabling to send, MAX485 is operated in semiduplex mode.
In initial condition, the RTS invalidating signal, MAX485 is in accepting state.When having data to send, at first enable RTS, the MAX485 chip is placed the transmission state, then send frame data.After being sent completely, need in time to regain (resetting) RTS signal, the MAX485 chip is placed accepting state, in order to receive the other side's response.If fail in time to regain the RTS signal, when the other side respond very fast the time, can not correctly receive the header byte in the back message using.
Fig. 2 is the process chart that serial ports interrupts.Multi-serial-port card shares an interrupt signal.When interrupt signal occured, CPU at first judged it is the interruption which serial ports occurs, and obtains the string slogan.Then read the status register of corresponding serial ports, judgement is receive interruption or sends interruption.If receive interruption reads receive data, be saved in the reception buffer zone in the internal memory.Whether interrupt if send, checking has data to send.If have, then enable the RTS signal, the MAX485 chip is placed the transmission state, then write the transmission data to ST16C554D.Wait for next time and interrupting.If do not have data to send, then check the TSR(shift register) the sky sign.If be not empty, then again enable to send and interrupt, wait for next time and interrupting.If be empty, (withdrawal) RTS signal that then resets places accepting state with the MAX485 chip, and a frame process of transmitting finishes.
Above demonstration and described basic principle of the present invention and principal character and advantage of the present invention.The technical staff of the industry should be appreciated that; the present invention is not restricted to the described embodiments; that describes in above-described embodiment and the specification just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications; these changes and improvements all fall in the claimed scope of the invention, and the claimed scope of the present invention is defined by its equivalent of appending claims.

Claims (3)

1. repeated interruptions mode 485 direction-controlling methods comprise following structure and step: A, chip, adopt the compatible UART chip of 16C550, and B, employing bus transceiving chip is characterized in that,
C, employing FIFO interrupt mode send, each transmission can write 16 bytes to 16C554 at most, during reception, according to setting, when continuously receiving 1,2,4 or 14 byte, produce and interrupt, perhaps after the byte stream that receives stops approximately 5 byte times, produce and interrupt;
Enabling 485 after D, the employing RTS signal inversion sends, realize the control of 485 transmit-receive positions, every road UART has the independently MODEM such as RTS, DTR control pin, wherein the RTS pin is usually used in the control of 485 transmit-receive positions after anti-phase, enables RTS before each frame serial data sends, and then opens the transmission driver of MAX485 chip, then begin process of transmitting, regain the RTS signal after sending end, close the transmission driver of MAX485 chip, MAX485 enters accepting state;
E, when sending aerial disconnected the arrival, repeat to enable to send aerial disconnected, and detect the sky sign of shift register TSR, after the empty sign of TSR produces, regain the RTS signal.
2. repeated interruptions mode 485 direction-controlling methods according to claim 1, it is characterized in that, chip is the ST16C554D chip, ST16C554D is the UART control chip of a 16C550, WINDOWS operating system compatibility, 4 tunnel serial ports passages are independently arranged, each paths only uses TX, RX, RTS signal in the line side, these 3 signals are after isolating through optocoupler T1-T3, DI, the DE and the RD pin that connect the MAX485 chip, wherein pass through inverter U4 between RTS and the DE, the DE of MAX485 chip and/RE signal and connecing, MAX485 is operated in semiduplex mode.
3. repeated interruptions mode 485 direction-controlling methods according to claim 1 and 2 is characterized in that, B, bus transceiving chip are MAX481 or MAX483 or MAX485 or MAX487 – MAX491, have and independently receive and dispatch the loop.
CN201210372192.XA 2012-09-29 2012-09-29 Repeated interruptions mode 485 direction-controlling method Active CN102882754B (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103268301A (en) * 2013-05-30 2013-08-28 华南理工大学广州学院 Automatic-flowing half-duplex UART interface circuit
CN105446925A (en) * 2015-06-16 2016-03-30 北京天诚盛业科技有限公司 Method and device for improving data receiving correctness of serial port
CN105512061A (en) * 2015-11-24 2016-04-20 北京天诚盛业科技有限公司 UART data receiving and analyzing method and apparatus
CN105721171A (en) * 2016-02-05 2016-06-29 福建师范大学 Low power consumption control method of 485 interface circuit
CN109062847A (en) * 2018-07-31 2018-12-21 深圳职业技术学院 System on chip, IP kernel and its control method for RS485 serial communication

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101122894A (en) * 2006-08-13 2008-02-13 朱金怀 Asynchronous serial communication control device
WO2008134732A1 (en) * 2007-04-30 2008-11-06 Zelmanovich, Victor Packet sniffer for ad hoc network
CN101383819A (en) * 2007-09-05 2009-03-11 迈普(四川)通信技术有限公司 Asynchronous serial data line information transceiving method and asynchronous serial transceiver
CN101986613A (en) * 2010-08-26 2011-03-16 中国航天科技集团公司第九研究院第七七一研究所 All-purpose asynchronous serial communication controller
CN202206412U (en) * 2011-08-23 2012-04-25 万洲电气集团有限公司 Full duplex RS485 bus communication device on basis of collision-free protocol

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101122894A (en) * 2006-08-13 2008-02-13 朱金怀 Asynchronous serial communication control device
WO2008134732A1 (en) * 2007-04-30 2008-11-06 Zelmanovich, Victor Packet sniffer for ad hoc network
CN101383819A (en) * 2007-09-05 2009-03-11 迈普(四川)通信技术有限公司 Asynchronous serial data line information transceiving method and asynchronous serial transceiver
CN101986613A (en) * 2010-08-26 2011-03-16 中国航天科技集团公司第九研究院第七七一研究所 All-purpose asynchronous serial communication controller
CN202206412U (en) * 2011-08-23 2012-04-25 万洲电气集团有限公司 Full duplex RS485 bus communication device on basis of collision-free protocol

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103268301A (en) * 2013-05-30 2013-08-28 华南理工大学广州学院 Automatic-flowing half-duplex UART interface circuit
CN103268301B (en) * 2013-05-30 2016-08-31 华南理工大学广州学院 A kind of half-duplex UART interface circuit of automatic stream
CN105446925A (en) * 2015-06-16 2016-03-30 北京天诚盛业科技有限公司 Method and device for improving data receiving correctness of serial port
CN105512061A (en) * 2015-11-24 2016-04-20 北京天诚盛业科技有限公司 UART data receiving and analyzing method and apparatus
CN105721171A (en) * 2016-02-05 2016-06-29 福建师范大学 Low power consumption control method of 485 interface circuit
CN105721171B (en) * 2016-02-05 2019-04-09 福建师范大学 A kind of Low-power-consumptiocontrol control method of 485 interface circuit
CN109062847A (en) * 2018-07-31 2018-12-21 深圳职业技术学院 System on chip, IP kernel and its control method for RS485 serial communication
CN109062847B (en) * 2018-07-31 2023-08-25 深圳职业技术学院 System on chip, IP core for RS485 serial port communication and control method thereof

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