CN111930676A - Method, device, system and storage medium for communication among multiple processors - Google Patents
Method, device, system and storage medium for communication among multiple processors Download PDFInfo
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- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
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Abstract
The application discloses a communication method, a device, a system and a storage medium among multiple processors, when data to be transmitted which needs to be transmitted to a second processor exists in a first processor, a first control module is used for closing transmission interrupt service; writing a write command into the first command FIFO module, and writing data to be transmitted into the first data FIFO module; the write command and the interrupt notification are sent to the second command FIFO module through a communication channel between the first command FIFO module and the second command FIFO module, the data to be transmitted are sent to the second data FIFO module through the communication channel between the first data FIFO module and the second data FIFO module, after the second control module opens and receives the interrupt service according to the interrupt notification, the second processor reads the data to be transmitted from the second data FIFO module for storage according to the write command, therefore, the inter-core communication can be realized based on hardware, the communication efficiency is high, and the system resource occupation is small.
Description
Technical Field
The present application relates to the field of chip communication technologies, and in particular, to a method, an apparatus, a system, and a storage medium for communication between multiple processors.
Background
To cope with the increasingly rich application scenarios, processor designs are increasingly complex, and it is becoming very common to integrate multiple cores (i.e., processors) on a single fingernail-sized chip. To accomplish system tasks, communication between multiple cores is inevitable, and is an indispensable part of chip design.
At present, a common inter-core communication mainly adopts a mode of sharing a memory and interrupting synchronization, that is, a shared memory specially used for inter-core communication is reserved in advance, and an interrupt mode is adopted to ensure that information among a plurality of cores is synchronized, but the inter-core communication mode needs to develop complex software and follows an RPMSG (remote Processor messaging) protocol or a migration protocol, so that the communication efficiency is not high, the shared memory cannot be used by other programs, and system resources are occupied.
Disclosure of Invention
Embodiments of the present application provide a method, an apparatus, a system, and a storage medium for communication among multiple processors, which can implement inter-core communication based on hardware, do not need to develop complex software and set a shared memory, and have high communication efficiency and a small system resource occupation.
The embodiment of the application provides a communication method among multiple processors, which is applied to a first processor, wherein a first mailbox register is arranged in the first processor, the first mailbox register comprises a first control module, a first command FIFO (first-in first-out) queue module and a first data FIFO module, and the communication method comprises the following steps:
when data to be transmitted which needs to be transmitted to a second processor exists in the first processor, the first control module closes the interrupt service, a second mailbox register is arranged in the second processor, and the second mailbox register comprises a second control module, a second command FIFO module and a second data FIFO module;
after the sending interrupt service is closed, writing a write command into the first command FIFO module, and writing the data to be transmitted into the first data FIFO module;
and the write command and the interrupt notification are sent to the second command FIFO module through a communication channel between the first command FIFO module and the second command FIFO module, and the data to be transmitted are sent to the second data FIFO module through a communication channel between the first data FIFO module and the second data FIFO module, so that after the second control module opens to receive interrupt service according to the interrupt notification, the second processor reads the data to be transmitted from the second data FIFO module for storage according to the write command.
The embodiment of the present application further provides a communication method between multiple processors, which is applied to a second processor, where the second processor is provided with a second mailbox register, the second mailbox register includes a second control module, a second command FIFO module, and a second data FIFO module, and the communication method includes:
when the second command FIFO module receives an interrupt notification sent by a first processor, the second control module opens the interrupt service, and a first mailbox register is arranged in the first processor and comprises a first control module, a first command FIFO module and a first data FIFO module;
after the receiving interrupt service is opened, reading a command currently stored in the second command FIFO module for analysis to obtain an analysis command;
and when the analysis command is a write command, reading the data currently stored in the second data FIFO module to a preset buffer area in the second processor.
The embodiment of the present application further provides a communication device between multiple processors, which is applied to a first processor, wherein a first mailbox register is disposed in the first processor, the first mailbox register includes a first control module, a first command FIFO module, and a first data FIFO module, and the communication device includes:
the closing unit is used for closing the sending interrupt service through the first control module when the first processor has data to be transmitted which needs to be transmitted to the second processor, a second mailbox register is arranged in the second processor, and the second mailbox register comprises a second control module, a second command FIFO module and a second data FIFO module;
a write-in unit, configured to write a write command to the first command FIFO module and write the to-be-transmitted data to the first data FIFO module after the sending interrupt service is closed;
and the sending unit is used for sending the write command and the interrupt notification to the second command FIFO module through a communication channel between the first command FIFO module and the second command FIFO module, and sending the data to be transmitted to the second data FIFO module through a communication channel between the first data FIFO module and the second data FIFO module, so that after the second control module opens to receive interrupt service according to the interrupt notification, the second processor reads the data to be transmitted from the second data FIFO module according to the write command and stores the data.
The embodiment of the present application further provides a communication device between multiple processors, which is applied to a second processor, wherein a second mailbox register is disposed in the second processor, the second mailbox register includes a second control module, a second command FIFO first-in first-out queue module and a second data FIFO module, and the communication device includes:
the opening unit is used for opening and receiving interrupt service through the second control module when the second command FIFO module receives an interrupt notification sent by a first processor, wherein a first mailbox register is arranged in the first processor and comprises a first control module, a first command FIFO module and a first data FIFO module;
the analysis unit is used for reading the currently stored command in the second command FIFO module for analysis after the receiving interrupt service is opened, so as to obtain an analysis command;
and the reading unit is used for reading the data currently stored in the second data FIFO module to a preset buffer area in the second processor when the analysis command is a write command.
The embodiment of the application also provides a communication device among multiple processors, which comprises a first processor and a second processor, wherein the first processor is provided with a first mailbox register, and the second processor is provided with a second mailbox register; the first mailbox register comprises a first control module, a first command FIFO (first in first out) queue module and a first data FIFO module; the second mailbox register includes a second control module, a second command FIFO module, and a second data FIFO module, wherein,
the first processor is to:
when data to be transmitted which needs to be transmitted to the second processor exists, the first control module closes transmission interrupt service; after the sending interrupt service is closed, writing a write command into the first command FIFO module, and writing the data to be transmitted into the first data FIFO module; sending the write command and the interrupt notification to the second command FIFO module through a communication channel between the first command FIFO module and the second command FIFO module, and sending the data to be transmitted to the second data FIFO module through a communication channel between the first data FIFO module and the second data FIFO module;
the second processor is to:
according to the interrupt notification, the second control module is opened to receive interrupt service; after the receiving interrupt service is opened, reading a command currently stored in the second command FIFO module for analysis to obtain an analysis command; and when the analysis command is a write command, reading the data currently stored in the second data FIFO module to a preset buffer area in the second processor.
The embodiment of the application also provides a computer-readable storage medium, wherein a plurality of instructions are stored in the storage medium, and the instructions are suitable for being loaded by a processor to execute the communication method among any one of the multiple processors.
When data to be transmitted to a second processor exists in a first processor, a sending interrupt service is closed through a first control module, then a write command is written into a first command FIFO module, the data to be transmitted is written into a first data FIFO module, then the write command and an interrupt notice are sent to a second command FIFO module through a communication channel between the first command FIFO module and the second command FIFO module, the data to be transmitted is sent to a second data FIFO module through the communication channel between the first data FIFO module and the second data FIFO module, so that after the second control module opens the receiving interrupt service according to the interrupt notice, the second processor reads the data to be transmitted from the second data FIFO module for storage according to the write command, and therefore the inter-core communication can be realized based on hardware, complex software does not need to be developed and a shared memory does not need to be set, the communication efficiency is high, and the system resource occupation is less.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a conventional communication mechanism between multiple processors.
Fig. 2 is a schematic structural diagram of a communication system between multiple processors according to an embodiment of the present application.
Fig. 3 is a flowchart illustrating a communication method between multiple processors according to an embodiment of the present application.
Fig. 4 is a flowchart illustrating another method for communication between multiple processors according to an embodiment of the present disclosure.
Fig. 5 is a flowchart illustrating another method for communication between multiple processors according to an embodiment of the present disclosure.
Fig. 6 is a schematic diagram of a communication mechanism between two processors according to an embodiment of the present application.
Fig. 7 is a software architecture diagram of a communication system between multiple processors according to an embodiment of the present application.
Fig. 8 is a schematic structural diagram of a communication device between multiple processors according to an embodiment of the present application.
Fig. 9 is a schematic structural diagram of another inter-multiprocessor communication apparatus according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," "third," "fourth," and the like (if any) in this application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
For example, referring to fig. 1, the conventional multiprocessor device is configured to divide a shared Memory area in a storage area separately as a data exchange area of each processor, and each processor (for example, processor a and processor B in fig. 1) is connected to the shared Memory area through a communication Interface, such as a Memory Bus (Memory Bus), an SDIO (Secure Digital Input and Output, Secure Digital Input and Output card), an SPI (Peripheral Interface), and an I Interface2C (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver/Transmitter), etc., and simultaneously ensures that information between two processors A, B communicating with each other is synchronous through an interrupt mechanism, the communication mode is realized based on software and needs to develop complex software programs,and the shared memory area can only be used for data exchange between the processors and cannot be used by other application programs.
In the present application, communication between processors is implemented based on hardware + interrupt, mailbox registers are designed in the processors based on a FIFO (First Input First Output) mechanism, so that safe, concise and fast transfer of information can be implemented without separately designing a shared memory area and complex data exchange rules (i.e. without developing complex software programs), specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of a communication system between multiple processors provided in an embodiment of the present application, where the communication system includes multiple processors, such as a Cortex-a76 core, a Cortex-a53 core, a Cortex-R52 processor, a Cortex-a55 processor, a Cortex-M4 processor and a DSP (Digital Signal processing) processor, a mailbox register is provided in each processor, and the mailbox registers are designed based on the FIFO mechanism, any two processors are connected through a mailbox channel through a mailbox register, and data receiving and sending between the two processors are further achieved.
The embodiment of the application provides a method, a device, a system and a storage medium for communication among multiple processors.
The inter-multiprocessor communication method provided by the present application will be described below from the perspective of a single processor (such as a transmit-side processor or a receive-side processor), which may include any one of a Cortex-a76 processor, a Cortex-a53 processor, a Cortex-R52 processor, a Cortex-M4 processor, and a DSP (Digital Signal processing) processor.
Referring to fig. 3, fig. 3 is a schematic flow chart of a communication method between multiple processors according to an embodiment of the present application, where the communication method between multiple processors is applied to a first processor, where the first processor is a sending-end processor and is provided with a first mailbox register, and the first mailbox register includes a first control module, a first command FIFO module, and a first data FIFO module, and a specific flow of the communication method may be as follows:
s101, when data to be transmitted which needs to be transmitted to a second processor exists in the first processor, the first control module closes the transmission interrupt service, a second mailbox register is arranged in the second processor, and the second mailbox register comprises a second control module, a second command FIFO module and a second data FIFO module.
The first control module is a controller and is used for controlling reading and writing of the first command FIFO module and the first data FIFO module and detecting the states of the first command FIFO module and the first data FIFO module, wherein the states can comprise transmission completion or incompletion, reception completion or incompletion and the like, and the second control module has a similar function as the first control module. The first and second command FIFO blocks may be an FIFO structure of 8 Word words (equivalent to 32 bytes, one Word =4 bytes) for creating write commands and commands indicating channel connection (such as open commands and close commands), and the first and second data FIFO blocks may be an FIFO structure of 128 Word words (equivalent to 512 bytes).
S102, writing a write command into the first command FIFO module, and writing the data to be transmitted into the first data FIFO module.
Wherein the first controller may cause the specified parameter to become 0 (equivalent to pulling low) to turn off the send interrupt service, at which time the first command FIFO may be filled with 8 Word commands and the first data FIFO may be filled with 128 Word data at most a single time. Before the sending of the interrupt service is turned off, the first command FIFO block and the first data FIFO block need to be emptied (if the sending is for the first time, the first command FIFO block and the first data FIFO block do not need to be emptied), that is, the communication method further includes:
detecting whether the first data FIFO module and the first command FIFO module have data which are not sent completely;
if so, the data in the first data FIFO module and the first command FIFO module are emptied.
S103, sending the write command and the interrupt notification to the second command FIFO module through a communication channel between the first command FIFO module and the second command FIFO module, and sending the data to be transmitted to the second data FIFO module through a communication channel between the first data FIFO module and the second data FIFO module, so that after the second control module opens to receive interrupt service according to the interrupt notification, the second processor reads the data to be transmitted from the second data FIFO module for storage according to the write command.
Before sending, the controller needs to detect whether data in the first data FIFO module is completely written, if not, continue writing, and if so, open the sending interrupt service, for example, change the specified parameter to 1 (equivalent to pull-up) to trigger the interrupt service, and then send data and commands to other processors through the mailbox channel, and need to notify the other processors through the interrupt. The interrupt notification is generated according to a trigger condition preset by another server, for example, the trigger condition may be a non-empty command, or 2 consecutive commands, and the second controller of the other processor may detect whether the second command FIFO module receives the interrupt notification, for example, whether the non-empty command is received, and if so, turn on to receive the interrupt service.
In addition, the Command and the data are generally packed into a data packet according to a set communication protocol format, and then sent to other processors, for example, please refer to the following table, the communication protocol may relate to contents of a plurality of fields, such as a Synchronization Word (Synchronization Word), a Command Word (Command Word), a Length (Length), data, a Check code (Cyclic Redundancy Check, CRC), and the like, wherein the Synchronization Word field is used to indicate a start character position of the data packet, such as 0x55AA, the Command Word field is used to indicate a classification of an application function, the Length field is used to indicate a number of characters (i.e., a data size), the data field generally stores application data, and the Check code is used to perform integrity Check.
| Byte(s) | Field(s) | Definition of |
| 0 | Synchronous word | Start character position of data packet |
| 1 | Command word | Classification of application functions |
| 2 | Length of | Data size |
| 3…3+n-1 | Data [ 1 … n ] | Application data |
| 3+n | Check code | CRC data |
It should be noted that, to improve the security of data transmission, the mailbox register may further encrypt the data before transmitting the data, for example, the step "sending the data to be transmitted to the second data FIFO module through the communication channel between the first data FIFO module and the second data FIFO module" may include:
acquiring a first identifier of the first processor and a second identifier of the second processor;
encrypting the data to be transmitted in the first data FIFO module according to the first identifier and the second identifier to obtain encrypted data;
the encrypted data is transmitted to the second data FIFO module through a communication channel between the first data FIFO module and the second data FIFO module.
Specifically, the step of encrypting the data to be transmitted in the first data FIFO module according to the first identifier and the second identifier may include:
performing exclusive or on the first identifier and the second identifier to obtain first data;
carrying out XOR on the first data and the data to be transmitted to obtain second data;
and circularly moving each character in the second data by a preset bit along a preset direction to obtain encrypted data.
The processor identifier, i.e., core ID, is used to uniquely identify the processor. The encryption method is preset, and may be implemented based on a hardware circuit, such as setting a nand gate circuit to implement xor processing, or may be implemented by pure software code. The predetermined direction may be a left shift or a right shift, such as a left shift of 4 bits, such that in the second data, starting from the tail character, each character is sequentially shifted forward by four bits, the first character is shifted to the fourth last of the tail, and the second character is shifted to the third last of the tail. The encryption is carried out by the aid of the identifiers of the sending end and the receiving end, so that the encryption can be carried out without setting keys in the receiving end and the sending end, and the method is simple.
In addition, before transmitting data and commands to the second processor, it is required to ensure that the channel between the first mailbox register and the second mailbox register is open, that is, before the step S103, the communication method further includes:
writing an open command indicating a channel connection in the first command FIFO block;
according to the open command, a communication channel is opened between the first data FIFO module and the second data FIFO module, and a communication channel is opened between the first command FIFO module and the second command FIFO module.
As can be seen from the above, in the communication method between multiple processors provided in the present application, when there is data to be transmitted that needs to be transmitted to a second processor in a first processor, a first control module closes a transmission interrupt service, after the transmission interrupt service is closed, a write command is written to a first command FIFO module, and data to be transmitted is written to a first data FIFO module, then a write command and an interrupt notification are sent to a second command FIFO module through a communication channel between the first command FIFO module and the second command FIFO module, and the data to be transmitted is sent to the second data FIFO module through the communication channel between the first data FIFO module and the second data FIFO module, so that after a second control module opens to receive the interrupt service according to the interrupt notification, the second processor reads the data to be transmitted from the second data FIFO module according to the write command for storage, therefore, the inter-core communication can be realized based on hardware, complex software does not need to be developed, a shared memory does not need to be set, the communication efficiency is high, and the system resource occupation is less.
Referring to fig. 4, fig. 4 is another flowchart illustrating a communication method between multiple processors according to an embodiment of the present application, where the communication method between multiple processors is applied to a second processor, the second processor is a receiver processor, the second processor is provided with a second mailbox register, the second mailbox register includes a second control module, a second command FIFO module, and a second data FIFO module, and the communication method includes:
s201, when the second command FIFO module receives an interrupt notification sent by the first processor, the second control module opens the interrupt service, and a first mailbox register is arranged in the first processor and comprises a first control module, a first command FIFO module and a first data FIFO module.
When the interrupt notification shows a non-empty command, the second control module may detect whether the non-empty command is received in the second command module, and if so, determine that the interrupt notification is received. Before the receiving interrupt service is opened, whether the data in the second data FIFO module is received completely can be detected, if not, the receiving is continued, and if so, the receiving interrupt service can be triggered.
And S202, after the receiving interrupt service is opened, reading the currently stored command in the second command FIFO module for analysis to obtain an analysis command.
The parsing operation mainly refers to restoring the packed data, and can be performed according to the contents of fields such as a synchronization word, a command word, a length and the like.
S203, when the analysis command is a write command, reading the currently stored data in the second data FIFO module to a preset buffer area in the second processor.
Wherein, except for recovering the packed data, if the received data is encrypted data, the method further involves a decryption operation, and at this time, the step of "reading the data currently stored in the second data FIFO module to a preset buffer area in the second processor" specifically includes:
reading the data currently stored in the second data FIFO module, and acquiring a first identifier of the first processor and a second identifier of the second processor;
decrypting the read data according to the first identifier and the second identifier to obtain decrypted data;
determining a target storage address from a preset cache region in the second processor according to the length of the decrypted data;
and putting the decrypted data into an area corresponding to the target storage address.
The decryption method is similar to the encryption method, for example, the encryption data is circularly moved by a preset bit in a direction (for example, right shift) opposite to the preset direction, the identifier of the first processor and the identifier of the second processor are subjected to exclusive-or, and then the results of the first processor and the second processor are subjected to exclusive-or to obtain the original plaintext data. Before the plaintext data is stored in the preset buffer area, a space as large as the plaintext data needs to be applied to the preset buffer area for storage.
In addition, in addition to data communication between processors, data communication also exists between processors and application programs, so that application data can be written into the processors, or data can be read from the processors to the application programs, and the data communication can be realized by designing a simple and efficient programming interface between the processors, such as a write-write interface, a read interface, an input/output control (ioctl) interface and the like, so that the software complexity is simplified.
When the processor communicates data with the application program, the interface transmission mode is also involved, such as a blocking mode and a non-blocking mode. For example, the communication method further includes:
acquiring a reading instruction sent by a target application, wherein the reading instruction carries the length of target data;
determining a current interface transmission mode according to the application reading instruction;
if the current interface transmission mode is a blocking mode, acquiring a preset transmission attribute parameter, determining target data in the preset cache region according to the transmission attribute parameter, and transmitting the target data to the target application through the reading interface;
if the current interface transmission mode is a non-blocking mode, the data with the length equal to the target data length is read from the preset cache area by using the reading interface and transmitted to the target application.
The transmission attribute parameters may include a minimum received byte number (Bcount) and a waiting time (Wtime), which may be set in the mailbox CMD file. When the data is in the blocking mode, if Bcount =0 and Wtime =5, waiting for 5 seconds for timeout, and returning all current data in the preset buffer area to the application program by the read function. If the mode is non-blocking, the read function immediately returns all the data requested by the read instruction.
In addition, when the second processor is a Cortex-R52 core, in view of its important role in functional security, an ECC encoder/decoder may be further provided, which decodes an error correction code using data read from a mailbox register, and performs error detection and correction using a singing error correction double error detection (SECDED, hamming check code algorithm) algorithm, thereby ensuring the security and integrity of communication data.
Referring to fig. 5, an embodiment of the present application further provides a communication system between multiple processors, including a first processor and a second processor, where the first processor is provided with a first mailbox register, and the second processor is provided with a second mailbox register; the first mailbox register comprises a first control module, a first command FIFO module and a first data FIFO module; the second mailbox register includes a second control module, a second command FIFO module, and a second data FIFO module, wherein,
the first processor is configured to:
s301, when data to be transmitted which needs to be transmitted to the second processor exists, the first control module closes transmission interrupt service;
s302, after the sending interrupt service is closed, writing a write command into the first command FIFO module, and writing the data to be transmitted into the first data FIFO module;
s303, sending the write command and the interrupt notification to the second command FIFO module through a communication channel between the first command FIFO module and the second command FIFO module, and sending the data to be transmitted to the second data FIFO module through a communication channel between the first data FIFO module and the second data FIFO module;
the second processor is configured to:
s304, according to the interrupt notice, the second control module opens and receives the interrupt service;
s305, after the receiving interrupt service is opened, reading the currently stored command in the second command FIFO module for analysis to obtain an analysis command;
s306, when the parsing command is a write command, reading the currently stored data in the second data FIFO module to a preset buffer area in the second processor.
Specifically, referring to fig. 6, the first processor may be Cortex-a76, the second processor may be Cortex-M4, and they are all provided with corresponding mailbox registers, and only various commands are transmitted between the command FIFO modules in each mailbox register, only various data are transmitted between the data FIFO modules, and the control module controls the writing and reading of the data FIFO modules and the command FIFO modules, and detects the states thereof.
It should be noted that, in the communication system between multiple processors, the mailbox register in each processor is set by way of logical mapping, and actually, physically, the communication system may provide 4 large FIFO modules, which are respectively used as a command FIFO module and a data FIFO module for reception, and a command FIFO module and a data FIFO module for transmission. For each FIFO module for reception or transmission, a plurality of small FIFO modules can be divided and mapped into processors to set corresponding small FIFO modules in the processors, which corresponds to a plurality of processors in a communication system dividing 4 large FIFO modules. Generally, since each processor can be a sending-end processor or a receiving-end processor, a single processor is provided with 4 small FIFO modules for processing data and commands related to the processor, and specifically, the single processor can include a sending command FIFO module, a receiving command FIFO module, a sending data FIFO module and a receiving data FIFO module.
It should be noted that, in the above embodiment, when describing the data communication process between the first processor and the second processor, only 2 small FIFO modules in each processor are selected, that is, the command FIFO module and the data FIFO module for transmission in the first processor are selected, and the command FIFO module and the data FIFO module for reception in the second processor are selected for description.
Referring to fig. 7, the software architecture of the communication system is divided into six layers, which are, from bottom to top, a Hardware Layer, a driver Layer, a HAL (hard Abstraction Layer), a protocol Layer, an adapter Layer, and an application Layer. The architecture supports three systems, Linux, Android, and FreeRtos. To support Android applications, the adapter layer provides JNI (Java Native Interface).
The above embodiments can be referred to as the foregoing embodiments, and detailed description thereof is omitted.
According to the method described in the above embodiments, the following description will be further made from the perspective of an inter-multiprocessor communication apparatus, which may be specifically implemented as a standalone entity or integrated in an electronic device, such as a smart phone, a personal computer, or the like.
Referring to fig. 8, fig. 8 specifically illustrates a communication device between multiple processors according to an embodiment of the present application, which is applied to a first processor, where the first processor is provided with a first mailbox register, and the first mailbox register includes a first control module, a first command FIFO module, and a first data FIFO module, and the communication device includes: a closing unit 10, a writing unit 20 and a sending unit 30, wherein:
(1) closing unit 10
A closing unit 10, configured to close, when there is data to be transmitted that needs to be transmitted to a second processor in the first processor, the sending interrupt service through the first control module, where a second mailbox register is arranged in the second processor, and the second mailbox register includes a second control module, a second command FIFO module, and a second data FIFO module.
(2) Write unit 20
A write unit 20, configured to write a write command to the first command FIFO module and write the data to be transmitted to the first data FIFO module after the sending interrupt service is turned off.
(3) Transmitting unit 30
A sending unit 30, configured to send the write command and the interrupt notification to the second command FIFO module through a communication channel between the first command FIFO module and the second command FIFO module, and send the data to be transmitted to the second data FIFO module through a communication channel between the first data FIFO module and the second data FIFO module, so that after the second control module opens the interrupt service according to the interrupt notification, the second processor reads the data to be transmitted from the second data FIFO module according to the write command and stores the data.
Further, the sending unit 30 is configured to:
acquiring a first identifier of the first processor and a second identifier of the second processor;
encrypting the data to be transmitted in the first data FIFO module according to the first identifier and the second identifier to obtain encrypted data;
the encrypted data is transmitted to the second data FIFO module through a communication channel between the first data FIFO module and the second data FIFO module.
Further, performing exclusive or on the first identifier and the second identifier to obtain first data;
carrying out XOR on the first data and the data to be transmitted to obtain second data;
and circularly moving each character in the second data by a preset bit along a preset direction to obtain encrypted data.
Wherein, the communication device further comprises a connection module for:
writing an open command indicating a channel connection in the first command FIFO block;
according to the connect command, a communication channel is opened between the first data FIFO module and the second data FIFO module, and a communication channel is opened between the first command FIFO module and the second command FIFO module.
Referring to fig. 9, fig. 9 specifically describes the communication device between multiple processors according to the embodiment of the present application, which is applied to a second processor, where the second processor is a receiving-end processor, and a second mailbox register is disposed in the second processor, where the second mailbox register includes a second control module, a second command FIFO module, and a second data FIFO module, and the communication device includes an opening unit 40, a parsing unit 50, and a reading unit 60, where:
(4) opening unit 40
And the opening unit 40 is configured to open, by the second control module, an interrupt service when the second command FIFO module receives an interrupt notification sent by the first processor, where the first processor is provided with a first mailbox register, and the first mailbox register includes a first control module, a first command FIFO module, and a first data FIFO module.
(5) Analyzing unit 50
The parsing unit 50 is configured to read a currently stored command in the second command FIFO module for parsing after the receiving interrupt service is opened, so as to obtain a parsing command;
(6) reading unit 60
And a reading unit 60, configured to read, when the parse command is a write command, data currently stored in the second data FIFO module to a preset buffer area in the second processor.
The reading unit 60 is specifically configured to:
reading the data currently stored in the second data FIFO module, and acquiring a first identifier of the first processor and a second identifier of the second processor;
decrypting the read data according to the first identifier and the second identifier to obtain decrypted data;
determining a target storage address from a preset cache region in the second processor according to the length of the decrypted data;
and putting the decrypted data into an area corresponding to the target storage address.
Wherein the communication device further comprises a transmission unit configured to:
acquiring a reading instruction sent by a target application, wherein the reading instruction carries the length of target data;
determining a current interface transmission mode according to the application reading instruction;
if the current interface transmission mode is a blocking mode, acquiring a preset transmission attribute parameter, determining target data in the preset cache region according to the transmission attribute parameter, and transmitting the target data to the target application through the reading interface;
if the current interface transmission mode is a non-blocking mode, the data with the length equal to the target data length is read from the preset cache area by using the reading interface and transmitted to the target application.
In a specific implementation, the above units may be implemented as independent entities, or may be combined arbitrarily to be implemented as the same or several entities, and the specific implementation of the above units may refer to the foregoing method embodiments, which are not described herein again.
It will be understood by those skilled in the art that all or part of the steps of the methods of the above embodiments may be performed by instructions or by instructions controlling associated hardware, and the instructions may be stored in a computer readable storage medium and loaded and executed by the first processor or the second processor. To this end, the embodiment of the present invention provides a storage medium, in which a plurality of instructions are stored, and the instructions can be loaded by the first processor or the second processor to execute the steps in any one of the methods for communication between multiple processors provided by the embodiment of the present invention.
Wherein the storage medium may include: read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and the like.
Since the instructions stored in the storage medium may execute the steps in any one of the methods for communicating among multiple processors provided by the embodiments of the present invention, the advantageous effects that can be achieved by any one of the methods for communicating among multiple processors provided by the embodiments of the present invention may be achieved, which are detailed in the foregoing embodiments and will not be described herein again.
In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be determined by the appended claims.
Claims (12)
1. A communication method between multiple processors is applied to a first processor, and is characterized in that a first mailbox register is arranged in the first processor and comprises a first control module, a first command FIFO (first-in first-out) queue module and a first data FIFO module, and the communication method comprises the following steps:
when data to be transmitted which needs to be transmitted to a second processor exists in the first processor, the first control module closes the interrupt service, a second mailbox register is arranged in the second processor, and the second mailbox register comprises a second control module, a second command FIFO module and a second data FIFO module;
after the sending interrupt service is closed, writing a write command into the first command FIFO module, and writing the data to be transmitted into the first data FIFO module;
and the write command and the interrupt notification are sent to the second command FIFO module through a communication channel between the first command FIFO module and the second command FIFO module, and the data to be transmitted are sent to the second data FIFO module through a communication channel between the first data FIFO module and the second data FIFO module, so that after the second control module opens to receive interrupt service according to the interrupt notification, the second processor reads the data to be transmitted from the second data FIFO module for storage according to the write command.
2. The inter-multiprocessor communication method according to claim 1, wherein the sending the data to be transmitted to the second data FIFO module through a communication channel between the first data FIFO module and the second data FIFO module comprises:
acquiring a first identifier of the first processor and a second identifier of the second processor;
encrypting the data to be transmitted in the first data FIFO module according to the first identifier and the second identifier to obtain encrypted data;
transmitting the encrypted data to the second data FIFO module via a communication channel between the first data FIFO module and the second data FIFO module.
3. The inter-multiprocessor communication method according to claim 2, wherein the encrypting the data to be transmitted in the first data FIFO module according to the first identifier and the second identifier comprises:
performing exclusive or on the first identifier and the second identifier to obtain first data;
performing exclusive or on the first data and the data to be transmitted to obtain second data;
and circularly moving each character in the second data by a preset bit along a preset direction to obtain encrypted data.
4. The inter-multiprocessor communication method according to claim 1, further comprising, before the sending interrupt service is turned off by the first control module:
detecting whether the first data FIFO module and the first command FIFO module have data which are not sent completely;
and if so, emptying the data in the first data FIFO module and the first command FIFO module.
5. The inter-multiprocessor communication method according to claim 1, further comprising:
writing an open command indicating a channel connection in the first command FIFO module;
according to the opening command, communicating a communication channel between the first data FIFO module and the second data FIFO module, and communicating a communication channel between the first command FIFO module and the second command FIFO module.
6. A communication method between multiple processors is applied to a second processor, and is characterized in that a second mailbox register is arranged in the second processor and comprises a second control module, a second command FIFO module and a second data FIFO module, and the communication method comprises the following steps:
when the second command FIFO module receives an interrupt notification sent by a first processor, the second control module opens the interrupt service, and a first mailbox register is arranged in the first processor and comprises a first control module, a first command FIFO module and a first data FIFO module;
after the receiving interrupt service is opened, reading a command currently stored in the second command FIFO module for analysis to obtain an analysis command;
and when the analysis command is a write command, reading the data currently stored in the second data FIFO module to a preset buffer area in the second processor.
7. The inter-multiprocessor communication method according to claim 6, wherein a read interface is further provided in the second processor, and further comprising:
acquiring a reading instruction sent by a target application, wherein the reading instruction carries a target data length;
determining a current interface transmission mode according to the application reading instruction;
if the current interface transmission mode is a blocking mode, acquiring a preset transmission attribute parameter; determining target data in the preset cache region according to the transmission attribute parameters, and transmitting the target data to the target application through the reading interface;
and if the current interface transmission mode is a non-blocking mode, reading data with the length equal to the target data length from the preset cache region by using the reading interface and transmitting the data to the target application.
8. The inter-multiprocessor communication method according to claim 6, wherein the reading the currently stored data in the second data FIFO module to a predetermined buffer in the second processor comprises:
reading currently stored data in the second data FIFO module, and acquiring a first identifier of the first processor and a second identifier of the second processor;
decrypting the read data according to the first identification and the second identification to obtain decrypted data;
determining a target storage address from a preset cache region in the second processor according to the length of the decrypted data;
and putting the decrypted data into an area corresponding to the target storage address.
9. A communication device between multiple processors is applied to a first processor, and is characterized in that a first mailbox register is arranged in the first processor, the first mailbox register comprises a first control module, a first command FIFO module and a first data FIFO module, and the communication device comprises:
the closing unit is used for closing the sending interrupt service through the first control module when the first processor has data to be transmitted which needs to be transmitted to the second processor, a second mailbox register is arranged in the second processor, and the second mailbox register comprises a second control module, a second command FIFO module and a second data FIFO module;
a write-in unit, configured to write a write command to the first command FIFO module and write the to-be-transmitted data to the first data FIFO module after the sending interrupt service is closed;
and the sending unit is used for sending the write command and the interrupt notification to the second command FIFO module through a communication channel between the first command FIFO module and the second command FIFO module, and sending the data to be transmitted to the second data FIFO module through a communication channel between the first data FIFO module and the second data FIFO module, so that after the second control module opens to receive interrupt service according to the interrupt notification, the second processor reads the data to be transmitted from the second data FIFO module according to the write command and stores the data.
10. A communication device between multiple processors is applied to a second processor, and is characterized in that a second mailbox register is arranged in the second processor and comprises a second control module, a second command FIFO (first-in first-out) queue module and a second data FIFO module, and the communication device comprises:
the opening unit is used for opening and receiving interrupt service through the second control module when the second command FIFO module receives an interrupt notification sent by a first processor, wherein a first mailbox register is arranged in the first processor and comprises a first control module, a first command FIFO module and a first data FIFO module;
the analysis unit is used for reading the currently stored command in the second command FIFO module for analysis after the receiving interrupt service is opened, so as to obtain an analysis command;
and the reading unit is used for reading the data currently stored in the second data FIFO module to a preset buffer area in the second processor when the analysis command is a write command.
11. A communication system among multiple processors is characterized by comprising a first processor and a second processor, wherein a first mailbox register is arranged in the first processor, and a second mailbox register is arranged in the second processor; the first mailbox register comprises a first control module, a first command FIFO (first in first out) queue module and a first data FIFO module; the second mailbox register includes a second control module, a second command FIFO module, and a second data FIFO module, wherein,
the first processor is to:
when data to be transmitted which needs to be transmitted to the second processor exists, the first control module closes transmission interrupt service; after the sending interrupt service is closed, writing a write command into the first command FIFO module, and writing the data to be transmitted into the first data FIFO module; sending the write command and the interrupt notification to the second command FIFO module through a communication channel between the first command FIFO module and the second command FIFO module, and sending the data to be transmitted to the second data FIFO module through a communication channel between the first data FIFO module and the second data FIFO module;
the second processor is to:
according to the interrupt notification, the second control module is opened to receive interrupt service; after the receiving interrupt service is opened, reading a command currently stored in the second command FIFO module for analysis to obtain an analysis command; and when the analysis command is a write command, reading the data currently stored in the second data FIFO module to a preset buffer area in the second processor.
12. A computer-readable storage medium, characterized in that a plurality of instructions are stored in said storage medium, said instructions being adapted to be loaded by a first processor for performing the inter-multiprocessor communication method according to any one of claims 1 to 5, or adapted to be loaded by a second processor for performing the inter-multiprocessor communication method according to any one of claims 6 to 8.
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