CN101894005A

CN101894005A - Asynchronous FIFO transmission method from high-speed interfaces to low-speed interfaces

Info

Publication number: CN101894005A
Application number: CN2010101857220A
Authority: CN
Inventors: 张俊杰; 袁文燕; 宋建港; 田进进; 施君浩
Original assignee: University of Shanghai for Science and Technology
Current assignee: University of Shanghai for Science and Technology
Priority date: 2010-05-26
Filing date: 2010-05-26
Publication date: 2010-11-24

Abstract

The invention discloses an asynchronous FIFO transmission method from high-speed interfaces to low-speed interfaces, comprising the following steps: 1. when data frames pass through a write control module, the write control module adds identification bits for each data unit and sets the identification bit of the second last data unit as a specific value (identification code of end of frame) different from the identification bits of the rest data units to show end of frame; 2. when the write control module detects that data FIFO is not full, W_ena is valid and the write control module writes the data frames with identification bits added into data FIFO; and 3. when a read control module detects that data FIFO is not empty, R_ena is valid and the read control module begins reading data and judging the identification bits of the data units, and when the identification bits are the identification codes of end of frame, R_ena is invalid and transmission of whole frame data is completed at the moment. The method can realize transmission of variable length frames, complete transmission of the data frames with only fewer identification bits, effectively increase the data transmission rate and adopt the method of reloading addresses for the data which can not be completely transmitted, thus ensuring the accuracy of data transmission.

Description

The asynchronous FIFO transmission method of high-speed interfaces to low-speed interfaces

Technical field

The present invention relates to a kind of FIFO transmission method, particularly a kind of asynchronous FIFO transmission method of high-speed interfaces to low-speed interfaces.

Background technology

In the communications field because fifo queue FIFO visit is simple, and do not need a large amount of decoding schemes, therefore be used widely in electronic system, be usually used in comprising high-speed data acquisition, multiprocessor interface and communicate by letter in various fields such as speed buffering.FIFO is usually used in transmitting bursty datas such as ether data, and when being used for the transmitting burst data, Frame is generally elongated frame, prior art is realizing on the elongated data transmission, if adopt the double-FIFO form to realize that hardware cost is high relatively, the present invention adopts single FIFO method to realize the transmission of elongated frame.

Summary of the invention

The objective of the invention is to defective at the prior art existence, a kind of high-speed interfaces to low-speed interfaces asynchronous FIFO transmission method is provided, increased the end of discrimination bit with the judgment data frame, realized of the transmission of elongated data from high-speed interfaces to low-speed interfaces, simultaneously to data that can not complete transmission, the reload method of address of employing has guaranteed the accuracy of data transmission.

For achieving the above object, the present invention adopts following technical proposals: a kind of asynchronous FIFO transmission method of high-speed interfaces to low-speed interfaces, its operation steps is: when (1) Frame process is write control module, the described control module of writing increases discrimination bit for each data unit, the discrimination bit of penult data unit is set to a certain particular value---the frame end identification code different with the discrimination bit of remainder data unit, with the expression frame end; (2) writing control module, to detect data FIFO non-when full, writes to enable effectively, and the described Frame of writing control module and will increasing behind the discrimination bit writes data FIFO; When (3) reading control module and detect the data FIFO non-NULL, read to enable effectively, describedly read the discrimination bit that control module begins reading of data and judgment data unit, when discrimination bit was the frame end identification code, it was invalid to read to enable, and whole frame data read and finished this moment.

Step (1) is before: the filtering of frame length filtering module is less than the data of 2 data units.

In the step (2): superimpose data FIFO writes when full, whole Frame is not also finished transmission, then write enable invalid, be changed to the signal of reloading effectively this moment, write and enable invalidly to continue to whole data frame transfer and finish, write the end position that end return to previous frame data of signal of reloading data FIFO.

The present invention compared with prior art, have following outstanding substantive distinguishing features and remarkable advantage: the present invention is owing to for Frame has increased discrimination bit with the identification frame end, therefore transmit any elongated data of length greater than 1 data unit in the scope that can allow at the degree of depth and the width of FIFO.The present invention can realize the transmission of elongated frame, and only finishes the transmission of data with less discrimination bit, effectively improves message transmission rate, and simultaneously to data that can not complete transmission, the reload method of address of employing has guaranteed the accuracy of data transmission.

Description of drawings

Fig. 1 is the realization block diagram of transmission method of the present invention.

Fig. 2 is the high-speed data of the present invention when not increasing discrimination bit.

Fig. 3 is the high-speed data after the present invention increases discrimination bit.

Fig. 4 is the sequential chart that the embodiment of the invention process of reloading realizes.

Embodiment

Referring to Fig. 1, the method for the invention is summarized as follows: the preferred embodiments of the present invention accompanying drawings is as follows: the operation steps of the asynchronous FIFO transmission method of high-speed interfaces to low-speed interfaces is as follows:

High-speed data process frame length filtering module at first filters out the data less than 2 data units;

The high-speed data of process frame length filtering module enters writes control module.When the Frame process is write control module, writing control module increases discrimination bit for each data unit, the discrimination bit of penult data unit is set to a certain particular value---the frame end identification code different with the discrimination bit of remainder data unit, with the expression frame end;

When writing control module and detecting data FIFO non-full (Not_full), write enable (W_ena) effective, the Frame that writing control module will increase behind the discrimination bit writes data FIFO; Superimpose data FIFO writes when full, whole Frame does not also transmit to be finished, then write enable (W_ena) invalid, be changed to (Reload) signal of reloading effectively this moment, write and enable invalidly to continue to whole data frame transfer and finish, write the end position that end return to previous frame data of (Reload) signal of reloading data FIFO;

When reading control module and detecting data FIFO non-NULL (Not_empty), it is effective to read to enable (R_ena), reads the discrimination bit that control module begins reading of data and judgment data unit, when discrimination bit is the frame end identification code, it is invalid to read to enable (R_ena), and whole frame data read and finished this moment.

Be described in further detail below:

High-speed data process frame length filtering module at first filters out the data less than 2 data units.The data of filtering through the frame length filtering module with data unit by a byte, to be passed Frame be that a N data unit is an example, as shown in Figure 2, passing through the data of filtering is that frame length is the data of N byte.

As shown in Figure 3, this Frame is when writing control module, and writing control module increases a discrimination bit after each byte, i.e. as shown in Figure 3 the 8th.Put the penult data unit promptly the discrimination bit of (N-1) individual byte be frame end identification code 1, put get final product different of discrimination bit of all the other each bytes, because only established a discrimination bit among this embodiment, so the value different with 1 can only be 0 with 1.

Writing control module, to have data to write fashionable, if when detecting data FIFO non-full (Not_full), write enable (W_ena) effective, the Frame that writing control module will increase behind the discrimination bit writes data FIFO.

As shown in Figure 4, when FIFO writes data, if constantly to t1, when writing Frame and only having write 0,1,2 these preceding 3 bytes, data FIFO has been write full, promptly non-full (Not_full) invalidating signal, then write enable (W_ena) invalid, be changed to (Reload) signal of reloading effectively this moment, writes to enable invalidly to continue to whole data frame transfer and finish, and (Reload) signal of reloading is held the end position that returns to the previous frame data with writing of data FIFO.To t2 constantly, when the next frame data need be transmitted, non-full (Not_full) signal was effective, and promptly FIFO is non-full, write enable (W_ena) effective, write control module and continue data are write data FIFO according to the position of (Reload) signal indication of reloading.

When reading control module and detecting data FIFO non-NULL (Not_empty), it is effective to read to enable (R_ena), read the discrimination bit that control module begins reading of data and judgment data unit, when reading discrimination bit and be frame end identification code 1, it is invalid to read to enable (R_ena), and whole frame data read and finished this moment.Whole data transmission procedure is finished.

Though the present invention discloses as above with embodiment; so it is not in order to limit scope of the present invention; those skilled in the art can do various changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.

Claims

1. the asynchronous FIFO transmission method of a high-speed interfaces to low-speed interfaces is characterized in that operation steps is as follows:

When (1) the Frame process is write control module, the described control module of writing increases discrimination bit for each data unit, the discrimination bit of penult data unit is set to a certain particular value---the frame end identification code different with the discrimination bit of remainder data unit, with the expression frame end;

(2) writing control module, to detect data FIFO non-when full, writes to enable effectively, and the described Frame of writing control module and will increasing behind the discrimination bit writes data FIFO;

When (3) reading control module and detect the data FIFO non-NULL, read to enable effectively, describedly read the discrimination bit that control module begins reading of data and judgment data unit, when discrimination bit was the frame end identification code, it was invalid to read to enable, and whole frame data read and finished this moment.

2. high-speed interfaces to low-speed interfaces asynchronous FIFO transmission method according to claim 1 is characterized in that described step (1) before:

The filtering of frame length filtering module is less than the data of 2 data units.

3. high-speed interfaces to low-speed interfaces asynchronous FIFO transmission method according to claim 1, it is characterized in that in the described step (2): superimpose data FIFO writes when full, whole Frame is not also finished transmission, then write enable invalid, be changed to the signal of reloading effectively this moment, write and enable invalidly to continue to whole data frame transfer and finish, write the end position that end return to previous frame data of signal of reloading data FIFO.