CN109308180A - The processing method and processing unit of cache congestion - Google Patents
The processing method and processing unit of cache congestion Download PDFInfo
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- CN109308180A CN109308180A CN201810937015.9A CN201810937015A CN109308180A CN 109308180 A CN109308180 A CN 109308180A CN 201810937015 A CN201810937015 A CN 201810937015A CN 109308180 A CN109308180 A CN 109308180A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
Abstract
The present invention provides the processing method and processing unit of a kind of cache congestion, which comprises corresponding data memory creates a data mode FIFO memory and multi-channel data abandons flag register；The data mode FIFO memory for storing data in memory storing data address, the corresponding channel number of data channel and the corresponding pressure of data channel terminate bit identification；In any clock cycle, when there are when read request and/or write request for any data, the at least one of current storage status of flag register is abandoned according to data storage, data mode FIFO memory and multi-channel data, judges that can current data be read to be forwarded and/or enter data storage by current data channel to leave active data storage and is cached.The present invention, to reduce the depth of data storage, reduces memory resource, promotes the effective rate of utilization of data storage by introducing depth and the asymmetric data mode FIFO memory of data storage.
Description
Technical field
The present invention relates to network communication field more particularly to the processing methods and processing unit of a kind of cache congestion.
Background technique
Data transmission and processing is that digital circuit commonly designs, wherein the packet interval of multichannel from high bandwidth interface
Low-bandwidth interfaces are sent to, and do not have under the scene of flow control to high bandwidth interface, it usually needs a data storage delays
The data packet of input is deposited, but under the premise of data persistently input, data storage can accumulate full data quickly and overflow；However number
It is that there is no Overflow handlings according to memory, in this way, needing to generate the data knot for forcing to terminate in the full data of data storage product
Beam character, to indicate the data packet end of transmission in current data channel, although the partial data in the channel has been written into data
Memory, but the follow-up data needs in this channel are dropped processing.
In the prior art, as shown in Figure 1, buffer in congestion processing framework, it is assumed that design requirement to solve the above-mentioned problems
The minimum-depth of middle data storage is N, and the data channel quantity of data input is M, then data storage in final design
Actual depth is N+M, reserves an address wherein there is M address space to be for each input channel.When data storage uses
Most N number of effective addresses carry out designation date memory and have accumulated full, can not receive input again it is necessary to generating full marking signal
Data to data storage is deposited, while the end of data that one pressure of write-in terminates in the data space that data storage is reserved
Memory will not be written with the data for reminding the channel to input, until the data end-of-packet in character again.However, since data are deposited
Memory resource is of great value, if it is each channel reserve a storage address, in the more situation in channel, can waste compared with
More address spaces.
Summary of the invention
In order to solve the above technical problems, the purpose of the present invention is to provide a kind of processing method and processing devices of cache congestion.
One of in order to achieve the above-mentioned object of the invention, an embodiment of the present invention provides a kind of processing method of cache congestion,
The described method includes: corresponding data memory creates a data mode FIFO memory and multi-channel data abandons mark deposit
Device；
The data storage is to store the data inputted by data channel, depth N；The data channel
Quantity is M；The data mode FIFO memory for storing data in memory storing data address, data channel is corresponding
Channel number and the corresponding pressure of data channel terminate bit identification, the minimum N+M of depth, the discarding flag register
Discarding for storing corresponding any data channel identifies, and minimum widith M, described M, N are the positive integer greater than 1；
In any clock cycle, when any data is there are when read request and/or write request, according to data storage, data
State FIFO memory and multi-channel data abandon at least one of current storage status of flag register, and judgement is current
Can data be read to leave active data storage and be forwarded and/or enter data storage by current data channel
It is cached.
As the further improvement of an embodiment of the present invention, " in any clock cycle, when there are read requests for any data
And/or when write request, flag register is abandoned extremely according to data storage, data mode FIFO memory and multi-channel data
One of few current storage status, judges that can current data be read to leave active data storage and be forwarded
And/or data storage is entered by current data channel and is cached " specifically include:
In any clock cycle, if current data issues write request, the discarding flag register is traversed, judges current number
It identifies whether to be set as enabled in the corresponding discarding of discarding flag register according to the data channel passed through,
If so, abandoning current data；Within the subsequent clock cycle, current data institute current data in the packet is abandoned
All data later；Until there is new data packet input, and when by new data packet input, corresponding data storage
State judge whether update abandon flag register discarding mark；
If it is not, being judged whether to abandon current data according to the state of active data storage.
As the further improvement of an embodiment of the present invention, " in any clock cycle, when there are read requests for any data
And/or when write request, flag register is abandoned extremely according to data storage, data mode FIFO memory and multi-channel data
One of few current storage status, judges that can current data be read to leave active data storage and be forwarded
And/or data storage is entered by current data channel and is cached " specifically include:
In any clock cycle, if current data issues write request, judge whether active data storage is to expire,
If so, abandoning current data；And judge multi-channel data abandon flag register correspond to current data channel
When discarding is identified as non-enabled, by the channel number of data channel where current data and it is adjusted to enabled pressure stop bits
Mark write-in data mode FIFO memory；Meanwhile multi-channel data discarding flag register being corresponded to the discarding of current channel
Mark is set as enabled；Within the clock cycle of connecting, current data institute owning after current data in the packet is abandoned
Data, and after the last one data for abandoning current data packet, it is corresponding current logical that multi-channel data is abandoned into flag register
The discarding mark in road is set as non-enabled；
It is cached if it is not, the data storage is written in current data, by current data write-in data storage
Address, the channel number of data channel where current data and the pressure for being adjusted to non-enabled state terminate bit identification while writing
Enter data mode FIFO memory.
As the further improvement of an embodiment of the present invention, " according to data storage, data mode FIFO memory with
And multi-channel data abandon at least one of current storage status of flag register, judge current data can be read with
Active data storage is left to be forwarded " it specifically includes:
In any clock cycle, if receiving data reads request, data mode FIFO memory is inquired, judgement is current
Data occupy channel number corresponding to pressure stop bits identify whether to be set as enabled,
If so, without inquiring data storage；
If it is not, the data memory addresses inquiry data storage stored in data mode FIFO memory is obtained, to obtain
Current data is obtained to be exported.
As the further improvement of an embodiment of the present invention, after " if so, without inquiring data storage ", the method
Further include: it generates error message instruction and is sent to Subordinate module, abnormality processing is done with the data packet to the data and its place.
Another in order to achieve the above-mentioned object of the invention, an embodiment of the present invention provides a kind of processing unit of cache congestion,
Described device includes:
Memory module, the memory module include: data storage, data mode FIFO memory and multi-channel data
Flag register is abandoned,
The data storage is to store the data inputted by data channel, depth N；The data channel
Quantity is M；The data mode FIFO memory for storing data in memory storing data address, data channel is corresponding
Channel number and the corresponding pressure of data channel terminate bit identification, the minimum N+M of depth, the discarding flag register
Discarding for storing corresponding any data channel identifies, and minimum widith M, described M, N are the positive integer greater than 1；
Processing module, in a clock cycle in office, when any data is there are when read request and/or write request, according to
Data storage, data mode FIFO memory and multi-channel data abandon that flag register is at least one of currently to be deposited
Storage state, judge current data can be read with leave active data storage be forwarded and/or by current data it is logical
Road enters data storage and is cached.
As the further improvement of an embodiment of the present invention, the processing module is specifically used for, a clock cycle in office
It is interior, if current data issues write request, the discarding flag register is traversed, judges that the data channel that current data passes through is being lost
Non-paying bid will register it is corresponding discarding identify whether to be set as enabled,
If so, abandoning current data；Within the subsequent clock cycle, current data institute current data in the packet is abandoned
All data later；Until there is new data packet input, and when by new data packet input, corresponding data storage
State judge whether update abandon flag register discarding mark；
If it is not, being judged whether to abandon current data according to the state of active data storage.
As the further improvement of an embodiment of the present invention, the processing module is specifically used for, a clock cycle in office
It is interior, if current data issues write request, judge whether active data storage is to expire,
If so, abandoning current data；And judge multi-channel data abandon flag register correspond to current data channel
When discarding is identified as non-enabled, by the channel number of data channel where current data and it is adjusted to enabled pressure stop bits
Mark write-in data mode FIFO memory；Meanwhile multi-channel data discarding flag register being corresponded to the discarding of current channel
Mark is set as enabled；Within the clock cycle of connecting, current data institute owning after current data in the packet is abandoned
Data, and after the last one data for abandoning current data packet, it is corresponding current logical that multi-channel data is abandoned into flag register
The discarding mark in road is set as non-enabled；
It is cached if it is not, the data storage is written in current data, by current data write-in data storage
Address, the channel number of data channel where current data and the pressure for being adjusted to non-enabled state terminate bit identification while writing
Enter data mode FIFO memory.
As the further improvement of an embodiment of the present invention, the processing module is specifically used for, a clock cycle in office
It is interior, if receiving data reads request, data mode FIFO memory is inquired, judges the channel number institute that current data occupies
Corresponding pressure stop bits identifies whether to be set as enabled,
If so, without inquiring data storage；
If it is not, the data memory addresses inquiry data storage stored in data mode FIFO memory is obtained, to obtain
Current data is obtained to be exported.
As the further improvement of an embodiment of the present invention, the processing module is also used to, and is deposited without inquiring data
After reservoir, generates error message instruction and be sent to Subordinate module, abnormality processing is done with the data packet to the data and its place.
Compared with prior art, the processing method and processing device of cache congestion of the present invention is stored by introducing depth and data
The asymmetric data mode FIFO memory of device reduces memory resource to reduce the depth of data storage, promotes data and deposits
The effective rate of utilization of reservoir.
Detailed description of the invention
Fig. 1 is the structural schematic diagram that congestion processing framework is buffered described in background of invention；
Fig. 2 is the flow diagram of the processing method of cache congestion in an embodiment of the present invention；
Fig. 3, Fig. 4, Fig. 5 are respectively the specific implementation stream of one of step in the processing method of cache congestion described in Fig. 2
Journey schematic diagram；
Fig. 6 is the structural schematic diagram that congestion processing framework is buffered in an embodiment of the present invention；
Fig. 7 is the module map of the processing unit of cache congestion in an embodiment of the present invention.
Specific embodiment
Hereinafter, the present invention will be described in detail with reference to various embodiments shown in the accompanying drawings.But these embodiments are not
The limitation present invention, structure that those skilled in the art are made according to these embodiments, method or change functionally
It changes and is included within the scope of protection of the present invention.
Message is the data cell exchanged in network with transmission, i.e. the website data block disposably to be sent.Message includes
Complete data information to be sent, length is very inconsistent, length is unlimited and variable.Message passes through in transmittance process
Including multiple data packets, and each data packet includes multiple data；Application scenarios of the invention are the data parlor of multichannel
During being sent to low-bandwidth interfaces from high bandwidth interface, high bandwidth interface does not have under the scene of flow control, guarantees data not
It can overflow.
As shown in Fig. 2, in the first embodiment of the present invention, the processing method of the cache congestion, comprising: corresponding number
A data mode FIFO memory is created according to memory and multi-channel data abandons flag register.
The data storage is to store the data inputted by data channel, depth N；The data channel
Quantity is M；The data mode FIFO memory is data state memory, for storing data storing data in memory
Address, the corresponding channel number of data channel and the corresponding pressure end bit identification of data channel, the minimum N+M of depth,
The discarding mark for abandoning flag register and being used to store corresponding any data channel, minimum widith M, described M, N are equal
For the positive integer greater than 1.
In the specific embodiment of the invention, the depth of newly created data mode FIFO memory is according to the number of data channel
Amount and the depth of data storage are set, and the minimum value of the depth of data mode FIFO memory is equal to data channel
The sum of quantity and the depth of data storage, in this way, if data storage is full, and each data channel still has data biography
When defeated, data mode FIFO memory is still free leeway location the corresponding status information of current data is written.
In an embodiment of the present invention, which comprises in any clock cycle, when there are read requests for any data
And/or when write request, flag register is abandoned extremely according to data storage, data mode FIFO memory and multi-channel data
One of few current storage status, judges that can current data be read to leave active data storage and be forwarded
And/or data storage is entered by current data channel and is cached.
In the specific embodiment of the invention, when data storage is written in data or reads from data storage, data shape
State FIFO memory and multi-channel data, which abandon the corresponding flag bit of flag register, to do phase according to the storage state of data
It should change.
Correspondingly, as shown in connection with fig. 3, in write-in data procedures, in any clock cycle, being asked if current data sending is write
It asks, traverses the discarding flag register, judging data channel that current data passes through, flag register is corresponding to be lost abandoning
Abandoning identifies whether to be set as enabled, if so, abandoning current data；Within the subsequent clock cycle, number where current data is abandoned
According to all data after current data in packet；It is right until there is new data packet input, and when by new data packet input
The state for the data storage answered judges whether to update the discarding mark for abandoning flag register；If it is not, being deposited according to current data
The state of reservoir judges whether to abandon current data.
The corresponding data channel of each memory space for abandoning flag register, is writing data into data storage mistake
Cheng Zhong, it is described abandon flag register storage state change therewith, if write-in data procedures in, data storage be it is full, then
Data storage cannot be written in current data, so need discarding flag register corresponding to the data that current data is passed through and lead to
Track address is adjusted to enabled, and the state is maintained until data storage has new effective address release, and corresponding data channel has
New data packet input；Correspondingly, data are normally written during data storage, the discarding flag register is corresponding current
The dataachannelaaddress that data are passed through is non-enabled state；In a better embodiment of the invention, with binary zero " 1 " table
Show the enabled state for abandoning any address of flag register, when it is " 1 ", indicates enabled, when it is " 0 ", indicating non-makes
Energy.In the initial state, the default value for abandoning each memory space of flag register is " 0 ", once a certain memory space
Data in corresponding data channel need to abandon, and corresponding bit will be set as " 1 ".
Correspondingly, as shown in connection with fig. 4, in write-in data procedures, in any clock cycle, being asked if current data sending is write
It asks, judges whether active data storage is full, if so, abandoning current data；And judge multi-channel data abandon mark post
When the discarding that storage corresponds to current data channel is identified as non-enabled, by the channel number of data channel where current data and
The pressure for being adjusted to enabled terminates bit identification write-in data mode FIFO memory；Meanwhile multi-channel data discarding mark being posted
The discarding mark that storage corresponds to current channel is set as enabled；Within the clock cycle of connecting, data where current data are abandoned
All data in packet after current data, and after the last one data for abandoning current data packet, multi-channel data is lost
Non-paying bid will register pair should the discarding mark of prepass be set as non-enabled；It is deposited if it is not, the data are written in current data
Reservoir is cached, by the address of current data write-in data storage, the channel number of data channel where current data with
And it is adjusted to the pressure of non-enabled state and terminates bit identification while data mode FIFO memory is written.
It is understood that including several data in a data packet, when one of data-transmission interruptions and lost
After abandoning, current data packet is imperfect state, in this way, in current data packet, data from after abandoning data are by whole quilts
It abandons, and within a clock cycle, usually transmitting a data further needs within subsequent multiple clock cycle,
The remaining data of current data packet are successively abandoned, further, after current data packet is all dropped, need to be corresponded to number
It is set as non-enabled according to the discarding mark in channel, and when new data packet is inputted by current data channel, because it corresponds to number
It is identified as non-enabled, and new data packet is handled again according to the state of data storage again according to the discarding in channel.
Each memory space of data mode FIFO memory corresponds to the address of storing data in storing data memory, leads to
Road number and the corresponding pressure of data channel terminate bit identification, when request of data writes into data storage, data mode
Whether the state of FIFO memory can be written into data storage according to write-in data and is adjusted, if data can be written into number
According to memory, then it is written into the address in data storage, the data channel that write-in data pass through, and force stop bits mark
Knowledge be adjusted to it is non-it is enabled after, while being written in one of storage address of data mode FIFO memory；If data storage
Be it is full, then data storage cannot be written in current data, at this time, it may be necessary to which it is corresponding logical that data channel that data are passed through will be written
Road number, and force end bit identification to be adjusted to one enabled rear while that data mode FIFO memory is written for corresponding
In storage address；In a better embodiment of the invention, there is a ratio in each storage address of data mode FIFO memory
Spy forces to terminate bit identification for being written, which forces to terminate bit identification by write-in binary zero " 1 " to indicate
Enabled state indicates enabled when it is " 1 ", when it is " 0 ", indicates non-enabled.
Correspondingly, as shown in connection with fig. 5, in reading data procedures, in any clock cycle, being asked if receiving data reading
It asks, then inquires data mode FIFO memory, judge that pressure corresponding to the channel number of current data occupancy terminates bit identification
Whether it is set as enabled, if so, without inquiring data storage；If it is not, obtaining the number stored in data mode FIFO memory
Data storage is inquired according to storage address, is exported with obtaining current data.
In the embodiment, if the pressure for reading the data channel that data occupy terminates bit identification and is set as enabled, show
It is the data being dropped, in writing process, and is not written in data storage, correspondingly, without inquires data storage
Device, and generate error message instruction and be sent to Subordinate module, abnormality processing is done with the data packet to the data and its place；Such as
Fruit, corresponding pressure terminate bit identification and are set as non-enabled, then show that current data can be read, at this point, according to normal
Program reads data, to discharge data memory space and the data mode FIFO memory space of its occupancy.
In order to make it easy to understand, the present invention describes a specific example for reference:
As shown in connection with fig. 6, in the example, to write place to data storage when continuous input data in same data channel
For reason: assuming that data storage has N number of storage address, it is respectively 0,1,2 ... N-1；The quantity of data channel is arranged
For M item, then it is respectively that 0,1,2 ... N-1 ... N+M-1 lose that data mode FIFO memory, which has M+N storage location,
Abandoning flag register has M storage address, is respectively 0,1,2 ... M-1；Each storage address of data storage is used
In a data are written, address, the channel of each storage address write-in data storage of data mode FIFO memory are compiled
Number and force to terminate bit identification, each address for abandoning flag register is used to store the discarding mark in corresponding any data channel
Know；In addition, the data channel of present input data is indicated with data channel 0, multiple clock cycle of the data channel 0 in connecting
Interior, the data of input are respectively data 0, data 1, data 2 ... data X.
Assuming that when the data 0 of data channel 0 input, the ground of data storage is written in first clock cycle
Location N-1, i.e. write-in the last one effective address space of data storage, then simultaneously by the address N-1 of data storage, data are logical
The channel number 0 in road 0 and pressure terminate write-in after bit identification is adjusted to 0 will abandon mark and deposits according to state FIFO memory
Device abandons mark accordingly and is adjusted to 0.
In second clock cycle, when the data 1 of data channel 0 input, data storage does not have address release, that is, arrives
Up to full state, at this time, it may be necessary to by the channel number 0 of data channel 0, and force to terminate that data are written after bit identification is set to 1
State FIFO memory, while the bit0 for abandoning flag register is set to 1, to show being in current data for subsequent input
The data of same data packet need to do discard processing.
In the third clock cycle, the data 2 of data channel 0 are inputted, and are looked into search data channel 0 first and are being abandoned register
In the discarding of corresponding data be identified as 1, then just data 2 are abandoned.
Further, within subsequent multiple clock cycle, other numbers of same data packet are in channel 0 with data 2
According to will all be handled according to the step of data 2, until effective address releases in data storage, and data channel 0
There is new data packet input, data storage could be written into again, while multi-channel data is abandoned into flag register
Bit0 is set to 0 again.
As shown in fig. 7, in the first embodiment of the present invention, the processing unit of the cache congestion includes: storage mould
Block 100 and processing module 200；The memory module 100 includes: data storage 101, data mode FIFO memory 103
And multi-channel data abandons flag register 105.
The data storage 101 is to store the data inputted by data channel, depth N；The data are logical
The quantity in road is M；The data mode FIFO memory 103 is data state memory, for storing data in memory 101
The address of storing data, the corresponding channel number of data channel and the corresponding pressure of data channel terminate bit identification, depth
Minimum N+M, the discarding mark for abandoning flag register and being used to store corresponding any data channel, minimum widith M,
Described M, N are the positive integer greater than 1.
In the specific embodiment of the invention, the depth of newly created data mode FIFO memory 103 is according to data channel
Quantity and the depth of data storage 101 set, the minimum value of the depth of data mode FIFO memory 103 is equal to
The sum of quantity and the depth of data storage 101 of data channel, in this way, if data storage 101 is full, and each data
When still there is data transmission in channel, data mode FIFO memory 103 is still free leeway location corresponding current data is written
Status information.
Processing module 200 is in a clock cycle in office, when receiving any data, there are read request and/or write requests
When, flag register 105 is abandoned at least according to data storage 101, data mode FIFO memory 103 and multi-channel data
The current storage status of one of them, judges that can current data be read to leave active data storage 101 and be forwarded
And/or data storage 101 is entered by current data channel and is cached.
In the specific embodiment of the invention, when data storage 101 is written in data or reads from data storage 101,
Data mode FIFO memory 103 and multi-channel data abandon the corresponding flag bit of flag register 105 can be according to data
Storage state does corresponding change.
Correspondingly, processing module 200 was specifically used in a clock cycle in office, if receiving in write-in data procedures
The write request that current data issues traverses the discarding flag register 105, judges that the data channel that current data passes through is being lost
It abandons the corresponding discarding of flag register 105 to identify whether to be set as enabled, if so, abandoning current data；In subsequent clock week
In phase, abandon current data all data after current data in the packet；Until there is new data packet input, and lead to
When crossing new data packet input, the state of corresponding data storage 101, which judges whether to update, abandons flag register 105
Abandon mark；If it is not, being judged whether to abandon current data according to the state of active data storage 101.
The corresponding data channel of each memory space for abandoning flag register, is writing data into data storage
During 101, the storage state for abandoning flag register is changed therewith, if in write-in data procedures, data storage 101
Be it is full, then data storage 101 cannot be written in current data, so need to abandon flag register and correspond to current data and lead to
The dataachannelaaddress crossed is adjusted to enabled, and the state is and right maintained until data storage 101 has new effective address release
Data channel is answered to have new data packet input；Correspondingly, data are normally written during data storage 101, the discarding mark
The dataachannelaaddress that will register pair answers current data to be passed through is non-enabled state；In a better embodiment of the invention,
Indicate that the enabled state for abandoning any address of flag register indicates enabled, when it when it is " 1 " with binary zero " 1 "
When for " 0 ", indicate non-enabled.In the initial state, the default value for abandoning each memory space of flag register is " 0 ",
Once the data in the corresponding data channel of a certain memory space need to abandon, corresponding bit will be set as " 1 ".
Correspondingly, processing module 200 was specifically used in a clock cycle in office, if current data in write-in data procedures
Write request is issued, judges whether active data storage 101 is completely, if so, abandoning current data, and to judge multi-channel data
When the discarding in the corresponding current data channel of discarding flag register 105 is identified as non-enabled, by data channel where current data
Channel number and be adjusted to enabled pressure terminate bit identification write-in data mode FIFO memory 103；Meanwhile by multi-pass
The discarding mark that track data abandons the corresponding current channel of flag register 105 is set as enabled, within the clock cycle of connecting, loses
Abandon current data all data after current data in the packet, and after abandoning the last one data, by multichannel
The discarding mark that data abandon the corresponding current channel of flag register 105 is set as non-enabled；If it is not, institute is written in current data
It states data storage 101 to be cached, by the address of current data write-in data storage 101, data are logical where current data
The channel number in road and the pressure for being adjusted to non-enabled state terminate bit identification while data mode FIFO memory are written
105。
It is understood that including several data in a data packet, when one of data-transmission interruptions and lost
After abandoning, current data packet is imperfect state, in this way, in current data packet, data from after abandoning data are by whole quilts
It abandons, and within a clock cycle, usually transmitting a data further needs within subsequent multiple clock cycle,
The remaining data of current data packet are successively abandoned, further, after current data packet is all dropped, need to be corresponded to number
It is set as non-enabled according to the discarding mark in channel, and when new data packet is inputted by current data channel, because it corresponds to number
It is identified as non-enabled, and new data packet is handled again according to the state of data storage 101 again according to the discarding in channel.
Each memory space of data mode FIFO memory 103 corresponds to storing data in storing data memory 101
Address, channel number and the corresponding pressure of data channel terminate bit identification, when request of data writes into data storage 101,
Whether the state of data mode FIFO memory 103 can be written into data storage 101 according to write-in data and is adjusted, if
Data can be written into data storage 101, then is written into the address in data storage 101, the data that write-in data pass through
Channel, and force to terminate bit identification be adjusted to it is non-it is enabled after, while one of them of data mode FIFO memory 103 is written
In storage address；If data storage 101 be it is full, data storage 101 cannot be written in current data, at this time, it may be necessary to will write
Enter the corresponding channel number of data channel that data are passed through, and corresponding pressure end bit identification is adjusted to enabled rear same
When write-in data mode FIFO memory 103 a storage address in；In a better embodiment of the invention, data mode
Have in each storage address of FIFO memory 103 bit for be written force end bit identification, which passes through write-in
Binary zero " 1 ", when it is " 1 ", indicates enabled to the enabled state for indicating to force to terminate bit identification, when it is " 0 "
When, indicate non-enabled.
Correspondingly, processing module 200 was specifically used in a clock cycle in office, if receiving in reading data procedures
Data read request, then inquire data mode FIFO memory 103, judge strong corresponding to the channel number of current data occupancy
Stop bits processed identifies whether to be set as enabled, if so, without inquiring data storage 101；It is deposited if it is not, obtaining data mode FIFO
The data memory addresses inquiry data storage 101 stored in reservoir 103, is exported with obtaining current data.
In the embodiment, if the pressure for reading the data channel that data occupy terminates bit identification and is set as enabled, show
It is the data being dropped, in writing process, and is not written in data storage 101, correspondingly, is deposited without inquiring data
Reservoir 101, further, the processing module 200 are also used to generate error message instruction and are sent to Subordinate module, to this
Data and its data packet at place do abnormality processing；If corresponding pressure, which terminates bit identification, is set as non-enabled, then show
Current data can be read, at this point, data are read according to normal procedure, to discharge 101 space of data storage of its occupancy
With 103 space of data mode FIFO memory.
Compared with prior art, the processing method and processing device of cache congestion of the present invention is stored by introducing depth and data
The asymmetric data mode FIFO memory of device reduces data storage to record the state of data packet and force end of identification
The depth of device；In cache congestion, dropping packets is forced, while recording pressure end of identification, on the one hand avoids cache overflow,
On the other hand it can identify that the message of partial write data storage is normal message, effectively reduce data and deposit
Memory resource promotes the effective rate of utilization of data storage.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description
The specific work process of middle module, can be with reference to the corresponding process in preceding method embodiment, and details are not described herein.
System embodiment described above is only schematical, wherein the module as illustrated by the separation member
It may or may not be physically separated, the component shown as module is logic module, it can be located at chip
In a module in logic, or it may be distributed on multiple data processing modules in chip.It can be according to actual
The purpose for needing to select some or all of the modules therein to realize present embodiment scheme.Those of ordinary skill in the art exist
In the case where not making the creative labor, it can understand and implement.
The application can be used in numerous general or special purpose communication chips.Such as: exchange chip, router chip, service
Device chip etc..
It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one
A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say
As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book
With the other embodiments of understanding.
The series of detailed descriptions listed above only for feasible embodiment of the invention specifically
Protection scope bright, that they are not intended to limit the invention, it is all without departing from equivalent implementations made by technical spirit of the present invention
Or change should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of processing method of cache congestion, which is characterized in that the described method includes:
Corresponding data memory creates a data mode FIFO memory and multi-channel data abandons flag register；
The data storage is to store the data inputted by data channel, depth N；The quantity of the data channel
For M；The data mode FIFO memory for storing data in memory storing data address, data channel is corresponding logical
Road number and the corresponding pressure of data channel terminate bit identification, the minimum N+M of depth, and the discarding flag register is used for
The discarding mark in corresponding any data channel is stored, minimum widith M, described M, N are the positive integer greater than 1；
In any clock cycle, when any data is there are when read request and/or write request, according to data storage, data mode
FIFO memory and multi-channel data abandon at least one of current storage status of flag register, judge current data
Can be read with leave active data storage be forwarded and/or by current data channel enter data storage carry out
Caching.
2. the processing method of cache congestion according to claim 1, which is characterized in that " in any clock cycle, when any
Data are lost there are when read request and/or write request according to data storage, data mode FIFO memory and multi-channel data
At least one of current storage status of flag register is abandoned, judges that can current data be read to leave current data and deposit
Reservoir is forwarded and/or enters data storage by current data channel and cached " it specifically includes:
In any clock cycle, if current data issues write request, the discarding flag register is traversed, judges that current data is logical
The data channel crossed abandon flag register it is corresponding discarding identify whether to be set as enabled,
If so, abandoning current data；Within the subsequent clock cycle, discarding current data institute is in the packet after current data
All data；Until there is new data packet input, and when by new data packet input, the shape of corresponding data storage
State judges whether to update the discarding mark for abandoning flag register；
If it is not, being judged whether to abandon current data according to the state of active data storage.
3. the processing method of cache congestion according to claim 2, which is characterized in that " in any clock cycle, when any
Data are lost there are when read request and/or write request according to data storage, data mode FIFO memory and multi-channel data
At least one of current storage status of flag register is abandoned, judges that can current data be read to leave current data and deposit
Reservoir is forwarded and/or enters data storage by current data channel and cached " it specifically includes:
In any clock cycle, if current data issues write request, judge whether active data storage is to expire,
If so, abandoning current data；And judging that multi-channel data abandons flag register and correspond to the discarding in current data channel
When being identified as non-enabled, by the channel number of data channel where current data and it is adjusted to enabled pressure and terminates bit identification
Data mode FIFO memory is written；Meanwhile the discarding that multi-channel data discarding flag register corresponds to current channel being identified
It is set as enabled；Within the clock cycle of connecting, abandon current data all data after current data in the packet,
And after the last one data for abandoning current data packet, multi-channel data discarding flag register is corresponded into losing for current channel
Non-paying bid knowledge is set as non-enabled；
It is cached if it is not, the data storage is written in current data, current data is written to the address of data storage,
The channel number of data channel where current data and the pressure for being adjusted to non-enabled state terminate bit identification while number are written
According to state FIFO memory.
4. the processing method of cache congestion according to any one of claims 1 to 3, which is characterized in that " stored according to data
Device, data mode FIFO memory and multi-channel data abandon at least one of current storage status of flag register,
Can judge current data be read to leave active data storage and be forwarded " it specifically includes:
In any clock cycle, if receiving data reads request, data mode FIFO memory is inquired, judges current data
Pressure stop bits corresponding to the channel number of occupancy identifies whether to be set as enabled,
If so, without inquiring data storage；
If it is not, the data memory addresses inquiry data storage stored in data mode FIFO memory is obtained, to be worked as
Preceding data are exported.
5. the processing method of cache congestion according to claim 4, which is characterized in that " if so, without inquiring data storage
After device ", the method also includes: it generates error message instruction and is sent to Subordinate module, with the number to the data and its place
Abnormality processing is done according to packet.
6. a kind of processing unit of cache congestion, which is characterized in that described device includes:
Memory module, the memory module include: data storage, and data mode FIFO memory and multi-channel data abandon
Flag register；
The data storage is to store the data inputted by data channel, depth N；The quantity of the data channel
For M；The data mode FIFO memory for storing data in memory storing data address, data channel is corresponding logical
Road number and the corresponding pressure of data channel terminate bit identification, the minimum N+M of depth, and the discarding flag register is used for
The discarding mark in corresponding any data channel is stored, minimum widith M, described M, N are the positive integer greater than 1；
Processing module, in a clock cycle in office, when any data is there are when read request and/or write request, according to data
Memory, data mode FIFO memory and multi-channel data abandon at least one of currently stored shape of flag register
State, judge current data can be read with leave active data storage be forwarded and/or by current data channel into
Entry data memory is cached.
7. the processing unit of cache congestion according to claim 6, which is characterized in that the processing module is specifically used for,
In a clock cycle in office, if current data issues write request, the discarding flag register is traversed, judges that current data passes through
Data channel abandon flag register it is corresponding discarding identify whether to be set as enabled,
If so, abandoning current data；Within the subsequent clock cycle, discarding current data institute is in the packet after current data
All data；Until there is new data packet input, and when by new data packet input, the shape of corresponding data storage
State judges whether to update the discarding mark for abandoning flag register；
If it is not, being judged whether to abandon current data according to the state of active data storage.
8. the processing unit of cache congestion according to claim 7, which is characterized in that the processing module is specifically used for,
In a clock cycle in office, if current data issues write request, judge whether active data storage is to expire,
If so, abandoning current data；And judging that multi-channel data abandons flag register and correspond to the discarding in current data channel
When being identified as non-enabled, by the channel number of data channel where current data and it is adjusted to enabled pressure and terminates bit identification
Data mode FIFO memory is written；Meanwhile the discarding that multi-channel data discarding flag register corresponds to current channel being identified
It is set as enabled；Within the clock cycle of connecting, abandon current data all data after current data in the packet,
And after the last one data for abandoning current data packet, multi-channel data discarding flag register is corresponded into losing for current channel
Non-paying bid knowledge is set as non-enabled；
It is cached if it is not, the data storage is written in current data, current data is written to the address of data storage,
The channel number of data channel where current data and the pressure for being adjusted to non-enabled state terminate bit identification while number are written
According to state FIFO memory.
9. according to the processing unit of the described in any item cache congestions of claim 6 to 8, which is characterized in that the processing module
It is specifically used for, in a clock cycle in office, if receiving data reads request, inquires data mode FIFO memory, judge
Current data occupy channel number corresponding to pressure stop bits identify whether to be set as enabled,
If so, without inquiring data storage；
If it is not, the data memory addresses inquiry data storage stored in data mode FIFO memory is obtained, to be worked as
Preceding data are exported.
10. the processing unit of cache congestion according to claim 9, which is characterized in that the processing module is also used to,
After inquiring data storage, generates error message instruction and be sent to Subordinate module, with the number to the data and its place
Abnormality processing is done according to packet.
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