CN204272167U

CN204272167U - A kind of data through type repeat circuit based on memory

Info

Publication number: CN204272167U
Application number: CN201420774237.0U
Authority: CN
Inventors: 王玉欢; 杨海波; 李攀; 蔡叶芳; 刘航; 张荣华
Original assignee: AVIC No 631 Research Institute
Current assignee: Xian Xiangteng Microelectronics Technology Co Ltd
Priority date: 2014-12-09
Filing date: 2014-12-09
Publication date: 2015-04-15
Anticipated expiration: 2024-12-09

Abstract

The utility model relates to a kind of data through type repeat circuit based on memory, this circuit provides a kind of mode for data receiver, storage, forwarding, setting data memory, odd address tag memory and even address tag memory respectively, the state of putting respective flag memory while data are written in data storage will be received, and remove the state flag bit of next data, after constrained input connects, immediately can read the through type retransmission method of data successively from data storage.The data retransmission circuit that this circuit and method provide and method substantially increase data retransmission efficiency.

Description

A kind of data through type repeat circuit based on memory

Technical field

The utility model belongs to integrated circuit (IC) design technology, relates to a kind of data through type repeat circuit based on memory and method.

Background technology

In the transmission of data, in the design of especially switch, the data retransmission receiving is needed to go out.Therefore need a kind of data retransmission circuit efficiently to complete this work.

Namely etc. traditional way is based on being stored into row data retransmission, and whole packet carries out the forwarding of data again after being all ready to, and this way can cause data throughput low, and time delay is comparatively large, and expends storage resources.

Summary of the invention

The technical problem that throughput is low, time delay is comparatively large and expend storage resources is there is in order to solve existing data retransmission circuit, the utility model provides a kind of data through type repeat circuit based on memory, this circuit can increase forward efficiency to greatest extent, reduce propagation delay time slow, and saving storage resources, and can be multiplexing in other projects based on data retransmission.

Technical solution of the present utility model:

Based on a data through type repeat circuit for memory, its special character is: comprise frame and receive control module 1, new frame sequence FIFO memory 2, data storage 3, tag memory 4 and read control module 5; Wherein, frame receives control module 1 and connects new frame sequence FIFO memory 2, and simultaneous connection is according to memory 3 and tag memory 4, and meanwhile, data storage 3 is connected with read control module 5 with tag memory 4;

Frame receives control module 1 and is written to by frame data by the Frame received in corresponding data storage 3 in order by frame head, to store in the Status Flag write tag memory 4 of data in these frame data simultaneously, the state of clear flag memory 4 next address, until postamble.

Above-mentioned tag memory 4 is made up of even address tag memory and odd address tag memory, and described even address tag memory is for storing the data mode mark on data storage 3 even address; Described odd address tag memory is for storing the data mode mark on data storage 3 odd address.

Above-mentioned data storage 3 has M memory address; The memory address of described even address tag memory and the memory address sum of odd address tag memory are M.

The beneficial effect that the utility model has:

The utility model adopts the mode arranging strange tag memory and even tag memory respectively, first receive control module 1 by frame writes in corresponding data storage 2 by frame data by the Frame received in order by frame head, put strange tag memory and even tag memory is corresponding states simultaneously, until postamble, then by read control module 4 read data frame from strange tag memory, even tag memory and data storage.The utility model can increase forward efficiency to greatest extent, reduces propagation delay time slow, and saves storage resources, and can be multiplexing in other projects based on data retransmission.

Accompanying drawing explanation

Fig. 1 is that the utility model is a kind of based on the data through type repeat circuit of memory and the configuration diagram of method.

Embodiment

Below in conjunction with drawings and Examples, the utility model is described further:

As shown in Figure 1.A kind of the comprising based on the data through type repeat circuit of memory and the framework of method that the utility model relates to receives control module 1, new frame sequence FIFO 2, data storage 3, tag memory 4 and read control module 5; Wherein, receive control module 1 and connect new frame sequence FIFO 2, simultaneous connection is according to the input of memory 3 and tag memory 4, and data storage 3 is connected with read control module 5 with the output of tag memory 4.

Receive control module 1 writes in corresponding data storage 3 by frame data according to sequence of addresses by the Frame received by frame head, put tag memory 4 for corresponding states simultaneously, the tag memory removing next address corresponding is that " 00 " (" 00 " representative data is invalid, " 01 " represents effective SOF, " 10 " represent valid frame content " 11 " and represent effective EOF, after reset by special initializing circuit by 0 address of the logic partitioning 0-7 of even address tag memory successively secondary write " 00 "; One time data exchanging completed is put " 00 " by even address mark 0 address of scheduling logic by corresponding buffer stopper, completes release) until postamble.

New frame sequence FIFO 2 degree of depth is M, for storing buffer logic block number, the degree of depth and the buffer logic block number of new frame sequence FIFO 2 are consistent, after reception control module 1 receives Frame, search for buffer logic block available in M buffer logic block, then by buffer logic block number write new frame sequence FIFO 2.

As shown in Figure 1, data storage 3 is for storing data, and comprise the logic partitioning of M (2N+2), each piecemeal deposits a content frame (from SOF) by address 0.

As shown in Figure 1, tag memory 4 is made up of even address tag memory and odd address tag memory, the corresponding even address (0 of storage internal representation data memory of each address of the logic partitioning of M 2bit* (N+1) of even address tag memory, 2,4,6,8 ...) data mode, " 00 " representative data is invalid; " 01 " represents effective SOF data; " 10 " represent effective payload data; " 11 " represent effective EOF data; The corresponding odd address (1,3,5,7 of storage internal representation data memory of each address of the logic partitioning of M 2bit* (N+1) of odd address tag memory ...) data mode.

Read control module 5 is for reading the tag memory 4 of data storage 3 and corresponding address, first judge whether even address tag memory is read " 01 ", if read " 01 " (namely SOF is effective), then obtain effective SOF of data storage output until read effective marker and valid data, progressively increase in address, frame count progressively increases, read odd address tag memory again, read successively, until read valid frame tail tag will, after reading end frame, read and terminate, toward address write " 00 " of corresponding address tag memory correspondence buffering, discharge this buffer stopper.

A kind of data through type retransmission method implementation method step based on memory is as follows:

1) after reception control module 1 receives Frame, search for buffer logic block available in M buffer logic block, then by buffer logic block number write new frame sequence FIFO 2, frame data are write the logical block of data storage 3 correspondence by SOF simultaneously, store data frame successively, put address corresponding to even tag memory for " 01 " (" 01 " represents effective SOF data) simultaneously, the same clock cycle puts address corresponding to odd address tag memory for " 00 " (" 00 " representative data is invalid), namely tag memory 4 corresponding to next address is removed, until EOF,

2) each piecemeal of data storage 3 deposits content frame (from SOF), successively a store data frame by address 0;

3) in tag memory 4, the content of write represents the data mode of corresponding data storage, and data mode comprises invalid data, valid frame leader will, valid frame Notation Of Content, valid frame tail tag will;

4) after connection establishment, read control module 5 reads the address of the address of the corresponding buffer stopper of even address tag memory number and the corresponding buffer stopper of data storage number from new frame sequence FIFO 2, judge whether even address tag memory is read " 01 ", if read " 01 " (namely SOF is effective), then obtain effective SOF that data storage exports, progressively increase in address, frame count progressively increases, following reading odd address tag memory, if read " 10 " (namely data are effective), then obtain valid data;

5) repeat step 4, until read valid frame tail tag will, frame reads and terminates, and the address 0 toward corresponding address tag memory correspondence buffering writes " 00 ", discharges this buffer stopper.

Last it is noted that above embodiment is only in order to illustrate the technical solution of the utility model, be not intended to limit; Although explain the utility model with reference to previous embodiment, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of each embodiment technical scheme of the utility model.

Claims

1. based on a data through type repeat circuit for memory, it is characterized in that: comprise frame and receive control module (1), new frame sequence FIFO memory (2), data storage (3), tag memory (4) and read control module (5); Wherein, frame receives control module (1) and connects new frame sequence FIFO memory (2), simultaneous connection is according to memory (3) and tag memory (4), meanwhile, data storage (3) is connected with read control module (5) with tag memory (4);

Frame receives control module (1) and is written to by frame data by the Frame received in corresponding data storage (3) in order by frame head, to store in Status Flag write tag memory (4) of data in these frame data simultaneously, the state of clear flag memory (4) next address, until postamble.

2. the data through type repeat circuit based on memory according to claim 1, it is characterized in that: described tag memory (4) is made up of even address tag memory and odd address tag memory, described even address tag memory is for storing the data mode mark on data storage (3) even address; Described odd address tag memory is for storing the data mode mark on data storage (3) odd address.

3. the data through type repeat circuit based on memory according to claim 1 and 2, is characterized in that: described data storage (3) has M memory address; The memory address of described even address tag memory and the memory address sum of odd address tag memory are M.