CN111026687B - Method, system and computer equipment for data transmission read-write rate matching - Google Patents
Method, system and computer equipment for data transmission read-write rate matching Download PDFInfo
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- CN111026687B CN111026687B CN201911044148.4A CN201911044148A CN111026687B CN 111026687 B CN111026687 B CN 111026687B CN 201911044148 A CN201911044148 A CN 201911044148A CN 111026687 B CN111026687 B CN 111026687B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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Abstract
The invention provides a method, a system and computer equipment for matching data transmission read-write rate, wherein the method comprises the following steps: the DMA controller receives the data sent by the PCM interface and sends an interrupt signal to the processor according to the received data quantity; the processor acquires an interrupt signal and acquires a pointer position corresponding to the interrupt time; copying data corresponding to preset interrupt duration from the memory without the cache of the DMA channel to the memory with the cache applied in advance by the processor according to the pointer positions respectively recorded at the interrupt signal moments; the processor reads data with a packing time length from the memory with the cache to the system memory for coding. In the opposite direction, the processor copies the decoded data from the system memory with the cache to the DMA channel memory without the cache according to the number of the interrupt signals, so that the PCM read-write function operated by the processor reads the data from the memory with the cache, and the problem of unbalanced PCM read-write interface speed is solved.
Description
Technical Field
The present invention relates to the field of data transmission in communications, and in particular, to a method, a system, and a computer device for data transmission read-write rate matching.
Background
The pulse code modulation (Pulse Code Modulation, PCM) interface is a time division multiplexed interface, and the direct memory access (Direct Memory Access, DMA) controller is a unique peripheral for transferring data within the system, which can be considered as a controller capable of connecting memory and external memory to each DMA capable peripheral via a set of dedicated buses, the DMA controller performing the transfer under the programmed control of the processor. In Linux sound card driving ASoC Platform, PCM-DMA architecture is used to apply for DMA channels for transmitting data, so as to reduce the burden of a processor. In practical application, the operation time of reading data of the PCM interface is found to be longer than the operation time of writing data, a single test is performed for the read operation and the write operation, the read operation time is found to be 3 times of the write operation time, so that the read-write speed of the PCM interface is unbalanced, the system coding time is longer than the decoding time, and the read operation time and the write operation time are quite an optimized direction by reducing the read operation time in order to improve the coding and decoding channel number of the system.
Accordingly, there is a need for further improvements in the art.
Disclosure of Invention
In view of the shortcomings of the prior art, the invention provides a method, a system and computer equipment for matching data transmission read-write speed, which aim to solve the technical problem of unbalanced PCM read-write speed.
In a first aspect, an embodiment of the present invention provides a method for matching a read-write rate of data transmission, where the method includes:
the DMA controller receives the data sent by the PCM interface and sends an interrupt signal to the processor according to the received data;
copying data corresponding to a preset interrupt duration from the memory of the DMA channel to a memory area applied in advance by the processor according to the received two continuous interrupt signals;
and the processor reads data corresponding to the preset packing time length in the memory area according to the received interrupt signal, wherein the ratio of the packing time length to the interrupt time length is a positive integer.
As a further improved technical solution, the DMA controller receives data sent by the PCM interface, and sends an interrupt signal to the processor according to the received data, including:
and each time the DMA controller receives data corresponding to a preset interrupt duration sent by the PCM interface, sending an interrupt signal to the processor.
As a further improved technical solution, the processor copies data corresponding to a preset interrupt duration from a memory of the DMA channel to a memory area applied in advance according to two received continuous interrupt signals, including:
the processor acquires pointer positions corresponding to the two continuous interrupt signals respectively according to the received two continuous interrupt signals;
and the processor copies the data corresponding to the preset interrupt duration from the memory of the DMA channel to the memory area applied in advance according to the pointer positions respectively corresponding to the two continuous interrupt signals.
As a further improvement technical solution, the processor obtains pointer positions corresponding to two continuous interrupt signals respectively according to the received two continuous interrupt signals, including:
when the processor receives an Nth interrupt signal, acquiring an Nth pointer position, wherein N is a positive integer;
and when the processor receives the (N+1) th interrupt signal, acquiring the (N+1) th pointer position, wherein the (N+1) th interrupt signal is the next interrupt signal of the received (N) th interrupt signal.
As a further improved technical scheme, the processor copies data corresponding to a preset interrupt duration from the memory of the DMA channel to a memory area applied in advance according to two received continuous interrupt signals, specifically:
the processor copies the data between the N pointer position and the N+1 pointer position to the memory area, wherein the data between the N pointer position and the N+1 pointer position is the data corresponding to the interrupt duration.
As a further improved technical solution, the processor reads data corresponding to a preset packing duration in the memory area according to the received interrupt signal, including:
each time the processor receives an interrupt signal, the counter is controlled to be increased by 1;
when the value of the counter reaches a preset value, the processor reads data corresponding to a preset packing time length in the memory area, wherein the preset value is the ratio of the packing time length to the interrupt time length;
the processor controls the counter to zero.
As a further improved technical solution, the DMA controller receives data sent by a PCM interface, including:
applying for a memory area with a cache in a preset size in advance;
and modifying the memory accessed by the read data into the memory area.
In a second aspect, an embodiment of the present invention provides a system for matching a read-write rate of data transmission, including: a DMA controller and a processor;
the DMA controller is used for receiving the data sent by the PCM interface and sending an interrupt signal to the processor according to the received data;
the processor is used for copying data corresponding to preset interrupt duration from the memory of the DMA channel to a memory area applied in advance according to the received two continuous interrupt signals; the method comprises the steps of,
and the method is also used for reading data corresponding to the preset packing time length in the memory area according to the received interrupt signal, wherein the ratio of the packing time length to the interrupt time length is a positive integer.
In a third aspect, an embodiment of the present invention provides a computer device, including a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:
the DMA controller receives the data sent by the PCM interface and sends an interrupt signal to the processor according to the received data;
copying data corresponding to a preset interrupt duration from the memory of the DMA channel to a memory area applied in advance by the processor according to the received two continuous interrupt signals;
and the processor reads data corresponding to the preset packing time length in the memory area according to the received interrupt signal, wherein the ratio of the packing time length to the interrupt time length is a positive integer.
In a fourth aspect, embodiments of the present invention provide a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of:
the DMA controller receives the data sent by the PCM interface and sends an interrupt signal to the processor according to the received data;
copying data corresponding to a preset interrupt duration from the memory of the DMA channel to a memory area applied in advance by the processor according to the received two continuous interrupt signals;
and the processor reads data corresponding to the preset packing time length in the memory area according to the received interrupt signal, wherein the ratio of the packing time length to the interrupt time length is a positive integer.
Compared with the prior art, the embodiment of the invention has the following advantages:
the method provided by the embodiment of the invention comprises the following steps: the DMA controller receives the data sent by the PCM interface and sends an interrupt signal to the processor according to the received data; copying data corresponding to a preset interrupt duration from the memory of the DMA channel to a memory area applied in advance by the processor according to the received two continuous interrupt signals; and the processor reads data corresponding to the preset packing time length in the memory area according to the received interrupt signal, wherein the ratio of the packing time length to the interrupt time length is a positive integer. In the invention, a DMA controller receives data sent by a PCM interface and sends an interrupt signal to a processor according to the received data quantity; the processor acquires an interrupt signal and acquires a pointer position of the data memory at a moment corresponding to the interrupt signal; copying data corresponding to preset interrupt duration from the memory without the cache of the DMA channel to the memory with the cache applied in advance by the processor according to the pointer positions respectively recorded by the interrupt signals; the processor reads data with a packing time length from the memory with the cache to the system memory for coding. In the opposite direction, the number of processors copies the decoded data from the system memory with the cache to the memory of the DMA channel without the cache according to the number of interrupt signals, so that the PCM read-write function operated by the processor reads the data from the memory with the cache, and the problem of unbalanced speed of the PCM read-write interface is solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a flowchart of a method for matching read-write rate of data transmission according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a system for matching data transmission read-write rate according to an embodiment of the present invention;
fig. 3 is an internal structure diagram of a computer device according to an embodiment of the present invention.
Detailed Description
In order to make the present invention better understood by those skilled in the art, the following description will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The inventors have found that the direction of PCM interface reading is writing data from DMA memory to system memory, the direction of PCM interface writing is writing data from system memory to DMA controller, the memory of DMA channel is uncached because system memory is cached, therefore the direction of PCM interface writing is writing data from cached memory (system memory) to uncached memory (DMA channel memory), the direction of PCM interface reading is writing data from uncached memory (DMA channel memory) to cached memory (system memory), the direction of PCM interface writing is data from cache, the direction of PCM interface reading is retrieving data from memory, and the speed of PCM interface reading is faster than the speed of PCM interface reading because the speed of PCM interface reading is much faster than the speed of PCM interface reading. According to the frame splitting algorithm, for each DSP channel, every time one byte is read and written, the pointer needs to jump downwards by 512 bytes, and when the packing time length is 20ms, one packing time length corresponds to 160 times of reading and writing operations, so that the problem of unbalanced speed of the PCM interface in the reading and writing direction is further worsened.
In order to solve the above problems, in the embodiment of the present invention, a DMA controller receives data sent by a PCM interface and sends an interrupt signal to a processor according to the received data; copying data corresponding to a preset interrupt duration from the memory of the DMA channel to a memory area applied in advance by the processor according to the received two continuous interrupt signals; and the processor reads data corresponding to the preset packing time length in the memory area according to the received interrupt signal, wherein the ratio of the packing time length to the interrupt time length is a positive integer. According to pointer positions respectively recorded by interrupt signals, copying data corresponding to preset interrupt duration from a memory without a cache of a DMA channel to a memory with a cache applied in advance; the processor reads data with a packing time length from the memory with the cache to the system memory for coding. In the opposite direction, the number of processors copies the decoded data from the system memory with the cache to the DMA channel memory without the cache according to the number of interrupt signals, so that the PCM read-write function operated by the processor reads the data from the memory with the cache, and the problem of unbalanced PCM read-write interface speed is solved.
Various non-limiting embodiments of the present invention are described in detail below with reference to the attached drawing figures.
Referring to fig. 1, a method for matching a read-write rate of data transmission according to a first embodiment of the present invention is shown, where the method includes:
s1, a DMA controller receives data sent by a PCM interface and sends an interrupt signal to a processor according to the data sent by the PCM interface.
In the embodiment of the invention, the DMA controller receives data sent by the PCM interface, under the normal working condition, the PCM interface continuously sends the data to the DMA controller, when the amount of the data sent by the PCM interface received by the DMA controller reaches the amount of the data corresponding to one interrupt duration, the DMA controller sends an interrupt signal to the processor once, namely, the DMA controller determines the time for sending the interrupt signal according to the received data amount, and sends the interrupt signal once every time the data amount received by the DMA controller reaches the data amount corresponding to one interrupt duration, wherein the preset interrupt duration can be 5ms, namely 40 frames, and the corresponding data amount is 40×512=20480 bytes.
And S2, copying data corresponding to a preset interrupt duration from the memory of the DMA channel to a memory area applied in advance by the processor according to the received two continuous interrupt signals, wherein the memory area is cached.
In the embodiment of the present invention, the DMA controller sends an interrupt signal, and for convenience of description, this interrupt signal is denoted as a first interrupt signal, and the second interrupt signal is the next interrupt signal sent by the DMA controller immediately after the first interrupt signal. Because each interrupt signal is sent when the DMA controller receives data corresponding to one interrupt duration, in theory, the time interval between the DMA controller sending the first interrupt signal and the second interrupt signal is one interrupt duration.
The processor copies the data corresponding to one interrupt duration from the memory of the DMA channel to a pre-applied memory area according to the received two continuous interrupt signals, the DMA channel is a channel for data reading and writing, the DMA channel is adopted, the processor reads the data sent by the PCM interface, and the processor writes the data into the PCM interface. In the prior art, the memory of the DMA channel is not provided with a cache, so that the processor needs to read the data of the memory of the DMA channel byte by byte, and the problem of unbalanced speed of the PCM interface in the reading and writing directions occurs; in the embodiment of the invention, the processor copies the data corresponding to one interrupt time length every time, the copying operation speed is high, and the time for transmitting the data in the reading direction is greatly reduced.
And S3, the processor reads data corresponding to the preset packing time length in the memory area according to the received interrupt signal, wherein the ratio of the packing time length to the interrupt time length is a positive integer.
In the embodiment of the invention, the processor reads data corresponding to a packing time length from a memory area with a cache every other packing time length, wherein the packing time length is different from an interrupt time length, and specifically, the interrupt time length is a preset numerical value multiple of the packing time length, and the preset numerical value is a positive integer. Therefore, the reading direction of the PCM interface is the direction that the processor reads data in the applied cache, the writing direction of the PCM interface is the direction that the data is written into the memory of the DMA channel from the cache, and the reading and writing directions of the PCM interface are all the directions that the data is read from the cache, so that the problem of unbalanced reading and writing speeds of the PCM interface is solved.
In order to further understand the technical solution of the embodiment of the present invention, before step S1, the method includes:
s01, pre-applying for a memory area with a cache of a preset size.
In the embodiment of the invention, the preset size is the memory size of the DMA channel, namely, a cached memory area which is the same as the memory size of the DMA channel without the cache is applied, the preset size is realized through an application function, the application function is provided with different marks, the different marks respectively correspond to the memories with different sizes, and the default applied memories are all cached.
S02, modifying the memory accessed by the read data into the memory area in advance.
The processor determines the address of the access memory by a software program, in the prior art, by the program: pucrxbuff=gucrxbuff+gulrxpos [ usActTs ]. Gw_tdm_max_slot_num+uloffset; the processor accesses the data in the gucRxBuff (i.e. the memory of the DMA channel), and in the embodiment of the invention, this line of program is modified as: pucrxbuff=guccachrxbuff+gulrxpos [ usActTs ]. Gw_tdm_max_slot_num+uloffset, the processor accesses the data of guccachaxbuff (i.e., memory region).
In the prior art, the processor accesses the memory of the DMA channel, in the embodiment of the present invention, step S01 has already applied for a memory to be cached, and then the memory of the DMA channel accessed by the original read data is modified to the memory area, so that the processor reads the data from the memory with the cache, and the speed of PCM reading the data is improved.
Next, the details of step S1 will be described, and specifically, step S1 includes:
and S11, transmitting an interrupt signal to the processor once when the DMA controller receives data corresponding to a preset interrupt duration transmitted by the PCM interface.
In the embodiment of the invention, the DMA controller sends an interrupt signal to the processor according to the data volume of the received data, and when the data volume received by the DMA controller reaches the data volume corresponding to one interrupt duration, the DMA controller sends an interrupt signal to the processor once.
Next, the details of step S2 will be described, and specifically, step S2 includes:
s21, the processor acquires pointer positions corresponding to the two continuous interrupt signals respectively according to the received two continuous interrupt signals.
In the embodiment of the invention, when the processor receives the first interrupt signal, the pointer position of the data memory is acquired at the moment of receiving the first interrupt signal and is recorded as the first pointer position; when the processor receives the second interrupt signal, the pointer position of the memory for receiving the data at the moment of receiving the second interrupt signal is acquired and recorded as the second pointer position.
Specifically, step S21 includes:
s211, when an Nth interrupt signal is received, acquiring an Nth pointer position, wherein N is a positive integer.
S212, when an N+1th interrupt signal is received, acquiring an N+1th pointer position, wherein the N+1th interrupt signal is the next interrupt signal of the received N-th interrupt signal.
In the embodiment of the invention, each time the processor receives an interrupt signal, a pointer position is obtained, the nth pointer position is the pointer position of the received data memory is read when the processor receives the nth interrupt signal, and the n+1th pointer position is the pointer position of the received data memory is read when the processor receives the n+1th interrupt signal.
For example, when N is equal to 1, the processor queries the pointer position of the received data memory as the 1 st pointer position when receiving the 1 st interrupt signal, may mark the 1 st pointer position as LastPos, and after an interrupt duration, the processor receives the 2 nd interrupt signal, and queries the pointer position of the received data memory as the 2 nd pointer position, may mark the 2 nd pointer position as CurrPos.
S22, the processor copies data corresponding to the preset interrupt duration from the memory of the DMA channel to a memory area applied in advance according to the pointer positions respectively corresponding to the two continuous interrupt signals.
In the embodiment of the invention, the memory area applied in advance is a memory area with a cache, and the size of the memory area is the same as the size of a memory without the cache of the DMA controller; after the DMA controller sends an interrupt signal, the DMA controller receives data corresponding to one interrupt time length and then sends the next interrupt signal, so that the data between the pointer positions corresponding to the two pointers respectively corresponds to the data of one interrupt time length, and the data corresponding to one interrupt time length can be copied to the memory area theoretically.
Specifically, step S22 specifically includes:
s221, copying the data between the N pointer position and the N+1 pointer position to the memory area, wherein the data between the N pointer position and the N+1 pointer position is the data corresponding to the interrupt duration.
In the embodiment of the present invention, in the above example, the data between the nth pointer position and the n+1th pointer position is the data between CurrPos and LastPos, and in theory, the data amount between CurrPos and LastPos is equal to the data amount corresponding to one interrupt duration. I.e. when data is copied from the DMA channel to the memory, the data quantity corresponding to one interrupt duration is copied at a time.
Next, the details of step S3 will be described, and step S3 includes:
s31, controlling a counter to be increased by 1 when the processor receives an interrupt signal;
s32, when the value of the counter reaches a preset value, reading data corresponding to a preset packing time length in the memory area, wherein the preset value is the ratio of the packing time length to the interrupt time length;
in the embodiment of the invention, the value of the counter represents the number of times that the processor copies data to the memory area after the processor acquires data corresponding to one package duration last time, for example, for the first time that the processor acquires data from the memory area, the value of the counter is 1, the processor copies data corresponding to one interrupt duration to the memory area again after the DMA controller receives data corresponding to one interrupt duration sent by the PCM interface, the ratio of the package duration to the interrupt duration is 4, namely, the preset value is 4, when the DMA controller receives data corresponding to one interrupt duration sent by the PCM interface, the first interrupt signal is sent to the processor, the value of the counter is increased by 1, when the DMA controller receives data corresponding to one interrupt duration sent by the PCM interface again, the counter is opposite to the second interrupt signal processor, and copies data corresponding to one interrupt duration to the memory area again, the counter is controlled to be increased by 1, at the moment, when the value of the counter reaches 4, the processor acquires data corresponding to one package duration from the memory area.
S33, the processor controls the counter to be cleared.
In the embodiment of the invention, when the value of the processor reaches the preset value, the processor is cleared, and it can be known that when the processor receives the interrupt signal next time, the value of the counter is 1, and the process is repeated in this way, and when the value of the counter reaches the preset value again, the processor acquires data corresponding to a packing duration from the memory area.
Based on the above method for matching the data transmission read-write rate, the embodiment of the invention also provides a system for matching the data transmission read-write rate, referring to fig. 2, the system comprises: a DMA controller 100 and a processor 200;
the DMA controller 100 is configured to receive data sent by the PCM interface, and send an interrupt signal to the processor according to the received data;
the processor 200 is configured to copy, according to the received two continuous interrupt signals, data corresponding to a preset interrupt duration from the memory of the DMA channel to a memory area applied in advance; the method comprises the steps of,
and the method is also used for reading data corresponding to the preset packing time length in the memory area according to the received interrupt signal, wherein the ratio of the packing time length to the interrupt time length is a positive integer.
Referring to fig. 3, a computer device provided in an embodiment of the present invention is shown, where the device may be a terminal, and an internal structure of the device is shown in fig. 3. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of data transmission read-write rate matching. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It will be appreciated by those skilled in the art that the block diagram of fig. 3 is merely a partial structure related to the present application and does not constitute a limitation of the computer device to which the present application is applied, and that a specific computer device may include more or less components than those shown in the drawings, or may combine some components, or have a different arrangement of components.
An embodiment of the present invention provides a computer device, including a memory and a processor, where the memory stores a computer program, and the processor executes the computer program to implement the following steps:
the DMA controller receives the data sent by the PCM interface and sends an interrupt signal to the processor according to the received data;
copying data corresponding to a preset interrupt duration from the memory of the DMA channel to a memory area applied in advance by the processor according to the received two continuous interrupt signals;
and the processor reads data corresponding to the preset packing time length in the memory area according to the received interrupt signal, wherein the ratio of the packing time length to the interrupt time length is a positive integer.
The embodiment of the invention also provides a computer readable storage medium, on which a computer program is stored, characterized in that the computer program when executed by a processor realizes the following steps:
the DMA controller receives the data sent by the PCM interface and sends an interrupt signal to the processor according to the received data;
copying data corresponding to a preset interrupt duration from the memory of the DMA channel to a memory area applied in advance by the processor according to the received two continuous interrupt signals;
and the processor reads data corresponding to the preset packing time length in the memory area according to the received interrupt signal, wherein the ratio of the packing time length to the interrupt time length is a positive integer.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (10)
1. A method for data transmission read-write rate matching, the method comprising:
the DMA controller receives the data sent by the PCM interface and sends an interrupt signal to the processor according to the received data;
copying data corresponding to preset interrupt duration from a memory of a DMA channel to a memory area applied in advance by a processor according to the received two continuous interrupt signals, wherein the memory area is cached;
and the processor reads data corresponding to the preset packing time length in the memory area according to the received interrupt signal, wherein the ratio of the packing time length to the interrupt time length is a positive integer.
2. The method of claim 1, wherein the DMA controller receives data transmitted from the PCM interface and transmits an interrupt signal to the processor according to the received data, comprising:
and each time the DMA controller receives data corresponding to a preset interrupt duration sent by the PCM interface, sending an interrupt signal to the processor.
3. The method of claim 1, wherein the processor copies data corresponding to a preset interrupt duration from the memory of the DMA channel to the pre-applied memory area according to the received two consecutive interrupt signals, comprising:
the processor acquires pointer positions corresponding to the two continuous interrupt signals respectively according to the received two continuous interrupt signals;
and the processor copies the data corresponding to the preset interrupt duration from the memory of the DMA channel to the memory area applied in advance according to the pointer positions respectively corresponding to the two continuous interrupt signals.
4. A method according to claim 3, wherein the processor obtaining pointer positions corresponding to two consecutive interrupt signals respectively according to the received two consecutive interrupt signals comprises:
when the processor receives an Nth interrupt signal, acquiring an Nth pointer position, wherein N is a positive integer;
and when the processor receives the (N+1) th interrupt signal, acquiring the (N+1) th pointer position, wherein the (N+1) th interrupt signal is the next interrupt signal of the received (N) th interrupt signal.
5. The method according to claim 4, wherein the processor copies the data corresponding to the preset interrupt duration from the memory of the DMA channel to the memory area applied in advance according to the received two continuous interrupt signals, specifically:
the processor copies the data between the N pointer position and the N+1 pointer position to the memory area, wherein the data between the N pointer position and the N+1 pointer position is the data corresponding to the interrupt duration.
6. The method of claim 1, wherein the processor reads data corresponding to a preset packing duration in the memory area according to the received interrupt signal, including:
each time the processor receives an interrupt signal, the counter is controlled to be increased by 1;
when the value of the counter reaches a preset value, the processor reads data corresponding to a preset packing time length in the memory area, wherein the preset value is the ratio of the packing time length to the interrupt time length;
the processor controls the counter to zero.
7. The method of claim 1, wherein before the DMA controller receives the data sent by the PCM interface, further comprising:
applying for a memory area with a cache in a preset size in advance;
and modifying the memory accessed by the read data into the memory area.
8. A system for data transmission read-write rate matching, the data transmission system comprising: a DMA controller and a processor;
the DMA controller is used for receiving the data sent by the PCM interface and sending an interrupt signal to the processor according to the received data;
the processor is used for copying data corresponding to preset interrupt duration from the memory of the DMA channel to a memory area applied in advance according to the received two continuous interrupt signals; the method comprises the steps of,
and the method is also used for reading data corresponding to the preset packing time length in the memory area according to the received interrupt signal, wherein the ratio of the packing time length to the interrupt time length is a positive integer.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 7 when the computer program is executed.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method according to any one of claims 1 to 7.
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| CN102567256A (en) * | 2011-12-16 | 2012-07-11 | 龙芯中科技术有限公司 | Processor system, as well as multi-channel memory copying DMA accelerator and method thereof |
| CN107943726A (en) * | 2017-11-16 | 2018-04-20 | 郑州云海信息技术有限公司 | A kind of data transmission system and method based on PCIe interface |
| CN110059042A (en) * | 2019-04-30 | 2019-07-26 | 成都启英泰伦科技有限公司 | A kind of data DMA transfer method of UART equipment |
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| CN102567256A (en) * | 2011-12-16 | 2012-07-11 | 龙芯中科技术有限公司 | Processor system, as well as multi-channel memory copying DMA accelerator and method thereof |
| CN107943726A (en) * | 2017-11-16 | 2018-04-20 | 郑州云海信息技术有限公司 | A kind of data transmission system and method based on PCIe interface |
| CN110059042A (en) * | 2019-04-30 | 2019-07-26 | 成都启英泰伦科技有限公司 | A kind of data DMA transfer method of UART equipment |
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