CN115757210A

CN115757210A - Address access method, device and system

Info

Publication number: CN115757210A
Application number: CN202211627093.1A
Authority: CN
Inventors: 徐润生; 朱艳青
Original assignee: Sundak Semiconductor Technology Shanghai Co ltd
Current assignee: Sundak Semiconductor Technology Shanghai Co ltd
Priority date: 2022-12-16
Filing date: 2022-12-16
Publication date: 2023-03-07

Abstract

The invention relates to an address access method, a device and a system, wherein the method comprises a read operation and a write operation, wherein the read operation comprises the mapping of similar registers of all modules in an equipment end to the same address segment; after a real read instruction for accessing the address is received, accessing the whole address space through a block read to acquire data of the similar registers of all the modules; sending the data to a host end; the write operation includes encoding all write operations into a data format of instruction + operand; the host side stores a plurality of pieces of write operation data into a data block and writes the data block into the equipment side at one time; the device end only decodes the data one by one, distributes the write operation to different modules according to the instruction to carry out parallel addressing registers, and synchronously writes the corresponding operand into the corresponding register. The invention adopts the methods of block reading and parallel writing to the register, and obviously improves the execution efficiency of the bus accessing the register on the basis of utilizing the bus bandwidth as high as possible.

Description

Address access method, device and system

Technical Field

The present invention relates to the field of cache management technologies, and in particular, to a method, an apparatus, and a system for address access.

Background

In the application of computer control electronic equipment, with the increasing performance of computers and electronic equipment, the amount of information to be processed is increasing, and therefore the performance requirements of buses interconnecting the computers and the equipment are also increasing. Electronic intelligent equipment usually encapsulates control interfaces of various internal functions into registers, maps all the registers to an address space according to a data-address coding rule, and a computer addresses and accesses the registers through a bus, so how to fully utilize the bus bandwidth to improve the register access efficiency is an important ring in data transmission.

The bus is a common data channel for realizing information transmission and data exchange between the host and the device. When data is transmitted, the bandwidth of the bus directly affects the transmission efficiency of data communication. Therefore, bus technology with higher and higher bandwidth continuously appears in the market, the advantage of the high-bandwidth bus is beneficial to storage devices such as U disks and hard disks and streaming media devices, the data of the device end is a whole block of data which is continuously stored, when the bus accesses the data, a large amount of data can be continuously accessed only by appointing the first address of a data block once, and the bandwidth can be fully utilized. Although the increase of the bandwidth obviously improves the transmission efficiency of the large-block data, the speed of single transmission of a single data is not obviously improved, namely, the access of a single small data volume cannot fully utilize the advantage of the bus bandwidth. The data of some electronic devices is composed of a large number of identical or similar modules, identical register structures are arranged in the modules, and a computer needs to synchronously control the modules to work in parallel, so that all registers of all the modules need to be accessed through a bus. Such devices, unlike memory devices, are relatively independent of register function and often require access to certain specified registers during operation. At present, the conventional method for mapping all registers to an address space is shown in fig. 1, where registers are mapped to an address space, all registers in each module are allocated to adjacent addresses, the registers of the adjacent addresses correspond to different functions, and the addresses at the upper level are expanded according to multiple modules. For example, a device contains M identical modules, and registers contained in the modules are of the same type, which requires access to the same type of registers in multiple modules. When the device under the environment is accessed by using the traditional method, the read operation of jumping addresses is needed when the read operation is executed, and the write operation of jumping addresses is needed when the write operation is executed; therefore, when the device needs concurrent operation of multiple modules, data processing can be performed only in a small-block fragmentation mode, although the bandwidth of a transmission bus is very large, register access of jump addresses needs to be performed for multiple times, and only one address can be accessed each time.

It is therefore desirable to provide a technique that improves the efficiency of bus address space access.

Disclosure of Invention

Therefore, the technical problem to be solved by the present invention is to overcome the technical defects existing in the prior art that address access is inefficient and cannot embody the advantage of high bandwidth.

In order to solve the above technical problem, the present invention provides an address access method, including a read operation, where the read operation is accessed according to a register address, and the read operation includes:

mapping the same type registers of all modules in the equipment end to the same address field with continuous addresses;

after receiving a real read instruction for accessing the address by the host terminal, the equipment terminal accesses the whole address space by block read to acquire data of the similar registers of all the modules;

and sending the data to a host side.

In an embodiment of the present invention, before the host side initiates a real read instruction for accessing the address, the host side initiates a pre-read instruction for accessing the address, and after receiving the pre-read instruction, the device side pre-caches data of the address in the register interface.

In an embodiment of the present invention, when a read operation is performed on a plurality of modules of the same type of register, the host sends the pre-read instruction to the plurality of modules simultaneously.

The invention also provides an address access method, which comprises a write operation, wherein the write operation comprises the following steps:

all write operations are encoded into a data format of an instruction and an operand, and address information is not carried;

the host end stores a plurality of pieces of continuously executed write operation data into a data block and writes the data block into the equipment end once;

after receiving the write data block from the host end, the device end ignores the address information of the write operation, decodes the data one by one, distributes the write operation to different modules according to the instruction in the data to perform parallel addressing register, and synchronously writes the corresponding operand into the corresponding register.

In an embodiment of the present invention, when write operations are performed on a plurality of registers of the same type, the host initiates an enumeration instruction, the device selects a module that needs to perform register write operations after receiving the enumeration instruction, and other modules enter an unselected mode and apply the write operations to all modules in the selected mode.

In one embodiment of the invention, all modules in the selected mode perform write operations synchronously.

The invention also provides an address access method, which comprises a read operation and a write operation,

the read operation comprises:

mapping the same type registers of all modules in the equipment end to the same address segment with continuous addresses;

after receiving a real read instruction for accessing the address by the host terminal, the equipment terminal accesses the whole address space by block read to acquire data of the similar registers of all the modules; and sending the data to a host side;

the write operation includes:

the host end stores a plurality of pieces of continuously executed write operation data into a data block and writes the data block into the equipment end at one time;

The present invention also provides a read operation device, comprising:

the address mapping module is used for mapping the same type registers of all modules in the equipment end to the same address field with continuous addresses;

the read operation module is used for accessing the whole address space by the equipment end through the block read after receiving a real read instruction for accessing the address by the host end, and acquiring data of the similar registers of all the modules;

and the data sending module is used for sending the data to the host side.

The present invention also provides a write operation apparatus comprising:

the encoding module is used for encoding all write operations into a data format of an instruction and an operand, and does not carry address information;

the write operation module is used for storing a plurality of pieces of write operation data which are continuously executed into a data block by the host end and writing the data block into the equipment end at one time;

the decoding module is used for neglecting the address information of the write operation after the device end receives the write data block of the host end, only decoding the data one by one, distributing the write operation to different modules according to the instruction in the data to carry out parallel addressing registers, and synchronously writing the corresponding operand into the corresponding register.

The present invention also provides an address access system, comprising:

the read operation device is used for mapping the same type registers of all modules in the equipment end to the same address field with continuous addresses; after receiving a real read instruction for accessing the address by the host terminal, the equipment terminal accesses the whole address space by block read to acquire data of the similar registers of all the modules; sending the data to a host end;

the write operation device is used for encoding all write operations into a data format of an instruction and an operand and does not carry address information; the host end stores a plurality of pieces of continuously executed write operation data into a data block and writes the data block into the equipment end once; after receiving the write data block from the host end, the device end ignores the address information of the write operation, only decodes the data one by one, distributes the write operation to different modules according to the instruction in the data to carry out parallel addressing registers, and synchronously writes the corresponding operand into the corresponding register.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the address access method, the device and the system, the register is subjected to block reading and parallel writing, the execution efficiency of the bus access register is obviously improved on the basis of utilizing the bus bandwidth as high as possible, and the problems that the address access is low in efficiency and cannot embody the advantage of high bandwidth in the prior art are solved.

Drawings

In order that the present disclosure may be more readily understood, a more particular description of the disclosure will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings

FIG. 1 is a diagram illustrating address allocation for a read operation in the prior art.

FIG. 2 is a flow chart of a read operation proposed by the present invention.

FIG. 3 is a diagram illustrating address allocation for a read operation according to the present invention.

Fig. 4 is a flow chart of a write operation proposed by the present invention.

Fig. 5 is a schematic diagram of a write operation proposed by the present invention.

FIG. 6 is a diagram illustrating a write operation of a load enumerate instruction according to the present invention.

FIG. 7 is a diagram illustrating simultaneous write operations to the registers of N modules according to the present invention.

FIG. 8 is a diagram illustrating data transmission after an enumerate instruction is introduced.

Fig. 9 is a schematic structural diagram of a read operation device according to the present invention.

Fig. 10 is a schematic structural diagram of a write operation device according to the present invention.

Wherein the reference numerals are as follows: 11. an address mapping module; 12. a read operation module; 13. a data transmission module; 21. an encoding module; 22. a write operation module; 23. and a decoding module.

Detailed Description

The present invention is further described below in conjunction with the following figures and specific examples so that those skilled in the art may better understand the present invention and practice it, but the examples are not intended to limit the present invention.

Referring to fig. 2, an embodiment of the present invention provides an address access method, which includes a read operation and a write operation, and significantly improves the execution efficiency of the bus access register on the basis of using the bus bandwidth as efficiently as possible by using a block read and parallel write method for the register.

Wherein the read operation is accessed according to a register address, the method of the read operation comprising the steps of:

s101: mapping the same type registers of all modules in the equipment end to the same address field with continuous addresses;

s102: after receiving a real read instruction for accessing the address by the host end, the equipment end accesses the whole address space through the block read to obtain data of the similar registers of all the modules;

s103: and sending the data to a host end.

Specifically, when the read operation needs to access the similar registers of multiple modules, the similar registers of all the modules are mapped to adjacent addresses, that is, all the similar registers are distributed on the same address segment with continuous addresses; the registers of different types are distributed to different address segments, and the address distribution of different registers in the same module is discontinuous and is positioned on different address segments. As shown in fig. 3, 1 in REG1_ [0] in the drawing indicates a register type number, 0 indicates a module number included in device, and M identical modules are included in device, when accessing homogeneous registers of each module, since the homogeneous registers of each module are allocated with adjacent addresses, the entire address space can be accessed through block read, values of the homogeneous registers in all modules can be obtained, and instructions or data with M × w bits can be read in one access cycle according to the addresses. Therefore, the addressing access efficiency of the similar registers is obviously improved, the phenomenon of 'no waiting' of the registers caused by the traditional method is avoided, the execution time is obviously reduced, the bandwidth of the bus can be fully utilized on the premise of not changing the access cycle of each module, and the reading efficiency of the similar registers in each module is obviously improved.

Also, for some registers where read operations would otherwise reflect a slower speed, a read-ahead instruction may be issued prior to the read operation. That is, the read operation received by the device end includes an actual read instruction and a pre-read instruction, the actual read instruction is a read operation initiated on the bus by the host end, and the device end immediately returns the specified data to the bus. The read-ahead instruction is actually a write operation, and the address information of the register to be read is written into the read-ahead module and responds to the register. That is, before the host initiates a real read instruction for accessing the address, the host initiates a pre-read instruction for accessing the address, and after receiving the pre-read instruction, the device executes a relatively time-consuming read operation inside, and pre-caches data of the address in a register interface. When the real read instruction aiming at the register is initiated, the cached data can be directly returned to the host end, so that the access speed of the bus is not slowed down. Meanwhile, a pre-reading instruction can be simultaneously sent to a plurality of modules in parallel to trigger pre-reading processing of the registers of the same type in the modules, and the optimization scheme of address allocation of the registers is combined, the whole address space is continuously accessed through a real-reading instruction, so that the values of the registers of the same type of all the modules can be directly obtained, the advantages of block read are fully exerted, and the problem of block read block caused by waiting before reading of each channel is effectively solved.

Referring to fig. 4, the method of writing operation includes the following steps:

s201: all write operations are encoded into a data format of an instruction and an operand, and address information is not carried;

s202: the host end stores a plurality of pieces of continuously executed write operation data into a data block and writes the data block into the equipment end once;

s203: after receiving the write data block from the host end, the device end ignores the address information of the write operation, only decodes the data one by one, distributes the write operation to different modules according to the instruction in the data to carry out parallel addressing registers, and synchronously writes the corresponding operand into the corresponding register.

Specifically, the above-mentioned write operation determines the access of the register according to the specific data content during data transmission, and the operation of the specific register is realized by encoding the write data format, and the encoding information includes "instruction + operand" information. The instruction represents register type information, namely, the address information originally equivalent to registers of different types is coded in the instruction; the operand refers to data written to the register.

When a certain register is written, the host end combines the coding information of the register address and the data required to be written into the register into a data format of 'instruction + operand', the data is transmitted through the bus, and the equipment end addresses the register according to the 'instruction' information in the data and writes the 'operand'.

Referring to fig. 5, when a plurality of heterogeneous registers at the device side need to perform write operations continuously, the host side encodes each write operation into a data format of "instruction + operand", and puts it into the storage register in advance for continuously storing all data of write operation information to be pieced into a data block, and then transmits the value in the storage register as one data block through the BUS. When the device side receives the write operation of the bus, the write operation is distributed to different modules to carry out parallel addressing registers according to the instruction in the data block, and the corresponding operand is synchronously written into the corresponding register. This mechanism allows the bus bandwidth to be fully utilized for concurrent writing of heterogeneous registers at the host side in a continuous data operation, even though the registers are not stored continuously at the device side.

Referring to fig. 6, when write operations are performed on a plurality of registers of the same type, a host initiates an enumeration instruction, after receiving the enumeration instruction, a device selects a module that needs to perform register write operations, and other modules enter an unselected mode and apply the write operations to all modules in the selected mode. Enabling the selected module to enter a selected mode and other modules to enter unselected modes through an enumerating instruction; after the enumeration instruction is sent, subsequent register write operations will simultaneously act on all modules in the selected mode without affecting the register states of all modules in the unselected mode. And all modules in the selected mode can implement synchronicity actions at the instruction level. Illustratively, operand 0 is written into registers 0 of all selected modules simultaneously, so that the data volume during write operation is reduced, the write operation speed is increased, the write efficiency of a plurality of similar registers is improved, and the parallel operation of the similar registers in the modules is realized.

As shown in fig. 7, under the condition that the device contains a large number of identical modules, the register parallel write-in method is adopted, the data block composed of the command and the operand is used for writing different types of registers (REG 0, REG1, \8230;, REGN) in parallel, and the commands are listed for accessing the same type of registers in a plurality of modules in parallel, so that the write operation time is obviously reduced, the data block is efficiently transmitted by utilizing the advantage of high bandwidth of the bus to perform the write operation of the registers, the transmission of redundant data blocks is avoided, the write operation efficiency is obviously improved, and the execution efficiency of the system is greatly improved.

As shown in fig. 8, the corresponding register REG0 is selected according to the selected module, and the DATA0 is synchronously written into each register REG0, so that the function of parallel writing of multiple registers is realized, and the work of repeating the writing operation N times in the conventional method can be completed by one writing operation. It can be seen that the enumerate instruction not only simplifies the operand, but also greatly reduces the occupation of bandwidth, and especially in the case of a large number of identical modules inside the device, the more identical modules are included in the device (the more registers of the same type), the more significant the advantage is.

Corresponding to the embodiment of the foregoing method, as shown in fig. 9, an embodiment of the present invention further provides a read operation apparatus, including:

the address mapping module 11 is used for mapping the same type registers of all modules inside the equipment end to the same address field with continuous addresses;

the read operation module 12 is configured to, after receiving a real read instruction for the host to access the address, access the entire address space by the device side through the block read, and acquire data of the similar registers of all the modules;

a data sending module 13, configured to send the data to a host.

As shown in fig. 10, an embodiment of the present invention further provides a write operation apparatus, including:

the encoding module 21 is configured to encode all write operations into a data format of an instruction + operand, and does not carry address information;

a write operation module 22 for storing a plurality of pieces of write operation data continuously executed as a data block by the host side and writing the data block to the device side at one time;

the decoding module 23 is configured to ignore address information of the write operation after the device side receives the write data block from the host side, decode the data one by one, distribute the write operation to different modules according to an instruction in the data to perform parallel addressing on a register, and synchronously write a corresponding operand into a corresponding register.

Corresponding to the embodiment of the foregoing apparatus, an embodiment of the present invention further provides an address access system, including:

the write operation device is used for encoding all write operations into a data format of an instruction and an operand and does not carry address information; the host end stores a plurality of pieces of continuously executed write operation data into a data block and writes the data block into the equipment end at one time; after receiving the write data block from the host end, the device end ignores the address information of the write operation, only decodes the data one by one, distributes the write operation to different modules according to the instruction in the data to carry out parallel addressing registers, and synchronously writes the corresponding operand into the corresponding register.

The address access system of the present embodiment is used to implement the foregoing address access system method, and therefore, a detailed implementation of the system may be found in the foregoing embodiment section of the address access method, and therefore, the detailed implementation of the system may refer to the description of the corresponding respective embodiment section, and is not described here again.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the spirit or scope of the invention.

Claims

1. An address access method, the method comprising a read operation, the read operation accessed according to a register address, characterized by: the read operation comprises:

and sending the data to a host side.

2. An address access method as claimed in claim 1, wherein: before the host side initiates an actual reading instruction for accessing the address, the host side initiates a pre-reading instruction for accessing the address, and after receiving the pre-reading instruction, the equipment side pre-caches data of the address in a register interface.

3. An address access method as claimed in claim 2, wherein: when the read operation is executed to the registers of the same type of a plurality of modules, the host side sends the pre-read instruction to the modules simultaneously.

4. An address access method, the method comprising a write operation, characterized by: the write operation includes:

after receiving the write data block from the host end, the device end ignores the address information of the write operation, only decodes the data one by one, distributes the write operation to different modules according to the instruction in the data to carry out parallel addressing registers, and synchronously writes the corresponding operand into the corresponding register.

5. An address access method as claimed in claim 4, wherein: when write operation is executed on a plurality of similar registers, the host end initiates an enumeration instruction, the device end selects a module needing to execute register write operation after receiving the enumeration instruction, and other modules enter an unselected mode and act subsequent write operation on all modules in the selected mode.

6. An address access method as claimed in claim 5, wherein: all modules in the selected mode synchronously perform write operations.

7. An address access method, the method comprising a read operation and a write operation, characterized by:

the read operation comprises:

the write operation includes:

all write operations are encoded into a data format of instruction + operand, and address information is not carried;

8. A read operation device, characterized by: the method comprises the following steps:

and the data sending module is used for sending the data to the host side.

9. A write operation apparatus characterized by: the method comprises the following steps:

10. An address access system, characterized by: the method comprises the following steps:

the write operation device is used for encoding all write operations into a data format of an instruction and an operand and does not carry address information; the host end stores a plurality of pieces of continuously executed write operation data into a data block and writes the data block into the equipment end at one time; after receiving the write data block from the host end, the device end ignores the address information of the write operation, decodes the data one by one, distributes the write operation to different modules according to the instruction in the data to perform parallel addressing register, and synchronously writes the corresponding operand into the corresponding register.