CN108388529B

CN108388529B - Method for actively realizing data exchange between peripheral and CPU

Info

Publication number: CN108388529B
Application number: CN201810078793.7A
Authority: CN
Inventors: 郑容�; 王晓斌; 陈伯芳; 袁成伟; 詹万鹏; 危必波
Original assignee: Wuhan Zhongyuan Huadian Electric Power Equipment Co ltd
Current assignee: Wuhan Zhongyuan Huadian Electric Power Equipment Co ltd
Priority date: 2018-01-26
Filing date: 2018-01-26
Publication date: 2021-03-09
Anticipated expiration: 2038-01-26
Also published as: CN108388529A

Abstract

The invention relates to a method for realizing data exchange between a peripheral and a CPU (central processing unit) actively, which is used for realizing data communication between the CPU and the peripheral quickly based on a PCIE + DMA (peripheral component interface express) framework, wherein the peripheral actively reads and writes a circulating memory, ensures the transmission reliability by using a cell calculation strategy, actively initiates interruption to the CPU and informs the CPU to operate the memory, and the CPU does not need to participate in address management and transmission control and only needs to access memory data according to the interruption information of the peripheral. The method can be used in occasions where the CPU load is expected to be reduced and the peripheral actively completes the memory read-write operation.

Description

Method for actively realizing data exchange between peripheral and CPU

Technical Field

The invention relates to a method for actively realizing data exchange between a peripheral and a CPU (central processing unit), which is used for occasions where the load of the CPU is expected to be reduced and the peripheral actively finishes the read-write operation of a memory.

Background

The peripheral equipment is hardware equipment connected to the outside of the computer host. The functions of transmitting, transferring and storing data and information are important components in computer systems. In a conventional peripheral and CPU data interaction system, even if a direct memory DMA mode is used to access data, a CPU needs to issue control information such as a request address, a length, a type, and the like to the peripheral, and when DMA access of large-traffic data is performed, a large amount of CPU resources need to be occupied to process interaction of the control information, which increases the burden of the CPU.

Disclosure of Invention

The invention aims to reduce the load of a CPU (Central processing Unit) when DMA (direct memory Access) of large-flow data is carried out, and provides a method for actively realizing data exchange between the Peripheral and the CPU. The method can be used in occasions where the CPU load is expected to be reduced and the peripheral actively completes the memory read-write operation.

The technical scheme of the invention is as follows:

a method for realizing data exchange between peripheral equipment and a CPU actively comprises a PCIE + DMA framework, wherein the DMA has the functions of realizing address maintenance, interrupt generation, message generation, read-write command generation, read-return data sorting and cell management actively; the method is characterized by comprising the following steps:

(1) in the initialization process, a fixed continuous cache space is distributed by a CPU to an external device for circularly reading and writing data, the continuous cache space is divided into a plurality of small cache spaces with equal length, and the initial address of the continuous cache space and the length of the small cache spaces are informed to the external device in a parameter configuration mode, so that the address of each data message to be processed is fixed when the external device performs data reading and writing operation; the small cache spaces with continuous equal length form a read/write cycle storage structure;

(2) when the peripheral equipment needs to write data into the memory, the peripheral equipment carries out incremental cyclic numbering on each message, a number value representing a message serial number is embedded into access data, meanwhile, according to an address calculated by a write cyclic storage structure, when a write cell condition calculated by the peripheral equipment is met, a DMA write request operation is initiated to a current address of the calculated cyclic storage structure, a DMA write cell mechanism ensures that the DMA write operation to be initiated does not cover the existing data which is not processed by the CPU, in the DMA write request operation process, the number and time of the written messages are counted, when the access number or an overtime condition is met, the peripheral equipment needs to write message messages into the fixed message memory and initiate interrupt messages to the CPU, after the CPU receives the interrupt messages, the content of the message is read, and the memory is managed according to the content of the message messages;

(3) when the peripheral needs to read data from the memory, whether to initiate a read request is determined according to a read cell calculated by the peripheral, and the DMA read cell comprises two cells, namely a data receiving cell and a read request initiating cell; the request can be initiated when both cells are satisfied, then DMA read request operation is initiated to the current address of the read cycle storage structure according to the address calculated by the read cycle storage structure, and the peripheral cell mechanism ensures that enough space is provided for receiving read response data; counting the number and time of read messages in the process of DMA reading request operation, when the number of received packets or overtime conditions are met, initiating a message to a fixed message memory and initiating an interrupt message to a CPU, and updating and releasing memory space after the CPU receives the interrupt message.

The parameters in the step (1) comprise: the starting address of the continuous cache corresponding to the write operation, the data block size of the continuous cache corresponding to the write operation, the data block number of the continuous cache corresponding to the write operation, the starting address of the continuous cache corresponding to the read operation, the data block size of the continuous cache corresponding to the read operation and the data block number of the continuous cache corresponding to the read operation.

And (3) the DMA write request operation in the step (2) is the initial address of the data block in the continuous cache corresponding to the write operation.

The DMA read request operation in the step (3) is the starting address of the data block in the continuous cache corresponding to the read operation.

The starting addresses of the continuous cache data blocks corresponding to the read/write operation are all as follows: adding the length of the data block from the initial address of the last immediately adjacent data block, namely accumulating the length of the data block from the base address to form the initial address of the subsequent data block, and taking care that the address returns to zero after the number of the data blocks is reached.

The DMA write unit mechanism: the peripheral equipment carries out cycle counting on the frames written into the memory; meanwhile, the CPU carries out cycle counting on the frames in the processed memory and sends the cycle counting of the processed frames to the peripheral at fixed time; the peripheral equipment subtracts the cycle count corresponding to the current write-in frame from the cycle count of the processed frame issued by the latest CPU, considers that the cell condition is satisfied when the difference value is less than the number of data blocks of the cycle cache corresponding to the write operation, and initiates the current DMA write operation; otherwise, the CPU is required to wait for processing the memory frame, the processed cycle count value of the CPU is updated, and the current DMA write operation can be initiated only after the cell condition is established.

The DMA read cell includes two types of cells: receiving a data cell and initiating a read request cell;

receiving data cells to ensure that the peripheral has enough space to receive read response data, and a calculation mechanism: receiving a data cell, wherein half of the buffer size of the DMA return data stored outside the data cell is an initial value, reducing the data length corresponding to the read request of the data cell when the DMA read request is initiated, and adding the delivered data length to the received data cell when the DMA read response data is received and delivered; if the current calculated received data cell is greater than 0, the cell condition is considered to be established;

initiating a read request cell to ensure that an address of an upcoming read request contains valid readable data, the computing mechanism: the peripheral equipment carries out cycle counting on the frame initiating the reading of the memory, and meanwhile, the CPU carries out cycle counting on the frame written into the memory and sends the cycle counting of the frame written into the memory to the peripheral equipment at regular time. The peripheral device subtracts the cycle count of the written frame issued by the latest CPU and the cycle count of the current frame to be started to read the memory, and when the difference value is greater than 0, the cell condition is considered to be satisfied;

when the memory read operation needs to be initiated each time, the DMA read operation can be initiated only when the data cell needs to be received and the cell for initiating the read request is satisfied simultaneously.

In the step (2), when the peripheral needs to write data into the memory, and when the access quantity or the timeout condition is met, the peripheral needs to write a message into the fixed message memory, and initiate an interrupt message to the CPU, the specific steps are as follows:

in each period, starting from the initiation of a first write request, simultaneously counting the write requests and time, triggering interruption when the request count reaches a threshold or the time count reaches the threshold, starting a new period, resetting both the request count and the time count, starting a new request and the time count from the initiation of the first write request in the new period, and triggering interruption and repeating the steps when at least one of the request and the time count reaches the threshold;

after the interruption is triggered, firstly generating a message carrying the number of the initiated writing request packets, and then generating an interruption message; after receiving the interrupt message, the CPU reads the message first to learn how many memory blocks can be processed, and then processes the data of the corresponding memory.

In the step (3), when the peripheral needs to read data from the memory, and when the number of received packets or the timeout condition is met, a message needs to be initiated to the fixed message memory, and an interrupt message is initiated to the CPU, the specific steps are as follows:

in each period, starting from the reception of a first frame of read response, counting responses and time at the same time, triggering interruption when the response count reaches a threshold or the time count reaches the threshold, starting a new cycle of period, resetting both the response count and the time count, starting a new cycle of response and time count from the reception of the first read response in the new cycle, and triggering interruption and repeating the cycle when at least one of the response count and the time count reaches the threshold;

after the interruption is triggered, firstly generating a message carrying the number of the received and read response packets, and then generating an interruption message; after receiving the interrupt message, the CPU accesses the message in the message to obtain the data of how many memory blocks have been read, and then processes the data of the corresponding memory blocks.

In the method, the CPU does not need to configure access address, length or other control information and does not need to track the access condition of the peripheral to the memory in real time. The peripheral actively initiates a read-write request according to the appointed cyclic address, the access length and the internal cell amount, actively initiates an interrupt message to the CPU when the request reaches a certain amount or is overtime, and simultaneously writes the current number of the processed messages into a message cache in a message form. The CPU only needs to manage the memory according to the control information of the message cache after receiving the interrupt message, thereby reducing the expense of the CPU to the maximum extent.

The advantages of the invention are as follows: 1, a continuous cache space of a continuous interval is adopted, the continuous cache space is divided into read/write circulating storage structures with equal length, and the starting addresses of the read/write circulating storage structures are aligned by 128 bytes, so that the control of peripheral equipment on an internal memory is simplified; 2. the peripheral actively completes read-write requests without excessive participation of a CPU; 3. and the peripheral equipment maintains cells, controls the request frequency and ensures the design reliability.

Drawings

Fig. 1 is a block diagram of a simple DMA internal implementation of the present invention.

FIG. 2 is a block diagram of a circular cache data block according to the present invention.

Detailed Description

The technical solution of the present invention is further elaborated below.

As shown in fig. 1, the method specifically includes the following steps:

the first step is as follows: determining parameters of a memory address, fixing the parameters in the peripheral, and comprising the following parameters:

the starting address of the contiguous memory accessed by a DMA write operation is approximately 128 bytes aligned, the starting address of the write, also referred to as the BASE address, denoted WR _ BASE _ ADDR.

2. The continuous write memory is divided into equal-length data BLOCKs, and each BLOCK stores one frame of data, so that the length of the data frame is less than or equal to the size of the data BLOCK, and the length is expressed as WR _ BLOCK _ LEN.

3. The number of data BLOCKs included in the continuous write memory is denoted as WR _ BLOCK _ NUM.

The starting address of the contiguous memory accessed by the DMA read operation is approximately 128 bytes aligned, and the starting address of the read is also referred to as the BASE address, which is denoted as RD _ BASE _ ADDR.

5. The continuous read memory is divided into data BLOCKs with equal length, and each BLOCK stores one frame of data, so that the length of the data frame is less than or equal to the size of the data BLOCK, and the length is represented as RD _ BLOCK _ LEN.

6. The continuous read memory includes the number of data BLOCKs, denoted as RD _ BLOCK _ NUM.

Although the locations of the consecutive caches corresponding to the read/write operations are different, the structures of the two caches are shown in fig. 2.

When caching is continued for write operations, the base addresses in FIG. 2 are: WR _ BASE _ ADDR; m is WR _ BLOCK _ LEN, and n is WR _ BLOCK _ NUM.

When caching is continued for read operations, the base addresses in FIG. 2 are: RD _ BASE _ ADDR; m is RD _ BLOCK _ LEN, and n is RD _ BLOCK _ NUM.

The second step is that: according to the relevant parameters of the memory address, the address is circularly increased when a DMA read/write request is sent once. The rules are as follows:

the structure of the circular block cache data block is shown in fig. 2:

DMA write request addresses start with WR _ BASE _ ADDR, next frame address adds WR _ BLOCK _ LEN on top of the previous frame address, and the address increments up to WR _ BASE _ ADDR + WR _ BLOCK _ LEN x (WR _ BLOCK _ NUM-1) back to WR _ BASE _ ADDR.

DMA read request addresses start with RD _ BASE _ ADDR, the next frame address adds RD _ BLOCK _ LEN on top of the previous frame address, and the address is incremented to RD _ BASE _ ADDR + RD _ BLOCK _ LEN x (RD _ BLOCK _ NUM-1) back to RD _ BASE _ ADDR.

3. The write address management module 01 in fig. 1 controls generation of a current write request address, and starts from WR _ BASE _ ADDR, updates the current write request address to be an initial address of a next adjacent data block after initiating a write request each time, that is, the current request address plus the length of the data block, and returns to the BASE address after noticing that the maximum value of the data block is reached.

4. The read address management module 04 in fig. 1 controls generation of a current read request address, and starts from RD _ BASE _ ADDR, updates the current read request address to be an initial address of a next adjacent data block after each read request is initiated, that is, the current request address plus the length of the data block, and returns to a BASE address after the maximum value of the data block is reached.

The third step: the write request processing flow comprises the following steps:

1. when data needs to be written into the memory, a frame unit is used for performing incremental cycle counting, for example, ethernet data is usually defined as a block of data by a frame, a data block carried by a write operation is described by a frame of data, each frame of data is numbered by the cycle counting, and the number is added to the initial position of each frame of data, so that the peripheral and the CPU can conveniently manage messages.

The CPU performs cycle counting on the number of frames in the processed memory, and issues the count value to the peripheral periodically, and the write cell management module 03 in fig. 1 performs cell calculation by using the count value and the frame cycle count value maintained by itself, determines that the DMA write operation to be initiated does not cover the unprocessed frame, and then triggers the DMA write operation.

3. The write cell calculation strategy is: the difference between the peripheral initiated message number count and the processed message cycle count informed by the CPU is smaller than the BLOCK number WR _ BLOCK _ NUM corresponding to the write cycle cache, and if the relation is established, the cell is considered to be enough, otherwise, the cell is not enough, the DMA write can be triggered only if the cell condition is satisfied and the CPU needs to update the processed cycle count.

4. The write request management module 02 in fig. 1 is responsible for collecting: if the current write request address of the write address management module 01 and the cell condition of the write cell management module 03 are satisfied, the data to be written into the memory is packaged in a DMA write request format.

5. When the peripheral actively initiates the DMA write operation, cells need to be considered, when the processing rate of the CPU to the existing data in the memory is too low, namely the increment rate of the processed cycle count informed by the CPU is lower, the rate of initiating the DMA write is also lower, otherwise, the rate of initiating the DMA write is not inhibited by the cells. To improve the efficiency of data interaction, the CPU needs to process the written data as soon as possible. The CPU does not need to monitor the memory at regular time, and the peripheral can actively initiate an interrupt message to the CPU. The process is realized by a write interrupt triggering condition management module 11 and an insertion interrupt and message module 10 in fig. 1, and the implementation mode is as follows:

A. the initiated interrupt message is used as a node, and the whole process is divided into a plurality of time intervals.

B. Within each time slot, the request packet and time are counted separately from the first write request initiated.

C. And triggering interruption when the number of the write request packets in the time gap reaches a specified threshold value or the time length reaches a specified threshold value.

D. After the interruption is triggered, firstly, generating a message carrying the number of the initiated writing request packets, writing the message into a specified message cache, and then generating an interruption message.

E. After receiving the interrupt message, the CPU accesses the message in the message to obtain how many memory blocks can be processed, and then processes the data of the corresponding memory blocks.

The steps are realized by peripheral devices except that the step E is realized by a CPU, wherein the steps A to C are realized in a write interruption triggering condition management module 11, and the step D is realized in an interrupt and message inserting module 10.

The fourth step: and a read request processing flow:

the CPU performs incremental cycle counting on the number of the message frames written into the memory and issues the cycle counting to the peripheral.

2. The read cell management module 06 in fig. 1 manages cells, and includes two types of cells:

A. receiving a data cell: the internal of the external device is provided with enough space for receiving the read response data;

calculating a strategy:

initial cell: the DMA receives one-half the read reply buffer size.

And (3) calculating flow: on the basis of the initial cell, each time a read request is initiated, the length of the read request data is subtracted from the cell, the simple DMA finishes the processing of the read response data and delivers the read response data to a port (which indicates that the data is removed from the DMA cache), and the length of the response data is added to the cell.

And (3) comparison strategy: and each time a read request is initiated, whether the cell value after calculation is greater than 0 or not is judged, and if yes, the cell is enough.

B. Initiating a read request cell: the pending read request address contains valid readable data.

Calculating a strategy:

the peripheral performs increasing cycle counting on the initiated read request, and then the difference between the cycle counting of the written memory frame sent by the CPU and the cycle counting of the initiated read request of the peripheral is more than 0, which indicates that a data block which can be read exists and the cell amount is satisfied.

3. The read request management module 05 in fig. 1 is responsible for collecting: if the current read request address of the read address management module 04 and the cell condition of the read cell management module 06 are satisfied, the memory data is packed in the DMA read request data format when the memory data needs to be read.

4. In fig. 1, the read return message module 07 receives the response message after the DMA read request, and separates data in the response message.

5. When the peripheral initiates a read request, it needs to see whether there is valid data available for reading in the memory, so the CPU needs to write the valid data into the memory in time and send the message frame count written into the memory to the peripheral in time, and in order to ensure the timely operation of the CPU, the peripheral can actively initiate an interrupt message to the CPU. The process is implemented by the read interrupt trigger condition management module 09 and the insert interrupt and message module 08 in fig. 1, and the implementation manner is as follows:

B. In each time interval, the response packet and the time are counted from the first time the read response packet is received.

C. And triggering interruption when the number of the read response packets in the time gap reaches a specified threshold value or the time length reaches a specified threshold value.

D. After the interruption is triggered, firstly, a message carrying the number of the received read response packets is generated (the message is written into a specified message cache), and then an interruption message is generated.

E. After receiving the interrupt message, the CPU accesses the message in the message to obtain the data of how many memory blocks have been read, and then processes the data of the corresponding memory blocks.

The steps are realized by peripheral devices except that the step E is realized by a CPU, wherein the steps A to C are realized in a read interrupt triggering condition management module 09, and the step D is realized in an interrupt inserting and message module 08.

Claims

1. A method for realizing data exchange between peripheral equipment and a CPU (central processing unit) actively comprises a PCIE + DMA framework, wherein the DMA has the functions of realizing address maintenance, interrupt generation, message generation, read-write command generation, read-return data sorting and cell management actively; the method is characterized by comprising the following steps:

(1) in the initialization process, a fixed continuous cache space is distributed by a CPU to the peripheral equipment for the operation of circularly reading and writing data, the continuous cache space is divided into a plurality of small cache spaces with equal length, and the initial address of the continuous cache space and the length of the small cache spaces are informed to the peripheral equipment in a parameter configuration mode, so that the address of each data message to be processed is fixed when the peripheral equipment performs data reading and writing operation; the small cache spaces with continuous equal length form a read/write cycle storage structure;

(2) when the peripheral equipment needs to write data into the memory, the peripheral equipment carries out incremental cyclic numbering on each message, a number value representing a message serial number is embedded into access data, meanwhile, according to an address calculated by a write cyclic storage structure, when a write cell condition calculated by the peripheral equipment is met, a DMA write request operation is initiated to the current address of the cyclic storage structure, a DMA write cell mechanism ensures that the DMA write operation to be initiated does not cover the existing data which is not processed by the CPU, in the DMA write request operation process, the number and time of the written messages are counted, when the access number or an overtime condition is met, the peripheral equipment needs to write message messages into the fixed message memory and initiate interrupt messages to the CPU, and after the CPU receives the interrupt messages, the content of the message messages is read, and the memory is managed according to the content of the message messages; the DMA write unit mechanism: the peripheral equipment carries out cycle counting on the frames written into the memory; meanwhile, the CPU carries out cycle counting on the frames in the processed memory and sends the cycle counting of the processed frames to the peripheral at fixed time; the peripheral equipment subtracts the cycle count corresponding to the current write-in frame from the cycle count of the processed frame issued by the latest CPU, and when the difference value is less than the number of data blocks of the cycle cache corresponding to the write operation, the cell condition is considered to be satisfied, and the current DMA write operation is initiated; otherwise, waiting for the CPU to process the memory frame, updating the processed cycle count value of the CPU, and initiating the current DMA write operation only after the cell condition is established;

(3) when the peripheral needs to read data from the memory, whether to initiate a read request is determined according to a read cell calculated by the peripheral, and the DMA read cell comprises two cells, namely a data receiving cell and a read request initiating cell; the request can be initiated when both cells are satisfied, then DMA read request operation is initiated to the current address of the read cycle storage structure according to the address calculated by the read cycle storage structure, and the peripheral cell mechanism ensures that enough space is provided for receiving read response data; counting the number and time of read messages in the process of DMA reading request operation, when the number of received packets or overtime conditions are met, initiating a message to a fixed message memory, initiating an interrupt message to a CPU, and updating and releasing memory space after the CPU receives the interrupt message.

2. The method for actively realizing data exchange with the CPU by the peripheral device according to claim 1, wherein: the parameters in the step (1) comprise: the starting address of the continuous cache corresponding to the write operation, the data block size of the continuous cache corresponding to the write operation, the data block number of the continuous cache corresponding to the write operation, the starting address of the continuous cache corresponding to the read operation, the data block size of the continuous cache corresponding to the read operation and the data block number of the continuous cache corresponding to the read operation.

3. The method for actively realizing data exchange with the CPU by the peripheral device according to claim 1, wherein: and (3) the DMA write request operation in the step (2) is the starting address of the data block in the continuous cache corresponding to the write operation.

4. The method for actively realizing data exchange with the CPU by the peripheral device according to claim 1, wherein: the DMA read request operation in the step (3) is the starting address of the data block in the continuous cache corresponding to the read operation.

5. The method for actively realizing data exchange with the CPU by the peripheral device according to claim 2, wherein: the starting addresses of the continuous cache data blocks corresponding to the read/write operation are all as follows: adding the length of the data block from the initial address of the last immediately adjacent data block, namely accumulating the length of the data block from the base address to form the initial address of the subsequent data block, and taking care that the address returns to zero after the number of the data blocks is reached.

6. The method for actively realizing data exchange with the CPU by the peripheral device according to claim 1, wherein: the DMA read cell includes two types of cells: receiving a data cell and initiating a read request cell;

receiving data cells to ensure that the peripheral has enough space to receive read response data, and a calculation mechanism: receiving data cells by taking half of the buffer size of the DMA return data stored by the peripheral as an initial value, receiving the data length corresponding to the data cell reading request when initiating the DMA reading request, and receiving the data cells and adding the delivered data length when receiving the DMA reading response data and delivering the DMA reading response data; if the current calculated received data cell is greater than 0, the cell condition is considered to be established;

initiating a read request cell to ensure that an address of an upcoming read request contains valid readable data, the computing mechanism: the peripheral equipment performs cycle counting on the frame initiating the reading of the memory, and simultaneously the CPU performs cycle counting on the frame written into the memory and issues the cycle counting of the written frame to the peripheral equipment at regular time; the peripheral device subtracts the cycle count of the written frame issued by the latest CPU and the cycle count of the current frame to be started to read the memory, and when the difference value is greater than 0, the cell condition is considered to be satisfied;

7. The method for actively realizing data exchange with the CPU by the peripheral device according to claim 1, wherein: in the step (2), when the peripheral needs to write data into the memory, and when the access quantity or the timeout condition is met, the peripheral needs to write a message into the fixed message memory, and initiate an interrupt message to the CPU, the specific steps are as follows:

in each period, starting from the initiation of a first write request, simultaneously counting the write requests and time, triggering interruption when the request count reaches a threshold value or the time count reaches the threshold value, starting a new period, clearing zero both the request count and the time count, starting a new request and the time count from the initiation of the first write request in the new period, and triggering interruption and repeating the steps when at least one of the request and the time count reaches the threshold value;

8. The method for actively realizing data exchange with the CPU by the peripheral device according to claim 1, wherein: in the step (3), when the peripheral needs to read data from the memory, and when the number of received packets or the timeout condition is met, a message needs to be initiated to the fixed message memory, and an interrupt message is initiated to the CPU, the specific steps are as follows:

after the interruption is triggered, firstly generating a message carrying the number of the received and read response packets, and then generating an interruption message; after receiving the interrupt message, the CPU accesses the message in the message, learns how many data of the memory blocks have been read, and processes the data of the corresponding memory block.