CN101059785A - Method for implementing two-dimensional data delivery using DMA controller - Google Patents
Method for implementing two-dimensional data delivery using DMA controller Download PDFInfo
- Publication number
- CN101059785A CN101059785A CN 200610066665 CN200610066665A CN101059785A CN 101059785 A CN101059785 A CN 101059785A CN 200610066665 CN200610066665 CN 200610066665 CN 200610066665 A CN200610066665 A CN 200610066665A CN 101059785 A CN101059785 A CN 101059785A
- Authority
- CN
- China
- Prior art keywords
- address
- register
- catena
- address register
- dma controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Bus Control (AREA)
Abstract
The invention discloses a method for using a DMA controller to realize two-dimension transmission, wherein the DMA controller is arranged with a linked list address register. And the method comprises that valuing each register, arranging source address, target address and linked list to relative registers, according to the address of linked list, storing the values of the object memory space relative to the source address register, the target address register, the linked list address register and the control register into a memory, and the DMA controller reads out the source address from the source address register, to obtain the data stored in the address, and transmit next data with increased addresses until all data in prior memory space are transmitted. The invention uses Scatter/Gather linked list to make DMA controller support two-dimension data transmission.
Description
Technical field
The present invention relates to a kind of dma controller method of computer technology, in particular a kind of method of utilizing dma controller to realize the 2-D data carrying.
Background technology
The basic framework of the dma controller of prior art as shown in Figure 1, it mainly is made up of four modules:
AHB is from the device interface module: this module functions is to be used for disposing dma controller.External program can be provided with the registers group module of dma controller.
AHB main device interface module: this module can be finished to ahb bus and send address, data and control signal, realizes putting into destination address from the source address reading of data.
The registers group module: this module comprises source address register, target address register, control register and some other relevant register.The initial value of source address register is the start address in the source memory space that will visit, and in handling process, the source address that dma controller will be visited the next one is kept in this register; The initial value of target address register is the start address in the target memory space that will visit, and in handling process, the destination address that dma controller will be visited the next one is kept in this register; Control register is used for setting the DMA passage and enables or do not enable, and whether loads start address or the like automatically.
The passage priority block: this module is used to realize the priority judgement of a plurality of logical channels in the dma controller.When receiving the DMA application, this module will be judged the priority of passage, to determine by which passage being initiated to transmit under present case.
On the ahb bus of AMBA agreement, dma controller is as the main device appearance arranged side by side with arm processor, in most of the cases, dma controller can substitute arm processor and carry out data carrying work (comprise memory to memory, storer to peripherals, peripherals to the carrying of the data between storer and the peripherals), thereby guarantee that arm processor stays out of in the concrete data carrying work during executing instruction, thereby improve the work efficiency of arm processor.
The dma controller of widespread use generally all is the carrying of carrying out one-dimensional data on the ahb bus at present, the source address space or the target address space that are dma controller are one section continuous storage space, have only these main registers of source address register, target address register and control register in the registers group module of this dma controller, in the process of data carrying, only need the address value in source address register or the target address register be increased progressively, just can obtain the storage address that the next one will be visited.
Yet in the operating process of reality, the storage space that tends to occur deposit data is a discontinuous address space, such as the deposit data of needs carryings in a plurality of storage space, each storage space home address is continuous, but the address between the storage space is discontinuous, shown in the grey color part among Fig. 2.Obviously, only support the dma controller of one-dimensional data carrying to carry continuously to this data that are stored in a plurality of storage space.
Therefore, prior art has yet to be improved and developed.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of method of utilizing dma controller to carry out the 2-D data carrying, in order to overcome the shortcoming that one-dimensional data carrying dma controller can only be carried the continuation address spatial data.
Technical scheme of the present invention comprises:
A kind of method of utilizing dma controller to realize the 2-D data carrying, it increases in dma controller the catena address register is set, and described method comprises step:
A, give each register assignment, source address, destination address, catena address are set gradually in the relevant register;
B, need the value of the pairing source address register of storage space, target address register, catena address register and the control register of carrying to deposit in the storer with every according to the address of catena;
C, described dma controller take out source address from source address register, obtain the data that preserve this address, and address increment carries next data, and the data carrying up to the current storage space finishes;
D, described dma controller go to obtain the value of the source address register, target address register, catena address register and the control register that characterize next block storage space by the value in the catena address register;
Carrying repeatedly is 0 up to the value of current catena address register.
Described method, wherein, a catena in the described catena address register all comprises 4 word, arranges in the following manner:
The value of a, source address register is used to write down the start address in next source memory space;
The value of b, target address register is used to write down the start address of next target storage space;
The value of c, catena address register is used to write down next catena address;
The value of d, control register is used to write down the value of the control register when carrying out the carrying of data next time.
Described method, wherein, described dma controller is visited this 4 word by the address that provides in the catena address register in the DMA passage in storage space, and these 4 word are in storage space continuous blow-down.
A kind of method of utilizing dma controller to realize the 2-D data carrying provided by the present invention owing to adopt the method for Scatter/Gather catena, makes dma controller support the 2-D data carrying.
Description of drawings
Fig. 1 is the basic framework synoptic diagram of the dma controller of prior art;
Fig. 2 is a nonconnected storage space synoptic diagram in the communication technology of prior art;
Fig. 3 is the Scatter/Gather catena method of work synoptic diagram of the inventive method;
Fig. 4 is the Scatter/Gather catena method of work data carrying process flow diagram of the inventive method.
Embodiment
Below in conjunction with accompanying drawing, will be described in more detail concrete preferred embodiment of the present invention.
The of the present invention utilization in the method that dma controller realizes the 2-D data carrying, the Scatter/Gather catena method that adopts can be used for the data that are stored in a plurality of storage space are carried continuously, its concrete working method as shown in Figure 3, except the original source address register of dma controller, target address register and control register, increase the catena address register in addition again.
Being described below of this catena address register: this register is used for setting the next catena address of this DMA passage, after the data carrying in current storage space finished, dma controller can go to obtain the value of the source address register, target address register, catena address register and the control register that characterize next block storage space by this catena address.When the value of this register is 0, show that the data carrying finishes.
From top description as can be seen, each catena all comprises 4 word (32), and these 4 word can arrange in the following manner:
The value of a, source address register (start address in next source memory space)
The value of b, target address register (start address of next target storage space)
The value of c, catena address register (next catena address)
The value of d, control register (value of the control register when carrying out data carrying next time)
Dma controller of the present invention is visited this 4 word by the address that provides in the catena address register in the DMA passage in storage space, so these 4 word must be continuous blow-down in storage space.
The concrete steps of the inventive method comprise:
A, give register assignment, source address, destination address, catena address are set gradually in the relevant register.
B, need the value of the pairing source address register of storage space, target address register, catena address register and the control register of carrying to deposit in the storer with every according to the address of catena.
C, when dma controller begins to carry data, at first from source address register, take out source address, obtain the data that preserve this address, address increment is carried next data then, data carrying up to the current storage space finishes, and this moment, dma controller can go to obtain the value of the source address register, target address register, catena address register and the control register that characterize next block storage space by the value in the catena address register.
Carrying and so forth is 0 up to the value of current catena address register, represents that promptly all data carryings finish.Concrete data carrying flow process as shown in Figure 4.
By the method for above-mentioned Scatter/Gather catena, just can reach the purpose of using dma controller to finish the 2-D data carrying.
A specific embodiment of the present invention below is described:
Dma controller need be from two discontinuous storage space carrying data, and the start address of supposing first source memory space is 0x00000000, and the start address in target memory space is 0x10000000; The start address in second source memory space is 0x00010000, and the start address in target memory space is 0x10010000; The degree of depth in every block storage space is 10, and data width is 32.
The start address in second source memory space is 0x00010000, and the start address in target memory space is 0x10010000, and catena address register value is 0.These values are stored in the storer according to above-mentioned order, and start address is 0x20000000.
At first give register assignment, with source address 0x00000000 write in the source memory address, destination address 0x10000000 writes target address register, catena address 0x20000000 is write the catena address register.
Dma controller takes out source address 0x00000000 from source address register, obtain the data that preserve this address, and address increment is 0x00000004 then, obtains next data again, and the data carrying up to the current storage space finishes.
The dma controller of the inventive method goes to obtain the value of the source address register, target address register, catena address register and the control register that characterize next block storage space by the value 0x20000000 in the catena address register.The value of the source address register that obtains is that the value of 0x00010000, target address register is 0x10010000, and the value of catena address register is 0.
Repeat aforesaid operations, finish up to the data carrying of this storage space, this moment, the value of catena address register was 0, represented that all data have all been carried to finish.
Thus, the inventive method has realized the carrying to 2-D data, and it realizes simple.But should be understood that above-mentioned description at specific embodiment is comparatively detailed, can not therefore be interpreted as the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (3)
1, a kind of method of utilizing dma controller to realize the 2-D data carrying, it increases in dma controller the catena address register is set, and described method comprises step:
A, give each register assignment, source address, destination address, catena address are set gradually in the relevant register;
B, need the value of the pairing source address register of storage space, target address register, catena address register and the control register of carrying to deposit in the storer with every according to the address of catena;
C, described dma controller take out source address from source address register, obtain the data that preserve this address, and address increment carries next data, and the data carrying up to the current storage space finishes;
D, described dma controller go to obtain the value of the source address register, target address register, catena address register and the control register that characterize next block storage space by the value in the catena address register;
Carrying repeatedly is 0 up to the value of current catena address register.
2, method according to claim 1 is characterized in that, a catena in the described catena address register all comprises 4 word, arranges in the following manner:
The value of a, source address register is used to write down the start address in next source memory space;
The value of b, target address register is used to write down the start address of next target storage space;
The value of c, catena address register is used to write down next catena address;
The value of d, control register is used to write down the value of the control register when carrying out the carrying of data next time.
3, method according to claim 2 is characterized in that, described dma controller is visited this 4 word by the address that provides in the catena address register in the DMA passage in storage space, and these 4 word are in storage space continuous blow-down.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610066665 CN101059785A (en) | 2006-04-17 | 2006-04-17 | Method for implementing two-dimensional data delivery using DMA controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610066665 CN101059785A (en) | 2006-04-17 | 2006-04-17 | Method for implementing two-dimensional data delivery using DMA controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101059785A true CN101059785A (en) | 2007-10-24 |
Family
ID=38865895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610066665 Pending CN101059785A (en) | 2006-04-17 | 2006-04-17 | Method for implementing two-dimensional data delivery using DMA controller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101059785A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102314400A (en) * | 2011-09-27 | 2012-01-11 | 广东威创视讯科技股份有限公司 | Method and device for dispersing converged DMA (Direct Memory Access) |
| CN108228497A (en) * | 2018-01-11 | 2018-06-29 | 湖南国科微电子股份有限公司 | A kind of DMA transfer method based on sgl chained lists |
| CN108804356A (en) * | 2017-04-26 | 2018-11-13 | 上海寒武纪信息科技有限公司 | Data transmission device and method |
| CN109800194A (en) * | 2019-01-24 | 2019-05-24 | 湖南国科微电子股份有限公司 | SDIO interface data transmission method and device based on linux system |
| CN112540730A (en) * | 2020-12-14 | 2021-03-23 | 无锡众星微系统技术有限公司 | Dynamically reconfigurable DMA array |
| CN112835828A (en) * | 2019-11-25 | 2021-05-25 | 美光科技公司 | Direct Memory Access (DMA) commands for non-sequential source and destination memory addresses |
| CN114785748A (en) * | 2022-06-21 | 2022-07-22 | 苏州领慧立芯科技有限公司 | DMA control system and method for image transmission |
-
2006
- 2006-04-17 CN CN 200610066665 patent/CN101059785A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102314400A (en) * | 2011-09-27 | 2012-01-11 | 广东威创视讯科技股份有限公司 | Method and device for dispersing converged DMA (Direct Memory Access) |
| CN102314400B (en) * | 2011-09-27 | 2014-12-24 | 广东威创视讯科技股份有限公司 | Method and device for dispersing converged DMA (Direct Memory Access) |
| CN108804356A (en) * | 2017-04-26 | 2018-11-13 | 上海寒武纪信息科技有限公司 | Data transmission device and method |
| CN108228497A (en) * | 2018-01-11 | 2018-06-29 | 湖南国科微电子股份有限公司 | A kind of DMA transfer method based on sgl chained lists |
| CN109800194A (en) * | 2019-01-24 | 2019-05-24 | 湖南国科微电子股份有限公司 | SDIO interface data transmission method and device based on linux system |
| CN112835828A (en) * | 2019-11-25 | 2021-05-25 | 美光科技公司 | Direct Memory Access (DMA) commands for non-sequential source and destination memory addresses |
| CN112835828B (en) * | 2019-11-25 | 2024-05-24 | 美光科技公司 | Direct Memory Access (DMA) commands for non-contiguous source and destination memory addresses |
| CN112540730A (en) * | 2020-12-14 | 2021-03-23 | 无锡众星微系统技术有限公司 | Dynamically reconfigurable DMA array |
| CN112540730B (en) * | 2020-12-14 | 2022-02-08 | 无锡众星微系统技术有限公司 | Dynamically reconfigurable DMA array |
| CN114785748A (en) * | 2022-06-21 | 2022-07-22 | 苏州领慧立芯科技有限公司 | DMA control system and method for image transmission |
| CN114785748B (en) * | 2022-06-21 | 2022-09-16 | 苏州领慧立芯科技有限公司 | DMA control system and method for image transmission |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101059785A (en) | Method for implementing two-dimensional data delivery using DMA controller | |
| CN1252605C (en) | Method for rearranging several data access instructions and its device | |
| CN1499530A (en) | Method and device for effectively allowing failure sequency writing processing in ono-volatile memory system | |
| CN1991810A (en) | A dma controller with multiple intra-channel software request support | |
| CN101038532A (en) | Data storage device and method thereof | |
| CN1222951C (en) | Real-time processing method for flash storage | |
| CN1652253A (en) | Memory card and semiconductor device | |
| CN1908903A (en) | System and method for executing job step, and computer product | |
| CN101046786A (en) | DMA controller and transmission method of implementing high efficient DMA transmission | |
| CN101030183A (en) | Direct memory access controller and method for realizing memory batch processing | |
| CN1645352A (en) | Method for managing data in an array processor and array processor carrying out this method | |
| KR20130034450A (en) | Storage device and driving method thereof | |
| CN1752916A (en) | Controller of magnetic disk array and its working method | |
| CN1286029C (en) | Device for controlling interior storage of chip and its storage method | |
| CN101043300A (en) | Resending control circuit, sending device, resending control method and resending control program | |
| CN100342360C (en) | Access apparatus and method for direct memory | |
| CN1845087A (en) | Interrupt handling method and interrupt handling apparatus | |
| CN101079753A (en) | A multi-link packet snapping system, method and network audit system | |
| CN101059784A (en) | Method for implementing two-dimensional data delivery using DMA controller | |
| CN1152330C (en) | Maintain method for remote node to read local memory and its application device | |
| CN1459112A (en) | Storage device | |
| CN101035187A (en) | Data buffer method, vertical zooming circuit and terminal | |
| CN200947355Y (en) | Data quick-fetching device of flash memory | |
| CN1808433A (en) | Quick and safe real-time database access method | |
| CN1866232A (en) | Direct memory access method for data of secure digital memory card and interface circuit therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |